Bureaucrats, dave_user, Administrators
8,154
edits
Changes
→J2 even pins (2 to 140)
{{InfoBoxBottom}}
==IntroductionPinout table==
This chapter contains the pinout description of the Bora module, grouped in six tables (two – odd and even pins – for each connector) that report the pin mapping of the three 140-pin Bora connectors.
Each row in the pinout tables contains the following information:
|J1.117||DGND||DGND||n.a.||||||||
|-
|J1.119||SPI0_DQ3/MODE0/NAND_IO0||CPU.PS_MIO5_500||A6|||||||| This signal is internally pulled up or down by 20kOhm resistor to select proper depending on order code (selecting then the bootstrap configuration.)
|-
|J1.121||SPI0_DQ2/MODE2/NAND_IO2||CPU.PS_MIO4_500||B7|||||||| This signal is internally pulled up or down by 20kOhm resistor to select proper depending on order code (selecting then the bootstrap configuration.)
|-
|J1.123||SPI0_DQ1/MODE1/NAND_WE||CPU.PS_MIO3_500||D6|||||||| This signal is internally pulled up or down by 20kOhm resistor to select proper depending on order code (selecting then the bootstrap configuration.)
|-
|J1.125||SPI0_DQ0/MODE3/NAND_ALE||CPU.PS_MIO2_500||B8|||||||| This signal is internally pulled up or down by 20kOhm resistor to select proper depending on order code (selecting then the bootstrap configuration.)
|-
|J1.127||DGND||DGND||n.a.||||||||
|-
|J1.129||SPI0_SCLK/MODE4/NAND_IO1||CPU.PS_MIO6_500||A5|||||||| This signal is internally pulled up or down by 20kOhm resistor to select proper depending on order code (selecting then the bootstrap configuration.)
|-
|J1.131||NAND_BUSY||CPU.PS_MIO14_500||C5||||||||
|J1.134||NAND_IO7||CPU.PS_MIO12_500<br>NAND.I/O7||D9<br>44||||||||
|-
|J1.136||NAND_RD_B/VCFG1||CPU.PS_MIO8_500<br>NAND.~RE||D5<br>8|||||||| This signal is internally pulled up or down by 20kOhm resistor to select proper depending on order code (selecting then the bootstrap configuration)
|-
|J1.138||NAND_CLE/VCFG0||CPU.PS_MIO7_500<br>NAND.CLE||D8<br>16|||||||| This signal is internally pulled up or down by 20kOhm resistor to select proper depending on order code (selecting then the bootstrap configuration)
|-
|J1.140||DGND||DGND||n.a.||||||||
|J2.88||DGND||DGND||n.a.||||||||
|-
|J2.90||FPGA_INIT_B||FPGA.INIT_B_0||R10||||||||Place external 4.7 kΩ (or stronger) pull-up resistor to BOARD_PGOOD driven +3.3V supplyFor more further details , please refer to Table 2-4 on [http:[PL_initialization_signals_(Bora/BoraX/www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf 7 Series FPGAs ConfigurationBoraLite) | PL initialization signals]]
|-
|J2.92||FPGA_PROGRAM_B||FPGA.PROGRAM_B_0||L6||||||||Place external 4.7 kΩ For further details, please refer to [[PL_initialization_signals_(or strongerBora/BoraX/BoraLite) pull-up resistor to BOARD_PGOOD driven +3.3V supply| PL initialization signals]]
|-
|J2.94||FPGA_DONE||FPGA.DONE_0||R11||||||||Place external 300Ω pull-up resistor to BOARD_PGOOD driven +3.3V supply For more further details , please refer to Table 2-4 on [http://www.xilinx.com/support/documentation[PL_initialization_signals_(Bora/user_guidesBoraX/ug470_7Series_Config.pdf 7 Series FPGAs ConfigurationBoraLite) | PL initialization signals]]
|-
|J2.96||WD_SET2||WDT.SET2||6||||||||
