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Pinout (Bora)

1,015 bytes removed, 15:48, 21 December 2020
→‎J2 even pins (2 to 140)
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==IntroductionPinout table==
This chapter contains the pinout description of the Bora module, grouped in six tables (two – odd and even pins – for each connector) that report the pin mapping of the three 140-pin Bora connectors.
Each row in the pinout tables contains the following information:
{| class="wikitable" {| {{table}}
| align="center" style="background:#f0f0f0;" align="center"|'''Pin'''| align="center" style="background:#f0f0f0;" align="center"|'''Pin Name'''| align="center" style="background:#f0f0f0;" align="center"|'''Internal Connections'''| align="center" style="background:#f0f0f0;" align="center"|'''Ball/pin #'''| align="center" style="background:#f0f0f0;" align="center"|'''Supply Group'''| align="center" style="background:#f0f0f0;" align="center"|'''Type'''| align="center" style="background:#f0f0f0;" align="center"|'''Voltage'''| align="center" style="background:#f0f0f0;" align="center"|'''Note'''
|-
|J1.1||DGND||DGND||n.a.||||||||
|J1.117||DGND||DGND||n.a.||||||||
|-
|J1.119||SPI0_DQ3/MODE0/NAND_IO0||CPU.PS_MIO5_500||A6|||||||| This signal is internally pulled up or down by 20kOhm resistor to select proper depending on order code (selecting then the bootstrap configuration.)
|-
|J1.121||SPI0_DQ2/MODE2/NAND_IO2||CPU.PS_MIO4_500||B7|||||||| This signal is internally pulled up or down by 20kOhm resistor to select proper depending on order code (selecting then the bootstrap configuration.)
|-
|J1.123||SPI0_DQ1/MODE1/NAND_WE||CPU.PS_MIO3_500||D6|||||||| This signal is internally pulled up or down by 20kOhm resistor to select proper depending on order code (selecting then the bootstrap configuration.)
|-
|J1.125||SPI0_DQ0/MODE3/NAND_ALE||CPU.PS_MIO2_500||B8|||||||| This signal is internally pulled up or down by 20kOhm resistor to select proper depending on order code (selecting then the bootstrap configuration.)
|-
|J1.127||DGND||DGND||n.a.||||||||
|-
|J1.129||SPI0_SCLK/MODE4/NAND_IO1||CPU.PS_MIO6_500||A5|||||||| This signal is internally pulled up or down by 20kOhm resistor to select proper depending on order code (selecting then the bootstrap configuration.)
|-
|J1.131||NAND_BUSY||CPU.PS_MIO14_500||C5||||||||
{| class="wikitable" {| {{table}}
| align="center" style="background:#f0f0f0;" align="center"|'''Pin'''| align="center" style="background:#f0f0f0;" align="center"|'''Pin Name'''| align="center" style="background:#f0f0f0;" align="center"|'''Internal Connections'''| align="center" style="background:#f0f0f0;" align="center"|'''Ball/pin #'''| align="center" style="background:#f0f0f0;" align="center"|'''Supply Group'''| align="center" style="background:#f0f0f0;" align="center"|'''Type'''| align="center" style="background:#f0f0f0;" align="center"|'''Voltage'''| align="center" style="background:#f0f0f0;" align="center"|'''Note'''
|-
|J1.2||VDDIO_BANK35||FPGA.VCCO_35||C19<br>F18<br>H14<br>J17<br>K20<br>M16||||||||
|J1.134||NAND_IO7||CPU.PS_MIO12_500<br>NAND.I/O7||D9<br>44||||||||
|-
|J1.136||NAND_RD_B/VCFG1||CPU.PS_MIO8_500<br>NAND.~RE||D5<br>8|||||||| This signal is internally pulled up or down by 20kOhm resistor to select proper depending on order code (selecting then the bootstrap configuration.)
|-
|J1.138||NAND_CLE/VCFG0||CPU.PS_MIO7_500<br>NAND.CLE||D8<br>16|||||||| This signal is internally pulled up or down by 20kOhm resistor to select proper depending on order code (selecting then the bootstrap configuration.)
|-
|J1.140||DGND||DGND||n.a.||||||||
{| class="wikitable" {| {{table}}
| align="center" style="background:#f0f0f0;" align="center"|'''Pin'''| align="center" style="background:#f0f0f0;" align="center"|'''Pin Name'''| align="center" style="background:#f0f0f0;" align="center"|'''Internal Connections'''| align="center" style="background:#f0f0f0;" align="center"|'''Ball/pin #'''| align="center" style="background:#f0f0f0;" align="center"|'''Supply Group'''| align="center" style="background:#f0f0f0;" align="center"|'''Type'''| align="center" style="background:#f0f0f0;" align="center"|'''Voltage'''| align="center" style="background:#f0f0f0;" align="center"|'''Note'''
|-
|J2.1||DGND||DGND||n.a.||||||||
|J2.113||RTC_VBAT||RTC.VBAT||6||||||||
|-
|J2.115||VBAT||CPU.VCCBATT_0||F11||||||||This pin is connected to the VCCBATT_0 (for the battery-backed RAM - BBRAM) pin of the Zynq SOC. For additional information, please refer to the Zynq datasheet and TRM.
|-
|J2.117||DGND||DGND||n.a.||||||||
{| class="wikitable" {| {{table}}
| align="center" style="background:#f0f0f0;" align="center"|'''Pin'''| align="center" style="background:#f0f0f0;" align="center"|'''Pin Name'''| align="center" style="background:#f0f0f0;" align="center"|'''Internal Connections'''| align="center" style="background:#f0f0f0;" align="center"|'''Ball/pin #'''| align="center" style="background:#f0f0f0;" align="center"|'''Supply Group'''| align="center" style="background:#f0f0f0;" align="center"|'''Type'''| align="center" style="background:#f0f0f0;" align="center"|'''Voltage'''| align="center" style="background:#f0f0f0;" align="center"|'''Note'''
|-
| J2.2||DGND||DGND||-n.a.||-||G||-||Digital ground
|-
| J2.4||IO_L9P_T1_DQS_34||FPGA.IO_L9P_T1_DQS_34||J3T16||Bank 34||I/O||User defined||
|-
| J2.6||IO_L9N_T1_DQS_34||FPGA.IO_L9N_T1_DQS_34||K2U17||Bank 34||I/O||User defined||
|-
| J2.8||IO_L7P_T1_34||FPGA.IO_L7P_T1_34||J5Y16||Bank 34||I/O||User defined||
|-
| J2.10||IO_L7N_T1_34||FPGA.IO_L7N_T1_34||K5Y17||Bank 34||I/O||User defined||
|-
| J2.12||DGND||DGND||-n.a.||-||G||-||Digital ground
|-
| J2.14||IO_L5P_T0_34||FPGA.IO_L5P_T0_34||N8T14||Bank 34||I/O||User defined||
|-
| J2.16||IO_L5N_T0_34||FPGA.IO_L5N_T0_34||P8T15||Bank 34||I/O||User defined||
|-
| J2.18||IO_L4P_T0_34||FPGA.IO_L4P_T0_34||L6V12||Bank 34||I/O||User defined||
|-
| J2.20||IO_L4N_T0_34||FPGA.IO_L4N_T0_34||M6W13||Bank 34||I/O||User defined||
|-
| J2.22||DGND||DGND||-n.a.||-||G||-||Digital ground
|-
| J2.24||IO_L24P_T3_34||FPGA.IO_L24P_T3_34||P7P15||Bank 34||I/O||User defined||
|-
| J2.26||IO_L24N_T3_34||FPGA.IO_L24N_T3_34||R7P16||Bank 34||I/O||User defined||
|-
| J2.28||IO_L23P_T3_34||FPGA.IO_L23P_T3_34||R5N17||Bank 34||I/O||User defined||
|-
| J2.30||IO_L23N_T3_34||FPGA.IO_L23N_T3_34||R4P18||Bank 34||I/O||User defined||
|-
| J2.32||DGND||DGND||-n.a.||-||G||-||Digital ground
|-
| J2.34||IO_L20P_T3_34||FPGA.IO_L20P_T3_34||P6T17||Bank 34||I/O||User defined||
|-
| J2.36||IO_L20N_T3_34||FPGA.IO_L20N_T3_34||P5R18||Bank 34||I/O||User defined||
|-
| J2.38||IO_L1P_T0_34||FPGA.IO_L1P_T0_34||J8T11||Bank 34||I/O||User defined||
|-
| J2.40||IO_L1N_T0_34||FPGA.IO_L1N_T0_34||K8T10||Bank 34||I/O||User defined||
|-
| J2.42||DGND||DGND||-n.a.||-||G||-||Digital ground
|-
| J2.44||IO_L17P_T2_34||FPGA.IO_L17P_T2_34||R3Y18||Bank 34||I/O||User defined||
|-
| J2.46||IO_L17N_T2_34||FPGA.IO_L17N_T2_34||R2Y19||Bank 34||I/O||User defined||
|-
| J2.48||IO_L16P_T2_34||FPGA.IO_L16P_T2_34||N1V20||Bank 34||I/O||User defined||
|-
| J2.50||IO_L16N_T2_34||FPGA.IO_L16N_T2_34||P1W20||Bank 34||I/O||User defined||
|-
| J2.52||DGND||DGND||-n.a.||-||G||-||Digital ground
|-
| J2.54||IO_L14P_T2_SRCC_34||FPGA.IO_L14P_T2_SRCC_34||U2N20||Bank 34||I/O||User defined||
|-
| J2.56||IO_L14N_T2_SRCC_34||FPGA.IO_L14N_T2_SRCC_34||U1P20||Bank 34||I/O||User defined||
|-
| J2.58||DGND||DGND||-n.a.||-||G||-||Digital ground
|-
| J2.60||IO_L12P_T1_MRCC_34||FPGA.IO_L12P_T1_MRCC_34||L5U18||Bank 34||I/O||User defined||
|-
| J2.62||IO_L12N_T1_MRCC_34||FPGA.IO_L12N_T1_MRCC_34||L4U19||Bank 34||I/O||User defined||
|-
| J2.64||DGND||DGND||-n.a.||-||G||-||Digital ground
|-
| J2.66||VDDIO_BANK34||FPGAN.C.VCCO_34||-Not Connected||-||R1n.a.||Bank 34||S||User defined||Bank34 I/O Power Supply
|-
| J2.68||VDDIO_BANK34N.C.||FPGA.VCCO_34Not Connected||R1n.a.||Bank 34||S||User defined||Bank34 I/O Power Supply
|-
| J2.70||VDDIO_BANK34N.C.||FPGA.VCCO_34Not Connected||K6R1n.a.||Bank 34||S||User defined||Bank34 I/O Power Supply
|-
| J2.72||VDDIO_BANK34N.C.||FPGA.VCCO_34Not Connected||K6R1n.a.||Bank 34||S||User defined||Bank34 I/O Power Supply
|-
| J2.74||RFUN.C.||-Not Connected||-n.a.||-||-||-||Reserved for future use. Must be left floating.
|-
| J2.76||RFUN.C.||-Not Connected||-n.a.||-||-||-||Reserved for future use. Must be left floating.
|-
| J2.78||RFUN.C.||-Not Connected||-n.a.||-||-||-||Reserved for future use. Must be left floating.
|-
| J2.80||JTAG_TDO||CPU.TDO_0||G9F6||BANK 0||O||3.3V||
|-
| J2.82||JTAG_TDI||CPU.TDI_0||H9G6||BANK 0||I||3.3V||
|-
| J2.84||JTAG_TMS||CPU.TMS_0||H10J6||BANK 0||I||3.3V||
|-
| J2.86||JTAG_TCK||CPU.TCK_0||H11F9||BANK 0||I||3.3V||
|-
| J2.88||DGND||DGND||-n.a.||-||G||-||Digital ground
|-
| J2.90||FPGA_INIT_B||FPGA.INIT_B_0||T8R10|||BANK 0||I/O||3.3V|For further details, please refer to [[PL_initialization_signals_(Bora/BoraX/BoraLite) |PL initialization signals]]
|-
| J2.92||FPGA_PROGRAM_B||FPGA.PROGRAM_B_0||V10L6||BANK 0||I||3.3V||For further details, please refer to [[PL_initialization_signals_(Bora/BoraX/BoraLite) | PL initialization signals]] (10 kΩ pull-up resistor is already mounted on BORA module)
|-
| J2.94||FPGA_DONE||FPGA.DONE0DONE_0||T10R11|||BANK 0||I/O||3.3V|For further details, please refer to [[PL_initialization_signals_(Bora/BoraX/BoraLite) |PL initialization signals]]
|-
| J2.96||WD_SET2||WDT.SET2||6||3.3V||I||3.3V||
|-
| J2.98||WD_SET1||WDT.SET1||5||3.3V||I||3.3V||
|-
| J2.100||WD_SET0||WDT.SET0||4||3.3V||I||3.3V||
|-
| J2.102||DGND||DGND||-n.a.||-||G||-||Digital ground
|-
| J2.104||PS_MIO50_501||CPU.PS_MIO50_501<br>USBOTG.RESETB||D10B13<br>22||BANK 501||I/O||1.8V||For further details, please refer to [[Reset_scheme_(BoraXpressBora)#PS_MIO50_501_.28J2.104.29 | Reset_scheme_(BoraXpressBora)#PS_MIO50_501]]
|-
| J2.106||PS_MIO51_501||CPU.PS_MIO51_501<br>ETHPHY1GB.RESET_N||C13B9<br>42||BANK 501||I/O||1.8V||For further details, please refer to [[Reset_scheme_(BoraXpressBora)#PS_MIO51_501_.28J2.106.29 | Reset_scheme_(BoraXpressBora)#PS_MIO51_501 ]]
|-
| J2.108||SOM_PGOODBOARD_PGOOD||SOM_PGOOD_LOGICPSUSWITCHFPGABANK13.OUT||nON<br>PSUSWITCHFPGABANK35.ON<br>PSUSWITCHFPGABANK500/34.ON<br>PSUSWITCHFPGABANK501.aON<br>DDRVREFREGULATOR.PGOOD||3.3V<br>3<br>3<br>3<br>9||||O||3.3V||Internally connected to DGND via 100K resistor
|-
| J2.110||CB_PWR_GOOD||1.0VREGULATOR1V0REGULATOR.ENABLESOM_PGOOD_LOGIC.IN||n.a.||3.3VIN||I||3.3V||Internally connected to 3.3VIN via 10K resistor
|-
| J2.112||SYS_RSTnSYS_RSTN||CPU.PS_SRST_B_501 <br>MTR.~RST||C14B10<br>5||BANK 501||I||1.8V||Internally connected to 1.8V via 20K resistor
|-
| J2.114||PORSTnPORSTN||CPU.PS_POR_B_500SV1.~RSTSV2.~RSTWD.~WDONOR.~RESET/RFU||B18557A4C7||BANK 500||I/O||3.3V||Internally connected to 3.3VIN via 2.2K resistorFor further details, please refer to [[Reset_scheme_(BoraXpress)#PORSTn_.28J2.114.29 | Reset_scheme_(BoraXpress)#PORSTn ]]
|-
| J2.116||MRSTnMRSTN||SV1MTR.~MR||6||3.3VIN||I||3.3V||Internally connected to 3.3VIN via 2.2K resistorFor further details, please refer to [[Reset_scheme_(BoraXpress)#MRSTn_.28J2.116.29 | Reset_scheme_(BoraXpress)#MRSTn ]]
|-
| J2.118||DGND||DGND||-n.a.||-||G||-||Digital ground
|-
| J2.120||3.3VIN||+3.3VIN3 V||-n.a.||3.3VIN||S||+3.3V||SOM Power Supply
|-
| J2.122||3.3VIN||+3.3VIN3 V||-n.a.||3.3VIN||S||+3.3V||SOM Power Supply
|-
| J2.124||DGND||DGND||-n.a.||-||G||-||Digital ground
|-
| J2.126||3.3VIN||+3.3VIN3 V||-n.a.||3.3VIN||S||+3.3V||SOM Power Supply
|-
| J2.128||3.3VIN||+3.3VIN3 V||-n.a.||3.3VIN||S||+3.3V||SOM Power Supply
|-
| J2.130||3.3VIN||+3.3VIN3 V||-n.a.||3.3VIN||S||+3.3V||SOM Power Supply
|-
| J2.132||3.3VIN||+3.3VIN3 V||-n.a.||3.3VIN||S||+3.3V||SOM Power Supply
|-
| J2.134||3.3VIN||+3.3VIN3 V||-n.a.||3.3VIN||S||+3.3V||SOM Power Supply
|-
| J2.136||3.3VIN||+3.3VIN3 V||-n.a.||3.3VIN||S||+3.3V||SOM Power Supply
|-
| J2.138||3.3VIN||+3.3VIN3 V||-n.a.||3.3VIN||S||+3.3V||SOM Power Supply
|-
| J2.140||DGND||DGND||-n.a.||-||G||-||Digital ground
|-
|}
{| class="wikitable" {| {{table}}
| align="center" style="background:#f0f0f0;" align="center"|'''Pin'''| align="center" style="background:#f0f0f0;" align="center"|'''Pin Name'''| align="center" style="background:#f0f0f0;" align="center"|'''Internal Connections'''| align="center" style="background:#f0f0f0;" align="center"|'''Ball/pin #'''| align="center" style="background:#f0f0f0;" align="center"|'''Supply Group'''| align="center" style="background:#f0f0f0;" align="center"|'''Type'''| align="center" style="background:#f0f0f0;" align="center"|'''Voltage'''| align="center" style="background:#f0f0f0;" align="center"|'''Note'''
|-
|J3.1||N.C.||Not Connected||n.a.||||||||
{| class="wikitable" {| {{table}}
| align="center" style="background:#f0f0f0;" align="center"|'''Pin'''| align="center" style="background:#f0f0f0;" align="center"|'''Pin Name'''| align="center" style="background:#f0f0f0;" align="center"|'''Internal Connections'''| align="center" style="background:#f0f0f0;" align="center"|'''Ball/pin #'''| align="center" style="background:#f0f0f0;" align="center"|'''Supply Group'''| align="center" style="background:#f0f0f0;" align="center"|'''Type'''| align="center" style="background:#f0f0f0;" align="center"|'''Voltage'''| align="center" style="background:#f0f0f0;" align="center"|'''Note'''
|-
|J3.2||N.C.||Not Connected||n.a.||||||||
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