Changes

Pinout (Bora)

8,038 bytes added, 15:48, 21 December 2020

→‎J2 even pins (2 to 140)

==~~Introduction~~Pinout table==

This chapter contains the pinout description of the Bora module, grouped in six tables (two – odd and even pins – for each connector) that report the pin mapping of the three 140-pin Bora connectors.

Each row in the pinout tables contains the following information:

{| class="wikitable" {| {{table}}

|-

|J1.1||DGND||DGND||n.a.||||||||

|J1.71||XADC_AGND||FPGA.GNDADC_0||J10||||||||

|-

|J1.73||~~PS_MIO33_501~~PS_MIO45_501 ||CPU.~~PS_MIO33_501~~PS_MIO45_501||~~D15~~B15||||||||

|-

|J1.75||~~PS_MIO32_501~~PS_MIO44_501||CPU.~~PS_MIO32_501~~PS_MIO44_501||~~A14~~F13||||||||

|-

|J1.77||~~PS_MIO31_501~~PS_MIO43_501||CPU.~~PS_MIO31_501~~PS_MIO43_501||~~E16~~A9||||||||

|-

|J1.79||~~PS_MIO30_501~~PS_MIO42_501||CPU.~~PS_MIO30_501~~PS_MIO42_501||~~C15~~E12||||||||

|-

|J1.81||~~PS_MIO29_501~~PS_MIO41_501||CPU.~~PS_MIO29_501~~PS_MIO41_501||~~C13~~C17||||||||

|-

|J1.83||DGND||DGND||n.a.||||||||

|-

|J1.85||~~PS_MIO28_501~~PS_MIO40_501||CPU.~~PS_MIO28_501~~PS_MIO40_501||~~C16~~D14||||||||

|-

|J1.87||ETH_MDIO||CPU.PS_MIO53_501 LAN.MDIO||C11 37||||||||

|-

|J1.89||ETH_MDC||CPU.PS_MIO12_501 LAN.MDC||C10 36||||||||

|-

|J1.91||ETH_LED1||LAN.LED1 / PME_N1||17||||||||

|J1.105||ETH_TXRX0_P||LAN.TXRXP_A||2||||||||

|-

|J1.107||DVDDH||LAN.DVDDH||1716 34 3940||||||||

|-

|J1.109||N.C.||Not Connected||n.a.||||||||

|J1.117||DGND||DGND||n.a.||||||||

|-

|J1.119||SPI0_DQ3/MODE0/NAND_IO0||CPU.PS_MIO5_500||A6||||||||This signal is internally pulled up or down by 20kOhm resistor depending on order code (selecting then the bootstrap configuration)

|-

|J1.121||SPI0_DQ2/MODE2/NAND_IO2||CPU.PS_MIO4_500||B7||||||||This signal is internally pulled up or down by 20kOhm resistor depending on order code (selecting then the bootstrap configuration)

|-

|J1.123||SPI0_DQ1/MODE1/NAND_WE||CPU.PS_MIO3_500||D6||||||||This signal is internally pulled up or down by 20kOhm resistor depending on order code (selecting then the bootstrap configuration)

|-

|J1.125||SPI0_DQ0/MODE3/NAND_ALE||CPU.PS_MIO2_500||B8||||||||This signal is internally pulled up or down by 20kOhm resistor depending on order code (selecting then the bootstrap configuration)

|-

|J1.127||DGND||DGND||n.a.||||||||

|-

|J1.129||SPI0_SCLK/MODE4/NAND_IO1||CPU.PS_MIO6_500||A5||||||||This signal is internally pulled up or down by 20kOhm resistor depending on order code (selecting then the bootstrap configuration)

|-

|J1.131||NAND_BUSY||CPU.PS_MIO14_500||C5||||||||

|-

|J1.133||PS_MIO15_500||CPU.PS_MIO15_500 WDT.WDI||C8 1||||||||See also [[Watchdog_(Bora)|this page]]

|-

|J1.135||N.C.||Not Connected||n.a.||||||||

{| class="wikitable" {| {{table}}

|-

|J1.2||VDDIO_BANK35||FPGA.VCCO_35||C19 - F18 - H14 - J17 - K20 - M16||||||||

|-

|J1.4||DGND||DGND||n.a.||||||||

|J1.74||IO_0_35||FPGA.IO_0_35||G14||||||||

|-

|J1.76||~~PS_MIO39_501~~N.C.||~~CPU.PS_MIO39_501~~Not Connected||~~C18~~n.a.||||||||

|-

|J1.78||~~PS_MIO38_501~~N.C.||~~CPU.PS_MIO38_501~~Not Connected||~~E13~~n.a.||||||||

|-

|J1.80||~~PS_MIO37_501~~PS_MIO49_501||CPU.~~PS_MIO37_501~~PS_MIO49_501||~~A10~~C12||||||||

|-

|J1.82||~~PS_MIO36_501~~PS_MIO48_501||CPU.~~PS_MIO36_501~~PS_MIO48_501||~~A11~~B12||||||||

|-

|J1.84||~~PS_MIO35_501~~PS_MIO47_501||CPU.~~PS_MIO35_501~~PS_MIO47_501||~~F12~~B14||||||||

|-

|J1.86||DGND||DGND||n.a.||||||||

|-

|J1.88||~~PS_MIO34_501~~PS_MIO46_501||CPU.~~PS_MIO34_501~~PS_MIO46_501||~~A12~~D16||||||||

|-

|J1.90||ETH_INTN||LAN.INT_N / PME_N2||38||||||||

|J1.118||DGND||DGND||n.a.||||||||

|-

|J1.120||SPI0_CS0N||CPU.PS_MIO1_500 NOR.CS#||A7 C2||||||||

|-

|J1.122||NAND_CS0/SPI0_CS1||CPU.PS_MIO0_500 NAND.~CE||E6 9||||||||

|-

|J1.124||NAND_IO3||CPU.PS_MIO13_500 NAND.I/O3||E8 32||||||||

|-

|J1.126||NAND_IO4||CPU.PS_MIO9_500 NAND.I/O4||B5 41||||||||

|-

|J1.128||NAND_IO5||CPU.PS_MIO10_500 NAND.I/O5||E9 42||||||||

|-

|J1.130||DGND||DGND||n.a.||||||||

|-

|J1.132||NAND_IO6||CPU.PS_MIO11_500 NAND.I/O6||C6 43||||||||

|-

|J1.134||NAND_IO7||CPU.PS_MIO12_500 NAND.I/O7||D9 44||||||||

|-

|J1.136||NAND_RD_B/VCFG1||CPU.PS_MIO8_500 NAND.~RE||D5 8||||||||This signal is internally pulled up or down by 20kOhm resistor depending on order code (selecting then the bootstrap configuration)

|-

|J1.138||NAND_CLE/VCFG0||CPU.PS_MIO7_500 NAND.CLE||D8 16||||||||This signal is internally pulled up or down by 20kOhm resistor depending on order code (selecting then the bootstrap configuration)

|-

|J1.140||DGND||DGND||n.a.||||||||

{| class="wikitable" {| {{table}}

|-

|J2.1||DGND||DGND||n.a.||||||||

|J2.13||DGND||DGND||n.a.||||||||

|-

|J2.15||IO_L3P_T0_DQS_PUDC_B_34||FPGA.IO_L3P_T0_DQS_PUDC_B_34||U13||||||Internally connected to 3V3 via 10K resistor ||

|-

|J2.17||IO_L3N_T0_DQS_34||FPGA.IO_L3N_T0_DQS_34||V13||||||||

|J2.91||N.C.||Not Connected||n.a.||||||||

|-

|J2.93||~~N.C.~~RTC_32KHZ||~~Not Connected~~RTC.32KHZ||~~n.a.~~1||||||||

|-

|J2.95||~~N.C.~~RTC_RST||~~Not Connected~~RTC.~RST ||~~n.a.~~4||||||||

|-

|J2.97||XADC_VN_R||FPGA.VN_0||L10||||||||

|J2.101||N.C.||Not Connected||n.a.||||||||

|-

|J2.103||~~N.C.~~CONN_SPI_RSTn||~~Not Connected~~NOR.~RESET/RFU ||~~n.a.~~A4||||||||

|-

|J2.105||CAN_L||CAN.L||6||||||||

|J2.109||DGND||DGND||n.a.||||||||

|-

|J2.111||RTC_INT/SQW||RTC.RTC_INT/SQW||3||||||||It can be left open if not used. When used, a proper pull-up resistor is required on the carrier board. For further details, please refer to the Maxim Integrated DS3232 datasheet.

|-

|J2.113||RTC_VBAT||RTC.VBAT||6||||||||

|-

|J2.115||VBAT||CPU.VCCBATT_0||F11||||||||This pin is connected to the VCCBATT_0 (for the battery-backed RAM - BBRAM) pin of the Zynq SOC. For additional information, please refer to the Zynq datasheet and TRM.

|-

|J2.117||DGND||DGND||n.a.||||||||

{| class="wikitable" {| {{table}}

|-

|J2.2||DGND||DGND||n.a.||||||||

|J2.88||DGND||DGND||n.a.||||||||

|-

|J2.90||FPGA_INIT_B||FPGA.INIT_B_0||R10||||||||For further details, please refer to [[PL_initialization_signals_(Bora/BoraX/BoraLite) | PL initialization signals]]

|-

|J2.92||FPGA_PROGRAM_B||FPGA.PROGRAM_B_0||L6||||||||For further details, please refer to [[PL_initialization_signals_(Bora/BoraX/BoraLite) | PL initialization signals]] (10 kΩ pull-up resistor is already mounted on BORA module)

|-

|J2.94||FPGA_DONE||FPGA.DONE_0||R11||||||||For further details, please refer to [[PL_initialization_signals_(Bora/BoraX/BoraLite) | PL initialization signals]]

|-

|J2.96||WD_SET2||WDT.SET2||6||||||||

|J2.102||DGND||DGND||n.a.||||||||

|-

|J2.104||~~IO_OTG_RESETN~~PS_MIO50_501||~~FPGA~~CPU.~~IO_25_34~~PS_MIO50_501 USBOTG.RESETB||~~T19~~B13 22||||||||For further details, please refer to [[Reset_scheme_(Bora)#PS_MIO50_501_.28J2.104.29 | Reset_scheme_(Bora)#PS_MIO50_501]]

|-

|J2.106||~~IO_ETH0_RESETN~~PS_MIO51_501||~~FPGA~~CPU.~~IO_0_34~~PS_MIO51_501 ETHPHY1GB.RESET_N||~~R19~~B9 42||||||||For further details, please refer to [[Reset_scheme_(Bora)#PS_MIO51_501_.28J2.106.29 | Reset_scheme_(Bora)#PS_MIO51_501]]

|-

|J2.108||BOARD_PGOOD||nPSUSWITCHFPGABANK13.aON PSUSWITCHFPGABANK35.ON PSUSWITCHFPGABANK500/34.ON PSUSWITCHFPGABANK501.ON DDRVREFREGULATOR.PGOOD||~~n.a.~~3 3 3 3 9||||||||

|-

|J2.110||~~1.0V_ENA~~CB_PWR_GOOD ||~~n.a~~1V0REGULATOR.ENABLE ||n.a.||||||||

|-

|J2.112||SYS_RSTN||CPU.PS_SRST_B_501 MTR.~RST||B10 5||||||||

|-

|J2.114||PORSTN||CPU.PS_POR_B_500||C7||||||||

{| class="wikitable" {| {{table}}

|-

|J3.1||N.C.||Not Connected||n.a.||||||||

|J3.93||DGND||DGND||n.a.||||||||

|-

|J3.95||VDDIO_BANK13||FPGA.VCCO_13||T8 U11 W7 Y10||||||||N.B. Although BANK 13 is not available on Bora SOMs equipped with the XC7Z010 SOC, VDDIO_BANK13 pin must not be left open and must be connected as described in [[Programmable_logic_(Bora)]].

|-

|J3.97||VDDIO_BANK13||FPGA.VCCO_13||T8 U11 W7 Y10||||||||N.B. Although BANK 13 is not available on Bora SOMs equipped with the XC7Z010 SOC, VDDIO_BANK13 pin must not be left open and must be connected as described in [[Programmable_logic_(Bora)]].

|-

|J3.99||VDDIO_BANK13||FPGA.VCCO_13||T8 U11 W7 Y10||||||||N.B. Although BANK 13 is not available on Bora SOMs equipped with the XC7Z010 SOC, VDDIO_BANK13 pin must not be left open and must be connected as described in [[Programmable_logic_(Bora)]].

|-

|J3.101||DGND||DGND||n.a.||||||||

|J3.103||DGND||DGND||n.a.||||||||

|-

|J3.105||IO_L21P_T3_DQS_13||FPGA.IO_L21P_T3_DQS_13||V11||||||||Not available on Bora SOMs equipped with the XC7Z010 SOC

|-

|J3.107||IO_L21N_T3_DQS_13||FPGA.IO_L21N_T3_DQS_13||V10||||||||Not available on Bora SOMs equipped with the XC7Z010 SOC

|-

|J3.109||DGND||DGND||n.a.||||||||

|-

|J3.111||IO_L19P_T3_13||FPGA.IO_L19P_T3_13||T5||||||||Not available on Bora SOMs equipped with the XC7Z010 SOC

|-

|J3.113||IO_L19N_T3_VREF_13||FPGA.IO_L19N_T3_VREF_13||U5||||||||Not available on Bora SOMs equipped with the XC7Z010 SOC

|-

|J3.115||DGND||DGND||n.a.||||||||

|-

|J3.117||IO_L18P_T2_13||FPGA.IO_L18P_T2_13||W11||||||||Not available on Bora SOMs equipped with the XC7Z010 SOC

|-

|J3.119||IO_L18N_T2_13||FPGA.IO_L18N_T2_13||Y11||||||||Not available on Bora SOMs equipped with the XC7Z010 SOC

|-

|J3.121||DGND||DGND||n.a.||||||||

|-

|J3.123||IO_L16P_T2_13||FPGA.IO_L16P_T2_13||W10||||||||Not available on Bora SOMs equipped with the XC7Z010 SOC

|-

|J3.125||IO_L16N_T2_13||FPGA.IO_L16N_T2_13||W9||||||||Not available on Bora SOMs equipped with the XC7Z010 SOC

|-

|J3.127||DGND||DGND||n.a.||||||||

|-

|J3.129||IO_L14P_T2_SRCC_13||FPGA.IO_L14P_T2_SRCC_13||Y9||||||||Not available on Bora SOMs equipped with the XC7Z010 SOC

|-

|J3.131||IO_L14N_T2_SRCC_13||FPGA.IO_L14N_T2_SRCC_13||Y8||||||||Not available on Bora SOMs equipped with the XC7Z010 SOC

|-

|J3.133||DGND||DGND||n.a.||||||||

|-

|J3.135||IO_L12P_T1_MRCC_13||FPGA.IO_L12P_T1_MRCC_13||T9||||||||Not available on Bora SOMs equipped with the XC7Z010 SOC

|-

|J3.137||IO_L12N_T1_MRCC_13||FPGA.IO_L12N_T1_MRCC_13||U10||||||||Not available on Bora SOMs equipped with the XC7Z010 SOC

|-

|J3.139||DGND||DGND||n.a.||||||||

{| class="wikitable" {| {{table}}

|-

|J3.2||N.C.||Not Connected||n.a.||||||||

|J3.70||N.C.||Not Connected||n.a.||||||||

|-

|J3.72||MON_VCCPLL||n.a.||n.a.||||||||By default this pin must not be connected. Optionally it can route power voltage generated by Bora PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.

|-

|J3.74||MON_XADC_VCC||n.a.||n.a.||||||||By default this pin must not be connected. Optionally it can route power voltage generated by Bora PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.

|-

|J3.76||MON_FPGA_VDDIO_BANK35||n.a.||n.a.||||||||By default this pin must not be connected. Optionally it can route power voltage generated by Bora PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.

|-

|J3.78||MON_FPGA_VDDIO_BANK34||n.a.||n.a.||||||||By default this pin must not be connected. Optionally it can route power voltage generated by Bora PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.

|-

|J3.80||MON_FPGA_VDDIO_BANK13||n.a.||n.a.||||||||By default this pin must not be connected. Optionally it can route power voltage generated by Bora PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.

|-

|J3.82||MON_1.8V_IO||n.a.||n.a.||||||||By default this pin must not be connected. Optionally it can route power voltage generated by Bora PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.

|-

|J3.84||MON_3.3V||n.a.||n.a.||||||||By default this pin must not be connected. Optionally it can route power voltage generated by Bora PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.

|-

|J3.86||MON_1V2_ETH||n.a.||n.a.||||||||By default this pin must not be connected. Optionally it can route power voltage generated by Bora PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.

|-

|J3.88||MON_VDDQ_1V5||n.a.||n.a.||||||||By default this pin must not be connected. Optionally it can route power voltage generated by Bora PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.

|-

|J3.90||MON_1.8V||n.a.||n.a.||||||||By default this pin must not be connected. Optionally it can route power voltage generated by Bora PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.

|-

|J3.92||MON_1.0V||n.a.||n.a.||||||||By default this pin must not be connected. Optionally it can route power voltage generated by Bora PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.

|-

|J3.94||DGND||DGND||n.a.||||||||

|-

|J3.96||VDDIO_BANK13||FPGA.VCCO_13||T8 U11 W7 Y10||||||||N.B. Although BANK 13 is not available on Bora SOMs equipped with the XC7Z010 SOC, VDDIO_BANK13 pin must not be left open and must be connected as described in [[Programmable_logic_(Bora)]].

|-

|J3.98||VDDIO_BANK13||FPGA.VCCO_13||T8 U11 W7 Y10||||||||N.B. Although BANK 13 is not available on Bora SOMs equipped with the XC7Z010 SOC, VDDIO_BANK13 pin must not be left open and must be connected as described in [[Programmable_logic_(Bora)]].

|-

|J3.100||IO_L6N_T0_VREF_13||FPGA.IO_L6N_T0_VREF_13||V5||||||||Not available on Bora SOMs equipped with the XC7Z010 SOC

|-

|J3.102||DGND||DGND||n.a.||||||||

|-

|J3.104||IO_L22P_T3_13||FPGA.IO_L22P_T3_13||V6||||||||Not available on Bora SOMs equipped with the XC7Z010 SOC

|-

|J3.106||IO_L22N_T3_13||FPGA.IO_L22N_T3_13||W6||||||||Not available on Bora SOMs equipped with the XC7Z010 SOC

|-

|J3.108||DGND||DGND||n.a.||||||||

|-

|J3.110||IO_L20P_T3_13||FPGA.IO_L20P_T3_13||Y12||||||||Not available on Bora SOMs equipped with the XC7Z010 SOC

|-

|J3.112||IO_L20N_T3_13||FPGA.IO_L20N_T3_13||Y13||||||||Not available on Bora SOMs equipped with the XC7Z010 SOC

|-

|J3.114||DGND||DGND||n.a.||||||||

|-

|J3.116||IO_L17P_T2_13||FPGA.IO_L17P_T2_13||U9||||||||Not available on Bora SOMs equipped with the XC7Z010 SOC

|-

|J3.118||IO_L17N_T2_13||FPGA.IO_L17N_T2_13||U8||||||||Not available on Bora SOMs equipped with the XC7Z010 SOC

|-

|J3.120||DGND||DGND||n.a.||||||||

|-

|J3.122||IO_L15P_T2_DQS_13||FPGA.IO_L15P_T2_DQS_13||V8||||||||Not available on Bora SOMs equipped with the XC7Z010 SOC

|-

|J3.124||IO_L15N_T2_DQS_13||FPGA.IO_L15N_T2_DQS_13||W8||||||||Not available on Bora SOMs equipped with the XC7Z010 SOC

|-

|J3.126||DGND||DGND||n.a.||||||||

|-

|J3.128||IO_L13P_T2_MRCC_13||FPGA.IO_L13P_T2_MRCC_13||Y7||||||||Not available on Bora SOMs equipped with the XC7Z010 SOC

|-

|J3.130||IO_L13N_T2_MRCC_13||FPGA.IO_L13N_T2_MRCC_13||Y6||||||||Not available on Bora SOMs equipped with the XC7Z010 SOC

|-

|J3.132||DGND||DGND||n.a.||||||||

|-

|J3.134||IO_L11P_T1_SRCC_13||FPGA.IO_L11P_T1_SRCC_13||U7||||||||Not available on Bora SOMs equipped with the XC7Z010 SOC

|-

|J3.136||IO_L11N_T1_SRCC_13||FPGA.IO_L11N_T1_SRCC_13||V7||||||||Not available on Bora SOMs equipped with the XC7Z010 SOC

|-

|J3.138||DGND||DGND||n.a.||||||||

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