Bureaucrats, dave_user, Administrators
8,157
edits
Changes
→J1 odd pins (1 to 139)
|J1.117||DGND||DGND||n.a.||||||||
|-
|J1.119||SPI0_DQ3/MODE0/NAND_IO0||CPU.PS_MIO5_500||A6|||||||| This signal is internally pulled up or down by 20kOhm resistor to select proper depending on order code (selecting then the bootstrap configuration.)
|-
|J1.121||SPI0_DQ2/MODE2/NAND_IO2||CPU.PS_MIO4_500||B7|||||||| This signal is internally pulled up or down by 20kOhm resistor to select proper depending on order code (selecting then the bootstrap configuration.)
|-
|J1.123||SPI0_DQ1/MODE1/NAND_WE||CPU.PS_MIO3_500||D6|||||||| This signal is internally pulled up or down by 20kOhm resistor to select proper depending on order code (selecting then the bootstrap configuration.)
|-
|J1.125||SPI0_DQ0/MODE3/NAND_ALE||CPU.PS_MIO2_500||B8|||||||| This signal is internally pulled up or down by 20kOhm resistor to select proper depending on order code (selecting then the bootstrap configuration.)
|-
|J1.127||DGND||DGND||n.a.||||||||
|-
|J1.129||SPI0_SCLK/MODE4/NAND_IO1||CPU.PS_MIO6_500||A5|||||||| This signal is internally pulled up or down by 20kOhm resistor to select proper depending on order code (selecting then the bootstrap configuration.)
|-
|J1.131||NAND_BUSY||CPU.PS_MIO14_500||C5||||||||
