View source for Pinout (Bora)

==SOM J2 ODD pins (1 to 139) declaration ==

{| class="wikitable" {| {{table}}
| style="background:#f0f0f0;" align="center" |'''Pin'''
| style="background:#f0f0f0;" align="center" |'''Pin Name'''
| style="background:#f0f0f0;" align="center" |'''Internal Connections'''
| style="background:#f0f0f0;" align="center" |'''Ball/pin #'''
| style="background:#f0f0f0;" align="center" |'''Supply Group'''
| style="background:#f0f0f0;" align="center" |'''Type'''
| style="background:#f0f0f0;" align="center" |'''Voltage'''
| style="background:#f0f0f0;" align="center" |'''Note'''
|-
|J2.1||DGND||DGND||-||||G||||
|-
|J2.3||DGND||DGND||-||||G||||
|-
|J2.5||IO_L8P_T1_34||FPGA.IO_L8P_T1_34||W14||BANK34||I/O||3.3V||
|-
|J2.7||IO_L8N_T1_34||FPGA.IO_L8N_T1_34||Y14||BANK34||I/O||3.3V||
|-
|J2.9||IO_L6P_T0_34||CAN.D<br>FPGA.IO_L6P_T0_34||1<br>P14||BANK34||I/O||3.3V||By default used as CAN.TX with internal CAN PHY transceiver (mount option) 
|-
|J2.11||IO_L6N_T0_VREF_34||FPGA.IO_L6N_T0_VREF_34||R14||BANK34||I/O||3.3V||
|-
|J2.13||DGND||DGND||-||||G||||
|-
|J2.15||IO_L3P_T0_DQS_PUDC_B_34||FPGA.IO_L3P_T0_DQS_PUDC_B_34||U13||BANK34||I/O||3.3V||Internal 10K resistor pull-up
|-
|J2.17||IO_L3N_T0_DQS_34||FPGA.IO_L3N_T0_DQS_34||V13||BANK34||I/O||3.3V||
|-
|J2.19||IO_L2P_T0_34||FPGA.IO_L2P_T0_34||T12||BANK34||I/O||3.3V||
|-
|J2.21||IO_L2N_T0_34||FPGA.IO_L2N_T0_34||U12||BANK34||I/O||3.3V||
|-
|J2.23||DGND||DGND||-||||G||||
|-
|J2.25||IO_L22P_T3_34||FPGA.IO_L22P_T3_34||W18||BANK34||I/O||3.3V||
|-
|J2.27||IO_L22N_T3_34||FPGA.IO_L22N_T3_34||W19||BANK34||I/O||3.3V||
|-
|J2.29||IO_L21P_T3_DQS_34||FPGA.IO_L21P_T3_DQS_34||V17||BANK34||I/O||3.3V||
|-
|J2.31||IO_L21N_T3_DQS_34||FPGA.IO_L21N_T3_DQS_34||V18||BANK34||I/O||3.3V||
|-
|J2.33||DGND||DGND||-||||G||||
|-
|J2.35||IO_L19P_T3_34||CAN.R<br>FPGA.IO_L19P_T3_34||4<br>R16||BANK34||I/O||3.3V||By default used as CAN.RX with internal CAN PHY transceiver (mount option) 
|-
|J2.37||IO_L19N_T3_VREF_34||FPGA.IO_L19N_T3_VREF_34||R17||BANK34||I/O||3.3V||
|-
|J2.39||IO_L18P_T2_34||FPGA.IO_L18P_T2_34||V16||BANK34||I/O||3.3V||
|-
|J2.41||IO_L18N_T2_34||FPGA.IO_L18N_T2_34||W16||BANK34||I/O||3.3V||
|-
|J2.43||DGND||DGND||-||||G||||
|-
|J2.45||IO_L15P_T2_DQS_34||FPGA.IO_L15P_T2_DQS_34||T20||BANK34||I/O||3.3V||
|-
|J2.47||IO_L15N_T2_DQS_34||FPGA.IO_L15N_T2_DQS_34||U20||BANK34||I/O||3.3V||
|-
|J2.49||DGND||DGND||-||||||||
|-
|J2.51||IO_L13P_T1_MRCC_34||FPGA.IO_L13P_T1_MRCC_34||N18||BANK34||I/O||3.3V||
|-
|J2.53||IO_L13N_T1_MRCC_34||FPGA.IO_L13N_T1_MRCC_34||P19||BANK34||I/O||3.3V||
|-
|J2.55||DGND||DGND||-||||||||
|-
|J2.57||IO_L11P_T1_SRCC_34||FPGA.IO_L11P_T1_SRCC_34||U14||BANK34||I/O||3.3V||
|-
|J2.59||IO_L11N_T1_SRCC_34||FPGA.IO_L11N_T1_SRCC_34||U15||BANK34||I/O||3.3V||
|-
|J2.61||DGND||DGND||-||||||||
|-
|J2.63||IO_L10P_T1_34||FPGA.IO_L10P_T1_34||V15||BANK34||I/O||3.3V||
|-
|J2.65||IO_L10N_T1_34||FPGA.IO_L10N_T1_34||W15||BANK34||I/O||3.3V||
|-
|J2.67||IO_25_34||FPGA.IO_25_34||T19||BANK34||I/O||3.3V||
|-
|J2.69||IO_0_34||FPGA.IO_0_34||R19||BANK34||I/O||3.3V||
|-
|J2.71||DGND||DGND||-||||G||||
|-
|J2.73||N.C.||Not Connected||-||||||||
|-
|J2.75||N.C.||Not Connected||-||||||||
|-
|J2.77||N.C.||Not Connected||-||||||||
|-
|J2.79||N.C.||Not Connected||-||||||||
|-
|J2.81||N.C.||Not Connected||-||||||||
|-
|J2.83||N.C.||Not Connected||-||||||||
|-
|J2.85||N.C.||Not Connected||-||||||||
|-
|J2.87||N.C.||Not Connected||-||||||||
|-
|J2.89||N.C.||Not Connected||-||||||||
|-
|J2.91||N.C.||Not Connected||-||||||||
|-
|J2.93||RTC_32KHZ||RTC.32KHZ||1||||O||3.3V||It can be left open if not used. For further details, please refer to the Maxim Integrated DS3232 datasheet.
|-
|J2.95||RTC_RST||RTC.~RST ||4||||I/O||3.3V||It can be left open if not used. For further details, please refer to the Maxim Integrated DS3232 datasheet.
|-
|J2.97||XADC_VN_R||FPGA.VN_0||L10||||A / I||VREFP
|See [[BELK-TN-012: Using XADC signal module|BELK-TN-012 Using XADC signal module]]
|-
|J2.99||XADC_VP_R||FPGA.VP_0||K9||||A / I||VREFP
|See [[BELK-TN-012: Using XADC signal module|BELK-TN-012 Using XADC signal module]]
|-
|J2.101||N.C.||Not Connected||-||||||||
|-
|J2.103||CONN_SPI_RSTn||NOR.~RESET/RFU ||A4||||||3.3V||
|-
|J2.105||CAN_L||CAN.L||6||||I/O||3.3V||For further details, please refer to the Texas Instruments SN65HVD232 datasheet.
|-
|J2.107||CAN_H||CAN.H||7||||I/O||3.3V||For further details, please refer to the Texas Instruments SN65HVD232 datasheet.
|-
|J2.109||DGND||DGND||-||||G||||
|-
|J2.111||RTC_INT/SQW||RTC.RTC_INT/SQW||3||||I/O||3.3V|| It can be left open if not used. When used, a proper pull-up resistor is required on the carrier board. For further details, please refer to the Maxim Integrated DS3232 datasheet.
|-
|J2.113||RTC_VBAT||RTC.VBAT||6||||S||3.0V||Connect to ground if not used. For further details, please refer to the Maxim Integrated DS3232 datasheet.
|-
|J2.115||VBAT||CPU.VCCBATT_0||F11|| ||S|| ||This pin is connected to the VCCBATT_0 (for the battery-backed RAM - BBRAM) pin of the Zynq SOC. For additional information, please refer to the Zynq datasheet and TRM.
|-
|J2.117||DGND||DGND||-||||G||||
|-
|J2.119||3.3VIN||+3.3 V||-||||S||||
|-
|J2.121||3.3VIN||+3.3 V||-||||S||||
|-
|J2.123||3.3VIN||+3.3 V||-||||S||||
|-
|J2.125||DGND||DGND||-||||G||||
|-
|J2.127||3.3VIN||+3.3 V||-||||S||||
|-
|J2.129||3.3VIN||+3.3 V||-||||S||||
|-
|J2.131||3.3VIN||+3.3 V||-||||S||||
|-
|J2.133||3.3VIN||+3.3 V||-||||S||||
|-
|J2.135||3.3VIN||+3.3 V||-||||S||||
|-
|J2.137||3.3VIN||+3.3 V||-||||S||||
|-
|J2.139||DGND||DGND||-||||G||||
|-
|}