View source for Pinout (Bora)

==J3 odd pins (1 to 139)==

{| class="wikitable" {| {{table}}
| style="background:#f0f0f0;" align="center" |'''Pin'''
| style="background:#f0f0f0;" align="center" |'''Pin Name'''
| style="background:#f0f0f0;" align="center" |'''Internal Connections'''
| style="background:#f0f0f0;" align="center" |'''Ball/pin #'''
| style="background:#f0f0f0;" align="center" |'''Supply Group'''
| style="background:#f0f0f0;" align="center" |'''Type'''
| style="background:#f0f0f0;" align="center" |'''Voltage'''
| style="background:#f0f0f0;" align="center" |'''Note'''
|-
|J3.1||N.C.||Not Connected||n.a.||||||||
|-
|J3.3||N.C.||Not Connected||n.a.||||||||
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|J3.5||N.C.||Not Connected||n.a.||||||||
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|J3.7||N.C.||Not Connected||n.a.||||||||
|-
|J3.9||N.C.||Not Connected||n.a.||||||||
|-
|J3.11||N.C.||Not Connected||n.a.||||||||
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|J3.13||N.C.||Not Connected||n.a.||||||||
|-
|J3.15||N.C.||Not Connected||n.a.||||||||
|-
|J3.17||N.C.||Not Connected||n.a.||||||||
|-
|J3.19||N.C.||Not Connected||n.a.||||||||
|-
|J3.21||N.C.||Not Connected||n.a.||||||||
|-
|J3.23||N.C.||Not Connected||n.a.||||||||
|-
|J3.25||N.C.||Not Connected||n.a.||||||||
|-
|J3.27||N.C.||Not Connected||n.a.||||||||
|-
|J3.29||N.C.||Not Connected||n.a.||||||||
|-
|J3.31||N.C.||Not Connected||n.a.||||||||
|-
|J3.33||N.C.||Not Connected||n.a.||||||||
|-
|J3.35||N.C.||Not Connected||n.a.||||||||
|-
|J3.37||N.C.||Not Connected||n.a.||||||||
|-
|J3.39||N.C.||Not Connected||n.a.||||||||
|-
|J3.41||N.C.||Not Connected||n.a.||||||||
|-
|J3.43||N.C.||Not Connected||n.a.||||||||
|-
|J3.45||N.C.||Not Connected||n.a.||||||||
|-
|J3.47||N.C.||Not Connected||n.a.||||||||
|-
|J3.49||N.C.||Not Connected||n.a.||||||||
|-
|J3.51||N.C.||Not Connected||n.a.||||||||
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|J3.53||N.C.||Not Connected||n.a.||||||||
|-
|J3.55||N.C.||Not Connected||n.a.||||||||
|-
|J3.57||N.C.||Not Connected||n.a.||||||||
|-
|J3.59||N.C.||Not Connected||n.a.||||||||
|-
|J3.61||N.C.||Not Connected||n.a.||||||||
|-
|J3.63||N.C.||Not Connected||n.a.||||||||
|-
|J3.65||N.C.||Not Connected||n.a.||||||||
|-
|J3.67||DGND||DGND||n.a.||||||||
|-
|J3.69||N.C.||Not Connected||n.a.||||||||
|-
|J3.71||N.C.||Not Connected||n.a.||||||||
|-
|J3.73||N.C.||Not Connected||n.a.||||||||
|-
|J3.75||N.C.||Not Connected||n.a.||||||||
|-
|J3.77||N.C.||Not Connected||n.a.||||||||
|-
|J3.79||N.C.||Not Connected||n.a.||||||||
|-
|J3.81||N.C.||Not Connected||n.a.||||||||
|-
|J3.83||N.C.||Not Connected||n.a.||||||||
|-
|J3.85||N.C.||Not Connected||n.a.||||||||
|-
|J3.87||N.C.||Not Connected||n.a.||||||||
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|J3.89||N.C.||Not Connected||n.a.||||||||
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|J3.91||N.C.||Not Connected||n.a.||||||||
|-
|J3.93||DGND||DGND||n.a.||||||||
|-
|J3.95||VDDIO_BANK13||FPGA.VCCO_13||T8<br>U11<br>W7<br>Y10|||||||| N.B. Although BANK 13 is not available on Bora SOMs equipped with the XC7Z010 SOC, VDDIO_BANK13 pin must not be left open and must be connected as described in [[Programmable_logic_(Bora)]].
|-
|J3.97||VDDIO_BANK13||FPGA.VCCO_13||T8<br>U11<br>W7<br>Y10|||||||| N.B. Although BANK 13 is not available on Bora SOMs equipped with the XC7Z010 SOC, VDDIO_BANK13 pin must not be left open and must be connected as described in [[Programmable_logic_(Bora)]].
|-
|J3.99||VDDIO_BANK13||FPGA.VCCO_13||T8<br>U11<br>W7<br>Y10|||||||| N.B. Although BANK 13 is not available on Bora SOMs equipped with the XC7Z010 SOC, VDDIO_BANK13 pin must not be left open and must be connected as described in [[Programmable_logic_(Bora)]].
|-
|J3.101||DGND||DGND||n.a.||||||||
|-
|J3.103||DGND||DGND||n.a.||||||||
|-
|J3.105||IO_L21P_T3_DQS_13||FPGA.IO_L21P_T3_DQS_13||V11|||||||| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|J3.107||IO_L21N_T3_DQS_13||FPGA.IO_L21N_T3_DQS_13||V10|||||||| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|J3.109||DGND||DGND||n.a.||||||||
|-
|J3.111||IO_L19P_T3_13||FPGA.IO_L19P_T3_13||T5|||||||| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|J3.113||IO_L19N_T3_VREF_13||FPGA.IO_L19N_T3_VREF_13||U5|||||||| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|J3.115||DGND||DGND||n.a.||||||||
|-
|J3.117||IO_L18P_T2_13||FPGA.IO_L18P_T2_13||W11|||||||| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|J3.119||IO_L18N_T2_13||FPGA.IO_L18N_T2_13||Y11|||||||| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|J3.121||DGND||DGND||n.a.||||||||
|-
|J3.123||IO_L16P_T2_13||FPGA.IO_L16P_T2_13||W10|||||||| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|J3.125||IO_L16N_T2_13||FPGA.IO_L16N_T2_13||W9|||||||| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|J3.127||DGND||DGND||n.a.||||||||
|-
|J3.129||IO_L14P_T2_SRCC_13||FPGA.IO_L14P_T2_SRCC_13||Y9|||||||| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|J3.131||IO_L14N_T2_SRCC_13||FPGA.IO_L14N_T2_SRCC_13||Y8|||||||| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|J3.133||DGND||DGND||n.a.||||||||
|-
|J3.135||IO_L12P_T1_MRCC_13||FPGA.IO_L12P_T1_MRCC_13||T9|||||||| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|J3.137||IO_L12N_T1_MRCC_13||FPGA.IO_L12N_T1_MRCC_13||U10|||||||| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|J3.139||DGND||DGND||n.a.||||||||
|-
|}