Changes

Pinout (BORAXpress)

1,597 bytes added, 16:00, 26 November 2018

→‎J1 even pins (2 to 140)

==J1 odd pins (1 to 139)==

{| class="wikitable" {| {{table}}

|-

| J1.1||DGND||DGND||-||-||G||-||Digital ground

| J1.21||IO_L17P_T2_AD5P_35||FPGA.IO_L17P_T2_AD5P_35||E2||Bank 35||I/O||User defined||

|-

| J1.23||IO_L17N_T2_AD5N_35||FPGA.IO_L17N_T2_AD5N_35||D2||Bank 35||I/O||User defined||

|-

| J1.25||IO_L15P_T2_DQS_AD12P_35||FPGA.IO_L15P_T2_DQS_AD12P_35||A2||Bank 35||I/O||User defined||

|-

| J1.27||IO_L15N_T2_DQS_AD12N_35||FPGA.IO_L15N_T2_DQS_AD12N_35||A1||Bank 35||I/O||User defined||

|-

| J1.29||DGND||DGND||-||-||G||-||Digital ground

|-

| J1.31||IO_L13P_T2_MRCC_35||FPGA.IO_L13P_T2_MRCC_35||B4||Bank 35||I/O||User defined||

|-

| J1.33||IO_L13N_T2_MRCC_35||FPGA.IO_L13N_T2_MRCC_35||B3||Bank 35||I/O||User defined||

|-

| J1.35||DGND||DGND||-||-||G||-||Digital ground

|-

| J1.37||IO_L11P_T1_SRCC_35||FPGA.IO_L11P_T1_SRCC_35||C6||Bank 35||I/O||User defined||

|-

| J1.39||IO_L11N_T1_SRCC_35||FPGA.IO_L11N_T1_SRCC_35||C5||Bank 35||I/O||User defined||

|-

| J1.41||IO_L9P_T1_DQS_AD3P_35||FPGA.IO_L9P_T1_DQS_AD3P_35||A7||Bank 35||I/O||User defined||

|-

| J1.43||IO_L9N_T1_DQS_AD3N_35||FPGA.IO_L9N_T1_DQS_AD3N_35||A6||Bank 35||I/O||User defined||

|-

| J1.45||IO_L7P_T1_AD2P_35||FPGA.IO_L7P_T1_AD2P_35||C8||Bank 35||I/O||User defined||

|-

| J1.47||IO_L7N_T1_AD2N_35||FPGA.IO_L7N_T1_AD2N_35||B8||Bank 35||I/O||User defined||

|-

| J1.49||DGND||DGND||-||-||G||-||Digital ground

|-

| J1.51||IO_L5P_T0_AD9P_35||FPGA.IO_L5P_T0_AD9P_35||F5||Bank 35||I/O||User defined||

|-

| J1.53||IO_L5N_T0_AD9N_35||FPGA.IO_L5N_T0_AD9N_35||E5||Bank 35||I/O||User defined||

|-

| J1.55||IO_L3P_T0_DQS_AD1P_35||FPGA.IO_L3P_T0_DQS_AD1P_35||E8||Bank 35||I/O||User defined||

|-

| J1.57||IO_L3N_T0_DQS_AD1N_35||FPGA.IO_L3N_T0_DQS_AD1N_35||D8||Bank 35||I/O||User defined||

|-

| J1.59||DGND||DGND||-||-||G||-||Digital ground

|-

| J1.61||IO_L1P_T0_AD0P_35||FPGA.IO_L1P_T0_AD0P_35||F7||Bank 35||I/O||User defined||

|-

| J1.63||IO_L1N_T0_AD0N_35||FPGA.IO_L1N_T0_AD0N_35||E7||Bank 35||I/O||User defined||

|-

| J1.65||DGND||DGND||-||-||G||-||Digital ground

| J1.105||ETH_TXRX0_P||LAN.ETH_TXRX0_P||2||||D||||

|-

| J1.107||DVDDH||LAN.DVDDH||16 34 40||||||1.8V||

|-

| J1.109||RFU||-||-||-||-||-||Reserved fo future use. Must be left floating.

| J1.117||DGND||DGND||-||-||G||-||Digital ground

|-

| J1.119||SPI0_DQ3/MODE0/NAND_IO0||CPU.PS_MIO5_500 NOR flash NAND flash||CPU.A20||Bank 500||I/O||3.3V||This signal is pulled up or down by 20kOhm resistor to select proper bootstrap configuration. Default configuration: pull-up (BOOT_MODE[0]=1)

|-

| J1.121||SPI0_DQ2/MODE2/NAND_IO2||CPU.PS_MIO4_500 NOR flash NAND flash||CPU.E19||Bank 500||I/O||3.3V||This signal is pulled up or down by 20kOhm resistor to select proper bootstrap configuration. Default configuration: pull-down (BOOT_MODE[2]=0)

|-

| J1.123||SPI0_DQ1/MODE1/NAND_WE||CPU.PS_MIO3_500 NOR flash NAND flash||CPU.F17||Bank 500||I/O||3.3V||This signal is pulled up or down by 20kOhm resistor to select proper bootstrap configuration. Default configuration: pull-down (BOOT_MODE[1]=0)

|-

| J1.125||SPI0_DQ0/MODE3/NAND_ALE||CPU.PS_MIO2_500 NOR flash NAND flash||CPU.A21||Bank 500||I/O||3.3V||This signal is pulled up or down by 20kOhm resistor to select proper bootstrap configuration. Default configuration: pull-down (BOOT_MODE[3]=0)

|-

| J1.127||DGND||DGND||-||-||G||-||Digital ground

|-

| J1.129||SPI0_SCLK/MODE4/NAND_IO1||CPU.PS_MIO6_500 NOR flash NAND flash||CPU.A19||Bank 500||I/O||3.3V||This signal is pulled up or down by 20kOhm resistor to select proper bootstrap configuration. Default configuration: pull-down (BOOT_MODE[4]=0)

|-

| J1.131||NAND_BUSY||CPU.PS_MIO14_500 NOR flash NAND flash||CPU.B17||Bank 500||I/O||3.3V||10kOhm pull-up

==J1 even pins (2 to 140)==

{| class="wikitable" {| {{table}}

|-

| J1.2||VDDIO_BANK35||||||||S||||

| J1.134||NAND_IO7||CPU.PS_MIO12_500 NAND flash||CPU.C18||Bank 500||I/O||3.3V||

|-

| J1.136||NAND_RD_B/VCFG1||CPU.PS_MIO8_500 NAND flash||CPU.E18||Bank 500||I/O||3.3V||This signal is pulled up or down by 20kOhm resistor to select proper bootstrap configuration. Default configuration: pull-up (VMODE[1]=1)

|-

| J1.138||NAND_CLE/VCFG0||CPU.PS_MIO7_500 NAND flash||CPU.D18||Bank 500||I/O||3.3V||This signal is pulled up or down by 20kOhm resistor to select proper bootstrap configuration. Default configuration: pull-down (VMODE[0]=0)

|-

| J1.140||DGND||DGND||-||-||-||G||Digital ground

==J2 odd pins (1 to 139)==

{| class="wikitable" {| {{table}}

|-

| J2.1||DGND||DGND||-||-||G||-||Digital ground

==J2 even pins (2 to 140)==

{| class="wikitable" {| {{table}}

|-

| J2.2||DGND||DGND||-||-||G||-||Digital ground

| J2.88||DGND||DGND||-||-||G||-||Digital ground

|-

| J2.90||FPGA_INIT_B||FPGA.INIT_B_0||T8||BANK 0||I/O||3.3V||Place external 4.7 kΩ (or stronger) pull-up resistor to BOARD_PGOOD driven +3.3V supplyFor more details please refer to Table 2-4 on [http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf 7 Series FPGAs Configuration]

|-

| J2.92||FPGA_PROGRAM_B||FPGA.PROGRAM_B_0||V10||BANK 0||I||3.3V||Place external 4.7 kΩ (or stronger) pull-up resistor to BOARD_PGOOD driven +3.3V supplyFor more details please refer to Table 2-4 on [http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf 7 Series FPGAs Configuration] (10 kΩ pull-up resistor is already mounted on BORAX module)

|-

| J2.94||FPGA_DONE||FPGA.DONE0||T10||BANK 0||I/O||3.3V||Place external 300Ω pull-up resistor to BOARD_PGOOD driven +3.3V supplyFor more details please refer to Table 2-4 on [http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf 7 Series FPGAs Configuration]

|-

| J2.96||WD_SET2||WDT.SET2||6||3.3V||I||3.3V||

==J3 odd pins (1 to 139)==

{| class="wikitable" {| {{table}}

|-

| J3.1||DGND||DGND||-||-||G||-||Digital ground

==J3 even pins (2 to 140)==

{| class="wikitable" {| {{table}}

|-

| J3.2||DGND||DGND||-||-||G||-||Digital ground

U0001

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