Changes

Pinout (BORAXpress)

15,997 bytes added, 16:00, 26 November 2018

→‎J1 even pins (2 to 140)

==J1 odd pins (1 to 139)==

{| class="wikitable" {| {{table}}

|-

| J1.1||DGND||DGND||-||-||G||-||Digital ground

| J1.21||IO_L17P_T2_AD5P_35||FPGA.IO_L17P_T2_AD5P_35||E2||Bank 35||I/O||User defined||

|-

| J1.23||IO_L17N_T2_AD5N_35||FPGA.IO_L17N_T2_AD5N_35||D2||Bank 35||I/O||User defined||

|-

| J1.25||IO_L15P_T2_DQS_AD12P_35||FPGA.IO_L15P_T2_DQS_AD12P_35||A2||Bank 35||I/O||User defined||

|-

| J1.27||IO_L15N_T2_DQS_AD12N_35||FPGA.IO_L15N_T2_DQS_AD12N_35||A1||Bank 35||I/O||User defined||

|-

| J1.29||DGND||DGND||-||-||G||-||Digital ground

|-

| J1.31||IO_L13P_T2_MRCC_35||FPGA.IO_L13P_T2_MRCC_35||B4||Bank 35||I/O||User defined||

|-

| J1.33||IO_L13N_T2_MRCC_35||FPGA.IO_L13N_T2_MRCC_35||B3||Bank 35||I/O||User defined||

|-

| J1.35||DGND||DGND||-||-||G||-||Digital ground

|-

| J1.37||IO_L11P_T1_SRCC_35||FPGA.IO_L11P_T1_SRCC_35||C6||Bank 35||I/O||User defined||

|-

| J1.39||IO_L11N_T1_SRCC_35||FPGA.IO_L11N_T1_SRCC_35||C5||Bank 35||I/O||User defined||

|-

| J1.41||IO_L9P_T1_DQS_AD3P_35||FPGA.IO_L9P_T1_DQS_AD3P_35||A7||Bank 35||I/O||User defined||

|-

| J1.43||IO_L9N_T1_DQS_AD3N_35||FPGA.IO_L9N_T1_DQS_AD3N_35||A6||Bank 35||I/O||User defined||

|-

| J1.45||IO_L7P_T1_AD2P_35||FPGA.IO_L7P_T1_AD2P_35||C8||Bank 35||I/O||User defined||

|-

| J1.47||IO_L7N_T1_AD2N_35||FPGA.IO_L7N_T1_AD2N_35||B8||Bank 35||I/O||User defined||

|-

| J1.49||DGND||DGND||-||-||G||-||Digital ground

|-

| J1.51||IO_L5P_T0_AD9P_35||FPGA.IO_L5P_T0_AD9P_35||F5||Bank 35||I/O||User defined||

|-

| J1.53||IO_L5N_T0_AD9N_35||FPGA.IO_L5N_T0_AD9N_35||E5||Bank 35||I/O||User defined||

|-

| J1.55||IO_L3P_T0_DQS_AD1P_35||FPGA.IO_L3P_T0_DQS_AD1P_35||E8||Bank 35||I/O||User defined||

|-

| J1.57||IO_L3N_T0_DQS_AD1N_35||FPGA.IO_L3N_T0_DQS_AD1N_35||D8||Bank 35||I/O||User defined||

|-

| J1.59||DGND||DGND||-||-||G||-||Digital ground

|-

| J1.61||IO_L1P_T0_AD0P_35||FPGA.IO_L1P_T0_AD0P_35||F7||Bank 35||I/O||User defined||

|-

| J1.63||IO_L1N_T0_AD0N_35||FPGA.IO_L1N_T0_AD0N_35||E7||Bank 35||I/O||User defined||

|-

| J1.65||DGND||DGND||-||-||G||-||Digital ground

| J1.105||ETH_TXRX0_P||LAN.ETH_TXRX0_P||2||||D||||

|-

| J1.107||DVDDH||LAN.DVDDH||16 34 40||||||1.8V||

|-

| J1.109||RFU||-||-||-||-||-||Reserved fo future use. Must be left floating.

| J1.117||DGND||DGND||-||-||G||-||Digital ground

|-

| J1.119||SPI0_DQ3/MODE0/NAND_IO0||CPU.PS_MIO5_500 NOR flash NAND flash||CPU.A20||Bank 500||I/O||3.3V||This signal is pulled up or down by 20kOhm resistor to select proper bootstrap configuration. Default configuration: pull-up (BOOT_MODE[0]=1)

|-

| J1.121||SPI0_DQ2/MODE2/NAND_IO2||CPU.PS_MIO4_500 NOR flash NAND flash||CPU.E19||Bank 500||I/O||3.3V||This signal is pulled up or down by 20kOhm resistor to select proper bootstrap configuration. Default configuration: pull-down (BOOT_MODE[2]=0)

|-

| J1.123||SPI0_DQ1/MODE1/NAND_WE||CPU.PS_MIO3_500 NOR flash NAND flash||CPU.F17||Bank 500||I/O||3.3V||This signal is pulled up or down by 20kOhm resistor to select proper bootstrap configuration. Default configuration: pull-down (BOOT_MODE[1]=0)

|-

| J1.125||SPI0_DQ0/MODE3/NAND_ALE||CPU.PS_MIO2_500 NOR flash NAND flash||CPU.A21||Bank 500||I/O||3.3V||This signal is pulled up or down by 20kOhm resistor to select proper bootstrap configuration. Default configuration: pull-down (BOOT_MODE[3]=0)

|-

| J1.127||DGND||DGND||-||-||G||-||Digital ground

|-

| J1.129||SPI0_SCLK/MODE4/NAND_IO1||CPU.PS_MIO6_500 NOR flash NAND flash||CPU.A19||Bank 500||I/O||3.3V||This signal is pulled up or down by 20kOhm resistor to select proper bootstrap configuration. Default configuration: pull-down (BOOT_MODE[4]=0)

|-

| J1.131||NAND_BUSY||CPU.PS_MIO14_500 NOR flash NAND flash||CPU.B17||Bank 500||I/O||3.3V||10kOhm pull-up

==J1 even pins (2 to 140)==

{| class="wikitable" {| {{table}}

|-

| J1.2||VDDIO_BANK35||||||||S||||

| J1.134||NAND_IO7||CPU.PS_MIO12_500 NAND flash||CPU.C18||Bank 500||I/O||3.3V||

|-

| J1.136||NAND_RD_B/VCFG1||CPU.PS_MIO8_500 NAND flash||CPU.E18||Bank 500||I/O||3.3V||This signal is pulled up or down by 20kOhm resistor to select proper bootstrap configuration. Default configuration: pull-up (VMODE[1]=1)

|-

| J1.138||NAND_CLE/VCFG0||CPU.PS_MIO7_500 NAND flash||CPU.D18||Bank 500||I/O||3.3V||This signal is pulled up or down by 20kOhm resistor to select proper bootstrap configuration. Default configuration: pull-down (VMODE[0]=0)

|-

| J1.140||DGND||DGND||-||-||-||G||Digital ground

==J2 odd pins (1 to 139)==

{| class="wikitable" {| {{table}}

|-

| J2.1||DGND||DGND||-||-||G||-||Digital ground

| J2.117||DGND||DGND||-||-||G||-||Digital ground

|-

| J2.119||3.3VIN||3.3VIN||-||3.3VIN||S||~~+3.3V~~||SOM Power Supply

|-

| J2.121||3.3VIN||3.3VIN||-||3.3VIN||S||~~+3.3V~~||SOM Power Supply

|-

| J2.123||3.3VIN||3.3VIN||-||3.3VIN||S||~~+3.3V~~||SOM Power Supply

|-

| J2.125||DGND||DGND||-||-||G||-||Digital ground

|-

| J2.127||3.3VIN||3.3VIN||-||3.3VIN||S||~~+3.3V~~||SOM Power Supply

|-

| J2.129||3.3VIN||3.3VIN||-||3.3VIN||S||~~+3.3V~~||SOM Power Supply

|-

| J2.131||3.3VIN||3.3VIN||-||3.3VIN||S||~~+3.3V~~||SOM Power Supply

|-

| J2.133||3.3VIN||3.3VIN||-||3.3VIN||S||~~+3.3V~~||SOM Power Supply

|-

| J2.135||3.3VIN||3.3VIN||-||3.3VIN||S||~~+3.3V~~||SOM Power Supply

|-

| J2.137||3.3VIN||3.3VIN||-||3.3VIN||S||~~+3.3V~~||SOM Power Supply

|-

| J2.139||DGND||DGND||-||-||G||-||Digital ground

==J2 even pins (2 to 140)==

{| class="wikitable" {| {{table}}

|-

| J2.2||DGND||DGND||-||-||G||-||Digital ground

| J2.88||DGND||DGND||-||-||G||-||Digital ground

|-

| J2.90||FPGA_INIT_B||FPGA.INIT_B_0||T8||BANK 0||I/O||3.3V||Place external 4.7 kΩ (or stronger) pull-up resistor to BOARD_PGOOD driven +3.3V supplyFor more details please refer to Table 2-4 on [http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf 7 Series FPGAs Configuration]

|-

| J2.92||FPGA_PROGRAM_B||FPGA.PROGRAM_B_0||V10||BANK 0||I||3.3V||Place external 4.7 kΩ (or stronger) pull-up resistor to BOARD_PGOOD driven +3.3V supplyFor more details please refer to Table 2-4 on [http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf 7 Series FPGAs Configuration] (10 kΩ pull-up resistor is already mounted on BORAX module)

|-

| J2.94||FPGA_DONE||FPGA.DONE0||T10||BANK 0||I/O||3.3V||Place external 300Ω pull-up resistor to BOARD_PGOOD driven +3.3V supplyFor more details please refer to Table 2-4 on [http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf 7 Series FPGAs Configuration]

|-

| J2.96||WD_SET2||WDT.SET2||6||3.3V||I||3.3V||

| J2.102||DGND||DGND||-||-||G||-||Digital ground

|-

| J2.104||PS_MIO50_501||CPU.PS_MIO50_501 USBOTG.RESETB||D10 22||BANK 501||I/O||1.8V||For further details, please refer to [[Reset_scheme_(~~BoraXpress~~BORAXpress)~~#PS_MIO50_501_.28J2.104.29~~ | Reset_scheme_(BoraXpress)#PS_MIO50_501]]

|-

| J2.106||PS_MIO51_501||CPU.PS_MIO51_501 ETHPHY1GB.RESET_N||C13 42||BANK 501||I/O||1.8V||For further details, please refer to [[Reset_scheme_(~~BoraXpress~~BORAXpress)~~#PS_MIO51_501_.28J2.106.29~~ | Reset_scheme_(BoraXpress)#PS_MIO51_501 ]]

|-

| J2.108||SOM_PGOOD||SOM_PGOOD_LOGIC.OUT||n.a.||3.3V||O||3.3V||Internally connected to DGND via 100K resistor

| J2.112||SYS_RSTn||CPU.PS_SRST_B_501 ||C14||BANK 501||I||1.8V||Internally connected to 1.8V via 20K resistor

|-

| J2.114||PORSTn||CPU.PS_POR_B_500~~ SV1.~RST SV2.~RST~~ WD.~WDO NOR.~RESET/RFU||B18~~ 5 5~~ 7 A4||BANK 500||I/O||3.3V||Internally connected to 3.3VIN via 2.2K resistor. For further details, please refer to [[Reset_scheme_(~~BoraXpress~~BORAXpress)~~#PORSTn_.28J2.114.29~~ | Reset_scheme_(BoraXpress)#PORSTn ]]

|-

| J2.116||MRSTn||~~SV1.~MR~~Voltage monitor||6||3.3VIN||I||3.3V||Internally connected to 3.3VIN via 2.2K resistorFor further details, please refer to [[Reset_scheme_(~~BoraXpress~~BORAXpress)~~#MRSTn_.28J2.116.29~~ | Reset_scheme_(BoraXpress)~~#MRSTn~~ ]]

|-

| J2.118||DGND||DGND||-||-||G||-||Digital ground

|-

| J2.120||3.3VIN||3.3VIN||-||3.3VIN||S||~~+3.3V~~||SOM Power Supply

|-

| J2.122||3.3VIN||3.3VIN||-||3.3VIN||S||~~+3.3V~~||SOM Power Supply

|-

| J2.124||DGND||DGND||-||-||G||-||Digital ground

|-

| J2.126||3.3VIN||3.3VIN||-||3.3VIN||S||~~+3.3V~~||SOM Power Supply

|-

| J2.128||3.3VIN||3.3VIN||-||3.3VIN||S||~~+3.3V~~||SOM Power Supply

|-

| J2.130||3.3VIN||3.3VIN||-||3.3VIN||S||~~+3.3V~~||SOM Power Supply

|-

| J2.132||3.3VIN||3.3VIN||-||3.3VIN||S||~~+3.3V~~||SOM Power Supply

|-

| J2.134||3.3VIN||3.3VIN||-||3.3VIN||S||~~+3.3V~~||SOM Power Supply

|-

| J2.136||3.3VIN||3.3VIN||-||3.3VIN||S||~~+3.3V~~||SOM Power Supply

|-

| J2.138||3.3VIN||3.3VIN||-||3.3VIN||S||~~+3.3V~~||SOM Power Supply

|-

| J2.140||DGND||DGND||-||-||G||-||Digital ground

==J3 odd pins (1 to 139)==

{| class="wikitable" {| {{table}}

| style="background:#f0f0f0;" align="center" |'''Pin'''

| style="background:#f0f0f0;" align="center" |'''Pin Name'''

| style="background:#f0f0f0;" align="center" |'''Internal Connections'''

| style="background:#f0f0f0;" align="center" |'''Ball/pin #'''

| style="background:#f0f0f0;" align="center" |'''Supply Group'''

| style="background:#f0f0f0;" align="center" |'''Type'''

| style="background:#f0f0f0;" align="center" |'''Voltage'''

| style="background:#f0f0f0;" align="center" |'''Note'''

|-

| J3.1||DGND||DGND||-||-||G||-||Digital ground

|-

| J3.3||MGTREFCLK0N||FPGA.MGTREFCLK0N_112||V9||MGTAVCC||D||||

|-

| J3.5||MGTREFCLK0P||FPGA.MGTREFCLK0P_112||U9||MGTAVCC||D||||

|-

| J3.7||DGND||DGND||-||-||G||-||Digital ground

|-

| J3.9||MGTxTXP0||FPGA.MGTXTXP0_112||AA3||MGTAVCC||D||||

|-

| J3.11||MGTxTXN0||FPGA.MGTXTXN0_112||AB3||MGTAVCC||D||||

|-

| J3.13||DGND||DGND||-||-||G||-||Digital ground

|-

| J3.15||MGTxTXP1||FPGA.MGTXTXP1_112||W4||MGTAVCC||D||||

|-

| J3.17||MGTxTXN1||FPGA.MGTXTXN1_112||Y4||MGTAVCC||D||||

|-

| J3.19||DGND||DGND||-||-||G||-||Digital ground

|-

| J3.21||MGTxTXP2||FPGA.MGTXTXP2_112||AA5||MGTAVCC||D||||

|-

| J3.23||MGTxTXN2||FPGA.MGTXTXN2_112||AB5||MGTAVCC||D||||

|-

| J3.25||DGND||DGND||-||-||G||-||Digital ground

|-

| J3.27||MGTxTXP3||FPGA.MGTXTXP3_112||W2||MGTAVCC||D||||

|-

| J3.29||MGTxTXN3||FPGA.MGTXTXN3_112||Y2||MGTAVCC||D||||

|-

| J3.31||DGND||DGND||-||-||G||-||Digital ground

|-

| J3.33||RFU||-||-||-||-||-||Reserved for future use. Must be left floating.

|-

| J3.35||RFU||-||-||-||-||-||Reserved for future use. Must be left floating.

|-

| J3.37||DGND||DGND||-||-||G||-||Digital ground

|-

| J3.39||IO_L23P_T3_13||FPGA.IO_L23P_T3_13||V16||Bank 13||I/O||User defined||

|-

| J3.41||IO_L23N_T3_13||FPGA.IO_L23N_T3_13||W16||Bank 13||I/O||User defined||

|-

| J3.43||DGND||DGND||-||-||G||-||Digital ground

|-

| J3.45||IO_L9P_T1_DQS_13||FPGA.IO_L9P_T1_DQS_13||AB13||Bank 13||I/O||User defined||

|-

| J3.47||IO_L9N_T1_DQS_13||FPGA.IO_L9N_T1_DQS_13||AB14||Bank 13||I/O||User defined||

|-

| J3.49||DGND||DGND||-||-||G||-||Digital ground

|-

| J3.51||IO_L7P_T1_13||FPGA.IO_L7P_T1_13||AA11||Bank 13||I/O||User defined||

|-

| J3.53||IO_L7N_T1_13||FPGA.IO_L7N_T1_13||AB11||Bank 13||I/O||User defined||

|-

| J3.55||DGND||DGND||-||-||G||-||Digital ground

|-

| J3.57||IO_L5P_T0_13||FPGA.IO_L5P_T0_13||U11||Bank 13||I/O||User defined||

|-

| J3.59||IO_L5N_T0_13||FPGA.IO_L5N_T0_13||U12||Bank 13||I/O||User defined||

|-

| J3.61||DGND||DGND||-||-||G||-||Digital ground

|-

| J3.63||IO_L4P_T0_13||FPGA.IO_L4P_T0_13||V11||Bank 13||I/O||User defined||

|-

| J3.65||IO_L4N_T0_13||FPGA.IO_L4N_T0_13||W11||Bank 13||I/O||User defined||

|-

| J3.67||DGND||DGND||-||-||G||-||Digital ground

|-

| J3.69||DGND||DGND||-||-||G||-||Digital ground

|-

| J3.71||IO_L3P_T0_DQS_13||FPGA.IO_L3P_T0_DQS_13||W12||Bank 13||I/O||User defined||

|-

| J3.73||IO_L3N_T0_DQS_13||FPGA.IO_L3N_T0_DQS_13||W13||Bank 13||I/O||User defined||

|-

| J3.75||DGND||DGND||-||-||G||-||Digital ground

|-

| J3.77||IO_L2P_T0_13||FPGA.IO_L2P_T0_13||V15||Bank 13||I/O||User defined||

|-

| J3.79||IO_L2N_T0_13||FPGA.IO_L2N_T0_13||W15||Bank 13||I/O||User defined||

|-

| J3.81||DGND||DGND||-||-||G||-||Digital ground

|-

| J3.83||IO_L1P_T0_13||FPGA.IO_L1P_T0_13||V13||Bank 13||I/O||User defined||

|-

| J3.85||IO_L1N_T0_13||FPGA.IO_L1N_T0_13||V14||Bank 13||I/O||User defined||

|-

| J3.87||DGND||DGND||-||-||G||-||Digital ground

|-

| J3.89||IO_25_13||FPGA.IO_25_13||U16||Bank 13||I/O||User defined||

|-

| J3.91||IO_0_13||FPGA.IO_0_13||T16||Bank 13||I/O||User defined||

|-

| J3.93||DGND||DGND||-||-||G||-||Digital ground

|-

| J3.95||VDDIO_BANK13||FPGA.VCCO_13||AA13 AB20 T18 Y16 W19 V12 U15||Bank 13||S||User defined||Bank13 I/O Power Supply

|-

| J3.97||VDDIO_BANK13||FPGA.VCCO_13||AA13 AB20 T18 Y16 W19 V12 U15||Bank 13||S||User defined||Bank13 I/O Power Supply

|-

| J3.99||VDDIO_BANK13||FPGA.VCCO_13||AA13 AB20 T18 Y16 W19 V12 U15||Bank 13||S||User defined||Bank13 I/O Power Supply

|-

| J3.101||DGND||DGND||-||-||G||-||Digital ground

|-

| J3.103||DGND||DGND||-||-||G||-||Digital ground

|-

| J3.105||IO_L21P_T3_DQS_13||FPGA.IO_L21P_T3_DQS_13||V18||Bank 13||I/O||User defined||

|-

| J3.107||IO_L21N_T3_DQS_13||FPGA.IO_L21N_T3_DQS_13||W18||Bank 13||I/O||User defined||

|-

| J3.109||DGND||DGND||-||-||G||-||Digital ground

|-

| J3.111||IO_L19P_T3_13||FPGA.IO_L19P_T3_13||R17||Bank 13||I/O||User defined||

|-

| J3.113||IO_L19N_T3_VREF_13||FPGA.IO_L19N_T3_VREF_13||T17||Bank 13||I/O||User defined||

|-

| J3.115||DGND||DGND||-||-||G||-||Digital ground

|-

| J3.117||IO_L18P_T2_13||FPGA.IO_L18P_T2_13||AA19||Bank 13||I/O||User defined||

|-

| J3.119||IO_L18N_T2_13||FPGA.IO_L18N_T2_13||AA20||Bank 13||I/O||User defined||

|-

| J3.121||DGND||DGND||-||-||G||-||Digital ground

|-

| J3.123||IO_L16P_T2_13||FPGA.IO_L16P_T2_13||AB18||Bank 13||I/O||User defined||

|-

| J3.125||IO_L16N_T2_13||FPGA.IO_L16N_T2_13||AB19||Bank 13||I/O||User defined||

|-

| J3.127||DGND||DGND||-||-||G||-||Digital ground

|-

| J3.129||IO_L14P_T2_SRCC_13||FPGA.IO_L14P_T2_SRCC_13||AA16||Bank 13||I/O||User defined||

|-

| J3.131||IO_L14N_T2_SRCC_13||FPGA.IO_L14N_T2_SRCC_13||AA17||Bank 13||I/O||User defined||

|-

| J3.133||DGND||DGND||-||-||G||-||Digital ground

|-

| J3.135||IO_L12P_T1_MRCC_13||FPGA.IO_L12P_T1_MRCC_13||Y14||Bank 13||I/O||User defined||

|-

| J3.137||IO_L12N_T1_MRCC_13||FPGA.IO_L12N_T1_MRCC_13||Y15||Bank 13||I/O||User defined||

|-

| J3.139||DGND||DGND||-||-||G||-||Digital ground

|}

==J3 even pins (2 to 140)==

{| class="wikitable" {| {{table}}

| style="background:#f0f0f0;" align="center" |'''Pin'''

| style="background:#f0f0f0;" align="center" |'''Pin Name'''

| style="background:#f0f0f0;" align="center" |'''Internal Connections'''

| style="background:#f0f0f0;" align="center" |'''Ball/pin #'''

| style="background:#f0f0f0;" align="center" |'''Supply Group'''

| style="background:#f0f0f0;" align="center" |'''Type'''

| style="background:#f0f0f0;" align="center" |'''Voltage'''

| style="background:#f0f0f0;" align="center" |'''Note'''

|-

| J3.2||DGND||DGND||-||-||G||-||Digital ground

|-

| J3.4||DGND||DGND||-||-||G||-||Digital ground

|-

| J3.6||MGTREFCLK1N||FPGA.MGTREFCLK1N_112||V5||MGTAVCC||D||||

|-

| J3.8||MGTREFCLK1P||FPGA.MGTREFCLK1P_112||U5||MGTAVCC||D||||

|-

| J3.10||DGND||DGND||-||-||G||-||Digital ground

|-

| J3.12||MGTxRXP0||FPGA.MGTXRXP0_112||AA7||MGTAVCC||D||||

|-

| J3.14||MGTxRXN0||FPGA.MGTXRXN0_112||AB7||MGTAVCC||D||||

|-

| J3.16||DGND||DGND||-||-||G||-||Digital ground

|-

| J3.18||MGTxRXP1||FPGA.MGTXRXP1_112||W8||MGTAVCC||D||||

|-

| J3.20||MGTxRXN1||FPGA.MGTXRXN1_112||Y8||MGTAVCC||D||||

|-

| J3.22||DGND||DGND||-||-||G||-||Digital ground

|-

| J3.24||MGTxRXP2||FPGA.MGTXRXP2_112||AA9||MGTAVCC||D||||

|-

| J3.26||MGTxRXN2||FPGA.MGTXRXN2_112||AB9||MGTAVCC||D||||

|-

| J3.28||DGND||DGND||-||-||G||-||Digital ground

|-

| J3.30||MGTxRXP3||FPGA.MGTXRXP3_112||W6||MGTAVCC||D||||

|-

| J3.32||MGTxRXN3||FPGA.MGTXRXN3_112||Y6||MGTAVCC||D||||

|-

| J3.34||DGND||DGND||-||-||G||-||Digital ground

|-

| J3.36||DGND||DGND||-||-||G||-||Digital ground

|-

| J3.38||IO_L24P_T3_13||FPGA.IO_L24P_T3_13||W17||Bank 13||I/O||User defined||

|-

| J3.40||IO_L24N_T3_13||FPGA.IO_L24N_T3_13||Y17||Bank 13||I/O||User defined||

|-

| J3.42||DGND||DGND||-||-||G||-||Digital ground

|-

| J3.44||IO_L10P_T1_13||FPGA.IO_L10P_T1_13||Y12||Bank 13||I/O||User defined||

|-

| J3.46||IO_L10N_T1_13||FPGA.IO_L10N_T1_13||Y13||Bank 13||I/O||User defined||

|-

| J3.48||DGND||DGND||-||-||G||-||Digital ground

|-

| J3.50||IO_L8P_T1_13||FPGA.IO_L8P_T1_13||AA12||Bank 13||I/O||User defined||

|-

| J3.52||IO_L8N_T1_13||FPGA.IO_L8N_T1_13||AB12||Bank 13||I/O||User defined||

|-

| J3.54||DGND||DGND||-||-||G||-||Digital ground

|-

| J3.56||IO_L6P_T0_13||FPGA.IO_L6P_T0_13||U13||Bank 13||I/O||User defined||

|-

| J3.58||IO_L6N_T0_VREF_13||FPGA.IO_L6N_T0_VREF_13||U14||Bank 13||I/O||User defined||

|-

| J3.60||DGND||DGND||-||-||G||-||Digital ground

|-

| J3.62||MON_MGTAVCC||||||||A||||By default this pin must not be connected. Optionally it can route power voltage generated by BoraXpress PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.

|-

| J3.64||MON_MGTAVCCAUX||||||||A||||By default this pin must not be connected. Optionally it can route power voltage generated by BoraXpress PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.

|-

| J3.66||MON_MGTAVTT||||||||A||||By default this pin must not be connected. Optionally it can route power voltage generated by BoraXpress PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.

|-

| J3.68||DGND||DGND||-||-||G||-||Digital ground

|-

| J3.70||RFU||-||-||-||-||-||Reserved for future use. Must be left floating.

|-

| J3.72||MON_VCCPLL||||||||A||||By default this pin must not be connected. Optionally it can route power voltage generated by BoraXpress PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.

|-

| J3.74||MON_XADC_VCC||||||||A||||By default this pin must not be connected. Optionally it can route power voltage generated by BoraXpress PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.

|-

| J3.76||MON_FPGA_VDDIO_BANK35||||||||A||||By default this pin must not be connected. Optionally it can route power voltage generated by BoraXpress PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.

|-

| J3.78||MON_FPGA_VDDIO_BANK34||||||||A||||By default this pin must not be connected. Optionally it can route power voltage generated by BoraXpress PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.

|-

| J3.80||MON_FPGA_VDDIO_BANK13||||||||A||||By default this pin must not be connected. Optionally it can route power voltage generated by BoraXpress PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.

|-

| J3.82||MON_1.8V_IO||||||||A||||By default this pin must not be connected. Optionally it can route power voltage generated by BoraXpress PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.

|-

| J3.84||MON_3.3V||||||||A||||By default this pin must not be connected. Optionally it can route power voltage generated by BoraXpress PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.

|-

| J3.86||MON_1V2_ETH||||||||A||||By default this pin must not be connected. Optionally it can route power voltage generated by BoraXpress PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.

|-

| J3.88||MON_VDDQ_1V5||||||||A||||By default this pin must not be connected. Optionally it can route power voltage generated by BoraXpress PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.

|-

| J3.90||MON_1.8V||||||||A||||By default this pin must not be connected. Optionally it can route power voltage generated by BoraXpress PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.

|-

| J3.92||MON_1.0V||||||||A||||By default this pin must not be connected. Optionally it can route power voltage generated by BoraXpress PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.

|-

| J3.94||DGND||DGND||-||-||G||-||Digital ground

|-

| J3.96||VDDIO_BANK13||FPGA.VCCO_13||AA13 AB20 T18 Y16 W19 V12 U15||Bank 13||S||User defined||Bank13 I/O Power Supply

|-

| J3.98||VDDIO_BANK13||FPGA.VCCO_13||AA13 AB20 T18 Y16 W19 V12 U15||Bank 13||S||User defined||Bank13 I/O Power Supply

|-

| J3.100||RFU||-||-||-||-||-||Reserved for future use. Must be left floating.

|-

| J3.102||DGND||DGND||-||-||G||-||Digital ground

|-

| J3.104||IO_L22P_T3_13||FPGA.IO_L22P_T3_13||U17||Bank 13||I/O||User defined||

|-

| J3.106||IO_L22N_T3_13||FPGA.IO_L22N_T3_13||U18||Bank 13||I/O||User defined||

|-

| J3.108||DGND||DGND||-||-||G||-||Digital ground

|-

| J3.110||IO_L20P_T3_13||FPGA.IO_L20P_T3_13||U19||Bank 13||I/O||User defined||

|-

| J3.112||IO_L20N_T3_13||FPGA.IO_L20N_T3_13||V19||Bank 13||I/O||User defined||

|-

| J3.114||DGND||DGND||-||-||G||-||Digital ground

|-

| J3.116||IO_L17P_T2_13||FPGA.IO_L17P_T2_13||AB16||Bank 13||I/O||User defined||

|-

| J3.118||IO_L17N_T2_13||FPGA.IO_L17N_T2_13||AB17||Bank 13||I/O||User defined||

|-

| J3.120||DGND||DGND||-||-||G||-||Digital ground

|-

| J3.122||IO_L15P_T2_DQS_13||FPGA.IO_L15P_T2_DQS_13||AB21||Bank 13||I/O||User defined||

|-

| J3.124||IO_L15N_T2_DQS_13||FPGA.IO_L15N_T2_DQS_13||AB22||Bank 13||I/O||User defined||

|-

| J3.126||DGND||DGND||-||-||G||-||Digital ground

|-

| J3.128||IO_L13P_T2_MRCC_13||FPGA.IO_L13P_T2_MRCC_13||Y18||Bank 13||I/O||User defined||

|-

| J3.130||IO_L13N_T2_MRCC_13||FPGA.IO_L13N_T2_MRCC_13||Y19||Bank 13||I/O||User defined||

|-

| J3.132||DGND||DGND||-||-||G||-||Digital ground

|-

| J3.134||IO_L11P_T1_SRCC_13||FPGA.IO_L11P_T1_SRCC_13||AA14||Bank 13||I/O||User defined||

|-

| J3.136||IO_L11N_T1_SRCC_13||FPGA.IO_L11N_T1_SRCC_13||AA15||Bank 13||I/O||User defined||

|-

| J3.138||DGND||DGND||-||-||G||-||Digital ground

|-

| J3.140||DGND||DGND||-||-||G||-||Digital ground

|}

U0001

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