Bureaucrats, dave_user, Administrators
4,650
edits
Changes
→J3 odd pins (1 to 139)
==J3 odd pins (1 to 139)==
{| class="wikitable" {| {{table}}
| align="center" style="background:#f0f0f0;"|'''Pin'''
| align="center" style="background:#f0f0f0;"|'''Pin Name'''
| align="center" style="background:#f0f0f0;"|'''Internal Connections'''
| align="center" style="background:#f0f0f0;"|'''Ball/pin #'''
| align="center" style="background:#f0f0f0;"|'''Supply Group'''
| align="center" style="background:#f0f0f0;"|'''Type'''
| align="center" style="background:#f0f0f0;"|'''Voltage'''
| align="center" style="background:#f0f0f0;"|'''Note'''
|-
| J3.1||DGND||DGND||-||-||G||-||Digital ground
|-
| J3.3||MGTREFCLK0N||FPGA.MGTREFCLK0N_112||V9||MGTAVCC||D||||
|-
| J3.5||MGTREFCLK0P||FPGA.MGTREFCLK0P_112||U9||MGTAVCC||D||||
|-
| J3.7||DGND||DGND||-||-||G||-||Digital ground
|-
| J3.9||MGTxTXP0||FPGA.MGTXTXP0_112||AA3||MGTAVCC||D||||
|-
| J3.11||MGTxTXN0||FPGA.MGTXTXN0_112||AB3||MGTAVCC||D||||
|-
| J3.13||DGND||DGND||-||-||G||-||Digital ground
|-
| J3.15||MGTxTXP1||FPGA.MGTXTXP1_112||W4||MGTAVCC||D||||
|-
| J3.17||MGTxTXN1||FPGA.MGTXTXN1_112||Y4||MGTAVCC||D||||
|-
| J3.19||DGND||DGND||-||-||G||-||Digital ground
|-
| J3.21||MGTxTXP2||FPGA.MGTXTXP2_112||AA5||MGTAVCC||D||||
|-
| J3.23||MGTxTXN2||FPGA.MGTXTXN2_112||AB5||MGTAVCC||D||||
|-
| J3.25||DGND||DGND||-||-||G||-||Digital ground
|-
| J3.27||MGTxTXP3||FPGA.MGTXTXP3_112||W2||MGTAVCC||D||||
|-
| J3.29||MGTxTXN3||FPGA.MGTXTXN3_112||Y2||MGTAVCC||D||||
|-
| J3.31||DGND||DGND||-||-||G||-||Digital ground
|-
| J3.33||RFU||-||-||-||-||-||Reserved for future use. Must be left floating.
|-
| J3.35||RFU||-||-||-||-||-||Reserved for future use. Must be left floating.
|-
| J3.37||DGND||DGND||-||-||G||-||Digital ground
|-
| J3.39||IO_L23P_T3_13||FPGA.IO_L23P_T3_13||V16||Bank 13||I/O||User defined||
|-
| J3.41||IO_L23N_T3_13||FPGA.IO_L23N_T3_13||W16||Bank 13||I/O||User defined||
|-
| J3.43||DGND||DGND||-||-||G||-||Digital ground
|-
| J3.45||IO_L9P_T1_DQS_13||FPGA.IO_L9P_T1_DQS_13||AB13||Bank 13||I/O||User defined||
|-
| J3.47||IO_L9N_T1_DQS_13||FPGA.IO_L9N_T1_DQS_13||AB14||Bank 13||I/O||User defined||
|-
| J3.49||DGND||DGND||-||-||G||-||Digital ground
|-
| J3.51||IO_L7P_T1_13||FPGA.IO_L7P_T1_13||AA11||Bank 13||I/O||User defined||
|-
| J3.53||IO_L7N_T1_13||FPGA.IO_L7N_T1_13||AB11||Bank 13||I/O||User defined||
|-
| J3.55||DGND||DGND||-||-||G||-||Digital ground
|-
| J3.57||IO_L5P_T0_13||FPGA.IO_L5P_T0_13||U11||Bank 13||I/O||User defined||
|-
| J3.59||IO_L5N_T0_13||FPGA.IO_L5N_T0_13||U12||Bank 13||I/O||User defined||
|-
| J3.61||DGND||DGND||-||-||G||-||Digital ground
|-
| J3.63||IO_L4P_T0_13||FPGA.IO_L4P_T0_13||V11||Bank 13||I/O||User defined||
|-
| J3.65||IO_L4N_T0_13||FPGA.IO_L4N_T0_13||W11||Bank 13||I/O||User defined||
|-
| J3.67||DGND||DGND||-||-||G||-||Digital ground
|-
| J3.69||DGND||DGND||-||-||G||-||Digital ground
|-
| J3.71||IO_L3P_T0_DQS_13||FPGA.IO_L3P_T0_DQS_13||W12||Bank 13||I/O||User defined||
|-
| J3.73||IO_L3N_T0_DQS_13||FPGA.IO_L3N_T0_DQS_13||W13||Bank 13||I/O||User defined||
|-
| J3.75||DGND||DGND||-||-||G||-||Digital ground
|-
| J3.77||IO_L2P_T0_13||FPGA.IO_L2P_T0_13||V15||Bank 13||I/O||User defined||
|-
| J3.79||IO_L2N_T0_13||FPGA.IO_L2N_T0_13||W15||Bank 13||I/O||User defined||
|-
| J3.81||DGND||DGND||-||-||G||-||Digital ground
|-
| J3.83||IO_L1P_T0_13||FPGA.IO_L1P_T0_13||V13||Bank 13||I/O||User defined||
|-
| J3.85||IO_L1N_T0_13||FPGA.IO_L1N_T0_13||V14||Bank 13||I/O||User defined||
|-
| J3.87||DGND||DGND||-||-||G||-||Digital ground
|-
| J3.89||IO_25_13||FPGA.IO_25_13||U16||Bank 13||I/O||User defined||
|-
| J3.91||IO_0_13||FPGA.IO_0_13||T16||Bank 13||I/O||User defined||
|-
| J3.93||DGND||DGND||-||-||G||-||Digital ground
|-
| J3.95||VDDIO_BANK13||FPGA.VCCO_13||AA13
AB20
T18
Y16
W19
V12
U15||Bank 13||S||User defined||Bank13 I/O Power Supply
|-
| J3.97||VDDIO_BANK13||FPGA.VCCO_13||AA13
AB20
T18
Y16
W19
V12
U15||Bank 13||S||User defined||Bank13 I/O Power Supply
|-
| J3.99||VDDIO_BANK13||FPGA.VCCO_13||AA13
AB20
T18
Y16
W19
V12
U15||Bank 13||S||User defined||Bank13 I/O Power Supply
|-
| J3.101||DGND||DGND||-||-||G||-||Digital ground
|-
| J3.103||DGND||DGND||-||-||G||-||Digital ground
|-
| J3.105||IO_L21P_T3_DQS_13||FPGA.IO_L21P_T3_DQS_13||V18||Bank 13||I/O||User defined||
|-
| J3.107||IO_L21N_T3_DQS_13||FPGA.IO_L21N_T3_DQS_13||W18||Bank 13||I/O||User defined||
|-
| J3.109||DGND||DGND||-||-||G||-||Digital ground
|-
| J3.111||IO_L19P_T3_13||FPGA.IO_L19P_T3_13||R17||Bank 13||I/O||User defined||
|-
| J3.113||IO_L19N_T3_VREF_13||FPGA.IO_L19N_T3_VREF_13||T17||Bank 13||I/O||User defined||
|-
| J3.115||DGND||DGND||-||-||G||-||Digital ground
|-
| J3.117||IO_L18P_T2_13||FPGA.IO_L18P_T2_13||AA19||Bank 13||I/O||User defined||
|-
| J3.119||IO_L18N_T2_13||FPGA.IO_L18N_T2_13||AA20||Bank 13||I/O||User defined||
|-
| J3.121||DGND||DGND||-||-||G||-||Digital ground
|-
| J3.123||IO_L16P_T2_13||FPGA.IO_L16P_T2_13||AB18||Bank 13||I/O||User defined||
|-
| J3.125||IO_L16N_T2_13||FPGA.IO_L16N_T2_13||AB19||Bank 13||I/O||User defined||
|-
| J3.127||DGND||DGND||-||-||G||-||Digital ground
|-
| J3.129||IO_L14P_T2_SRCC_13||FPGA.IO_L14P_T2_SRCC_13||AA16||Bank 13||I/O||User defined||
|-
| J3.131||IO_L14N_T2_SRCC_13||FPGA.IO_L14N_T2_SRCC_13||AA17||Bank 13||I/O||User defined||
|-
| J3.133||DGND||DGND||-||-||G||-||Digital ground
|-
| J3.135||IO_L12P_T1_MRCC_13||FPGA.IO_L12P_T1_MRCC_13||Y14||Bank 13||I/O||User defined||
|-
| J3.137||IO_L12N_T1_MRCC_13||FPGA.IO_L12N_T1_MRCC_13||Y15||Bank 13||I/O||User defined||
|-
| J3.139||DGND||DGND||-||-||G||-||Digital ground
|}
==J3 even pins (2 to 140)==
