Difference between revisions of "Pinout (BORAXpress)"

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(→‎J1 even pins (2 to 140))
(→‎J2 even pins (2 to 140))
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==J2 even pins (2 to 140)==
 
==J2 even pins (2 to 140)==
 +
{| class="wikitable" {| {{table}}
 +
| align="center" style="background:#f0f0f0;"|'''Pin'''
 +
| align="center" style="background:#f0f0f0;"|'''Pin Name'''
 +
| align="center" style="background:#f0f0f0;"|'''Internal Connections'''
 +
| align="center" style="background:#f0f0f0;"|'''Ball/pin #'''
 +
| align="center" style="background:#f0f0f0;"|'''Supply Group'''
 +
| align="center" style="background:#f0f0f0;"|'''Type'''
 +
| align="center" style="background:#f0f0f0;"|'''Voltage'''
 +
| align="center" style="background:#f0f0f0;"|'''Note'''
 +
|-
 +
| J2.2||DGND||DGND||-||-||G||-||Digital ground
 +
|-
 +
| J2.4||IO_L9P_T1_DQS_34||FPGA.IO_L9P_T1_DQS_34||J3||Bank 34||I/O||User defined||
 +
|-
 +
| J2.6||IO_L9N_T1_DQS_34||FPGA.IO_L9N_T1_DQS_34||K2||Bank 34||I/O||User defined||
 +
|-
 +
| J2.8||IO_L7P_T1_34||FPGA.IO_L7P_T1_34||J5||Bank 34||I/O||User defined||
 +
|-
 +
| J2.10||IO_L7N_T1_34||FPGA.IO_L7N_T1_34||K5||Bank 34||I/O||User defined||
 +
|-
 +
| J2.12||DGND||DGND||-||-||G||-||Digital ground
 +
|-
 +
| J2.14||IO_L5P_T0_34||FPGA.IO_L5P_T0_34||N8||Bank 34||I/O||User defined||
 +
|-
 +
| J2.16||IO_L5N_T0_34||FPGA.IO_L5N_T0_34||P8||Bank 34||I/O||User defined||
 +
|-
 +
| J2.18||IO_L4P_T0_34||FPGA.IO_L4P_T0_34||L6||Bank 34||I/O||User defined||
 +
|-
 +
| J2.20||IO_L4N_T0_34||FPGA.IO_L4N_T0_34||M6||Bank 34||I/O||User defined||
 +
|-
 +
| J2.22||DGND||DGND||-||-||G||-||Digital ground
 +
|-
 +
| J2.24||IO_L24P_T3_34||FPGA.IO_L24P_T3_34||P7||Bank 34||I/O||User defined||
 +
|-
 +
| J2.26||IO_L24N_T3_34||FPGA.IO_L24N_T3_34||R7||Bank 34||I/O||User defined||
 +
|-
 +
| J2.28||IO_L23P_T3_34||FPGA.IO_L23P_T3_34||R5||Bank 34||I/O||User defined||
 +
|-
 +
| J2.30||IO_L23N_T3_34||FPGA.IO_L23N_T3_34||R4||Bank 34||I/O||User defined||
 +
|-
 +
| J2.32||DGND||DGND||-||-||G||-||Digital ground
 +
|-
 +
| J2.34||IO_L20P_T3_34||FPGA.IO_L20P_T3_34||P6||Bank 34||I/O||User defined||
 +
|-
 +
| J2.36||IO_L20N_T3_34||FPGA.IO_L20N_T3_34||P5||Bank 34||I/O||User defined||
 +
|-
 +
| J2.38||IO_L1P_T0_34||FPGA.IO_L1P_T0_34||J8||Bank 34||I/O||User defined||
 +
|-
 +
| J2.40||IO_L1N_T0_34||FPGA.IO_L1N_T0_34||K8||Bank 34||I/O||User defined||
 +
|-
 +
| J2.42||DGND||DGND||-||-||G||-||Digital ground
 +
|-
 +
| J2.44||IO_L17P_T2_34||FPGA.IO_L17P_T2_34||R3||Bank 34||I/O||User defined||
 +
|-
 +
| J2.46||IO_L17N_T2_34||FPGA.IO_L17N_T2_34||R2||Bank 34||I/O||User defined||
 +
|-
 +
| J2.48||IO_L16P_T2_34||FPGA.IO_L16P_T2_34||N1||Bank 34||I/O||User defined||
 +
|-
 +
| J2.50||IO_L16N_T2_34||FPGA.IO_L16N_T2_34||P1||Bank 34||I/O||User defined||
 +
|-
 +
| J2.52||DGND||DGND||-||-||G||-||Digital ground
 +
|-
 +
| J2.54||IO_L14P_T2_SRCC_34||FPGA.IO_L14P_T2_SRCC_34||U2||Bank 34||I/O||User defined||
 +
|-
 +
| J2.56||IO_L14N_T2_SRCC_34||FPGA.IO_L14N_T2_SRCC_34||U1||Bank 34||I/O||User defined||
 +
|-
 +
| J2.58||DGND||DGND||-||-||G||-||Digital ground
 +
|-
 +
| J2.60||IO_L12P_T1_MRCC_34||FPGA.IO_L12P_T1_MRCC_34||L5||Bank 34||I/O||User defined||
 +
|-
 +
| J2.62||IO_L12N_T1_MRCC_34||FPGA.IO_L12N_T1_MRCC_34||L4||Bank 34||I/O||User defined||
 +
|-
 +
| J2.64||DGND||DGND||-||-||G||-||Digital ground
 +
|-
 +
| J2.66||VDDIO_BANK34||FPGA.VCCO_34||K6
 +
H2
 +
L3
 +
N7
 +
P4
 +
R1||Bank 34||S||User defined||Bank34 I/O Power Supply
 +
|-
 +
| J2.68||VDDIO_BANK34||FPGA.VCCO_34||K6
 +
H2
 +
L3
 +
N7
 +
P4
 +
R1||Bank 34||S||User defined||Bank34 I/O Power Supply
 +
|-
 +
| J2.70||VDDIO_BANK34||FPGA.VCCO_34||K6
 +
H2
 +
L3
 +
N7
 +
P4
 +
R1||Bank 34||S||User defined||Bank34 I/O Power Supply
 +
|-
 +
| J2.72||VDDIO_BANK34||FPGA.VCCO_34||K6
 +
H2
 +
L3
 +
N7
 +
P4
 +
R1||Bank 34||S||User defined||Bank34 I/O Power Supply
 +
|-
 +
| J2.74||RFU||-||-||-||-||-||Reserved for future use. Must be left floating.
 +
|-
 +
| J2.76||RFU||-||-||-||-||-||Reserved for future use. Must be left floating.
 +
|-
 +
| J2.78||RFU||-||-||-||-||-||Reserved for future use. Must be left floating.
 +
|-
 +
| J2.80||JTAG_TDO||CPU.TDO_0||G9||BANK 0||O||3.3V||
 +
|-
 +
| J2.82||JTAG_TDI||CPU.TDI_0||H9||BANK 0||I||3.3V||
 +
|-
 +
| J2.84||JTAG_TMS||CPU.TMS_0||H10||BANK 0||I||3.3V||
 +
|-
 +
| J2.86||JTAG_TCK||CPU.TCK_0||H11||BANK 0||I||3.3V||
 +
|-
 +
| J2.88||DGND||DGND||-||-||G||-||Digital ground
 +
|-
 +
| J2.90||FPGA_INIT_B||FPGA.INIT_B_0||T8||BANK 0||I/O||3.3V||
 +
|-
 +
| J2.92||FPGA_PROGRAM_B||FPGA.PROGRAM_B_0||V10||BANK 0||I||3.3V||
 +
|-
 +
| J2.94||FPGA_DONE||FPGA.DONE0||T10||BANK 0||I/O||3.3V||
 +
|-
 +
| J2.96||WD_SET2||WDT.SET2||6||3.3V||I||3.3V||
 +
|-
 +
| J2.98||WD_SET1||WDT.SET1||5||3.3V||I||3.3V||
 +
|-
 +
| J2.100||WD_SET0||WDT.SET0||4||3.3V||I||3.3V||
 +
|-
 +
| J2.102||DGND||DGND||-||-||G||-||Digital ground
 +
|-
 +
| J2.104||PS_MIO50_501||CPU.PS_MIO50_501
 +
USBOTG.RESETB||D10
 +
22||BANK 501||I/O||1.8V||For further details, please refer to [[Reset_scheme_(BoraXpress)#PS_MIO50_501_.28J2.104.29 | Reset_scheme_(BoraXpress)#PS_MIO50_501]]
 +
|-
 +
| J2.106||PS_MIO51_501||CPU.PS_MIO51_501
 +
ETHPHY1GB.RESET_N||C13
 +
42||BANK 501||I/O||1.8V||For further details, please refer to [[Reset_scheme_(BoraXpress)#PS_MIO51_501_.28J2.106.29 | Reset_scheme_(BoraXpress)#PS_MIO51_501 ]]
 +
|-
 +
| J2.108||SOM_PGOOD||SOM_PGOOD_LOGIC.OUT||n.a.||3.3V||O||3.3V||Internally connected to DGND via 100K resistor
 +
|-
 +
| J2.110||CB_PWR_GOOD||1.0VREGULATOR.ENABLE
 +
SOM_PGOOD_LOGIC.IN||n.a.||3.3VIN||I||3.3V||Internally connected to 3.3VIN via 10K resistor
 +
|-
 +
| J2.112||SYS_RSTn||CPU.PS_SRST_B_501 ||C14||BANK 501||I||1.8V||Internally connected to 1.8V via 20K resistor
 +
|-
 +
| J2.114||PORSTn||CPU.PS_POR_B_500
 +
SV1.~RST
 +
SV2.~RST
 +
WD.~WDO
 +
NOR.~RESET/RFU||B18
 +
5
 +
5
 +
7
 +
A4||BANK 500||I/O||3.3V||Internally connected to 3.3VIN via 2.2K resistor
 +
For further details, please refer to [[Reset_scheme_(BoraXpress)#PORSTn_.28J2.114.29 | Reset_scheme_(BoraXpress)#PORSTn ]]
 +
|-
 +
| J2.116||MRSTn||SV1.~MR||6||3.3VIN||I||3.3V||Internally connected to 3.3VIN via 2.2K resistor
 +
For further details, please refer to [[Reset_scheme_(BoraXpress)#MRSTn_.28J2.116.29 | Reset_scheme_(BoraXpress)#MRSTn ]]
 +
|-
 +
| J2.118||DGND||DGND||-||-||G||-||Digital ground
 +
|-
 +
| J2.120||3.3VIN||3.3VIN||-||3.3VIN||S||+3.3V||SOM Power Supply
 +
|-
 +
| J2.122||3.3VIN||3.3VIN||-||3.3VIN||S||+3.3V||SOM Power Supply
 +
|-
 +
| J2.124||DGND||DGND||-||-||G||-||Digital ground
 +
|-
 +
| J2.126||3.3VIN||3.3VIN||-||3.3VIN||S||+3.3V||SOM Power Supply
 +
|-
 +
| J2.128||3.3VIN||3.3VIN||-||3.3VIN||S||+3.3V||SOM Power Supply
 +
|-
 +
| J2.130||3.3VIN||3.3VIN||-||3.3VIN||S||+3.3V||SOM Power Supply
 +
|-
 +
| J2.132||3.3VIN||3.3VIN||-||3.3VIN||S||+3.3V||SOM Power Supply
 +
|-
 +
| J2.134||3.3VIN||3.3VIN||-||3.3VIN||S||+3.3V||SOM Power Supply
 +
|-
 +
| J2.136||3.3VIN||3.3VIN||-||3.3VIN||S||+3.3V||SOM Power Supply
 +
|-
 +
| J2.138||3.3VIN||3.3VIN||-||3.3VIN||S||+3.3V||SOM Power Supply
 +
|-
 +
| J2.140||DGND||DGND||-||-||G||-||Digital ground
 +
|}
  
 
==J3 odd pins (1 to 139)==
 
==J3 odd pins (1 to 139)==
  
 
==J3 even pins (2 to 140)==
 
==J3 even pins (2 to 140)==

Revision as of 11:50, 3 November 2015

HOME SOMs SBCs ToloMEO Embedded Assistant Sale-tag.pngGET A QUOTE Customer-service.pngONLINE HELPDESK
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BORA Xpress.png Applies to BORA Xpress

Introduction[edit | edit source]

This chapter contains the pinout description of the BORA Xpress module, grouped in six tables (two – odd and even pins – for each connector) that report the pin mapping of the three 140-pin BORA Xpress connectors. Each row in the pinout tables contains the following information:

  • Pin: reference to the connector pin
  • Pin Name: pin (signal) name on the BORA Xpress connectors
  • Internal connections: connections to the BORA Xpress components
    • CPU.<x> : pin connected to CPU (processing system) pad named <x>
    • FPGA.<x>: pin connected to FPGA (programmable logic) pad named <x>
    • CAN.<x> : pin connected to the CAN transceiver
    • LAN.<x> : pin connected to the LAN PHY
    • USB.<x> : pin connected to the USB transceiver
    • NAND.<x>: pin connected to the flash NAND
    • NOR.<x>: pin connected to the flash NOR
    • SV.<x>: pin connected to voltage supervisor
    • MTR: pin connected to voltage monitors
  • Ball/pin #: Component ball/pin number connected to signal
  • Supply Group: Power Supply Group
  • Type: pin type
    • I = Input
    • O = Output
    • D = Differential
    • Z = High impedance
    • S = Power supply voltage
    • G = Ground
    • A = Analog signal
  • Voltage: I/O voltage levels

J1 odd pins (1 to 139)[edit | edit source]

Pin Pin Name Internal Connections Ball/pin # Supply Group Type Voltage Note
J1.1 DGND DGND - - G - Digital ground
J1.3 IO_25_VRP_35 FPGA.IO_25_35/IO_25_VRP_35 H5 Bank 35 I/O User defined Optional on-board pull-down
J1.5 IO_L23P_T3_35 FPGA.IO_L10P_T1_AD11P_35 F2 Bank 35 I/O User defined
J1.7 IO_L23N_T3_35 FPGA.IO_L23N_T3_35 F1 Bank 35 I/O User defined
J1.9 IO_L21P_T3_DQS_AD14P_35 FPGA.IO_L21P_T3_DQS_AD14P_35 E4 Bank 35 I/O User defined
J1.11 IO_L21N_T3_DQS_AD14N_35 FPGA.IO_L21N_T3_DQS_AD14N_35 E3 Bank 35 I/O User defined
J1.13 DGND DGND - - - - Digital ground
J1.15 IO_L19P_T3_35 FPGA.IO_L19P_T3_35 H4 Bank 35 I/O User defined
J1.17 IO_L19N_T3_VREF_35 FPGA.IO_L19N_T3_VREF_35 H3 Bank 35 I/O User defined
J1.19 DGND DGND - - G - Digital ground
J1.21 IO_L17P_T2_AD5P_35 FPGA.IO_L17P_T2_AD5P_35 E2 Bank 35 I/O User defined
J1.23 IO_L17N_T2_AD5N_35 FPGA.IO_L17N_T2_AD5N_35 D2
J1.25 IO_L15P_T2_DQS_AD12P_35 FPGA.IO_L15P_T2_DQS_AD12P_35 A2
J1.27 IO_L15N_T2_DQS_AD12N_35 FPGA.IO_L15N_T2_DQS_AD12N_35 A1
J1.29 DGND DGND - - G - Digital ground
J1.31 IO_L13P_T2_MRCC_35 FPGA.IO_L13P_T2_MRCC_35 B4
J1.33 IO_L13N_T2_MRCC_35 FPGA.IO_L13N_T2_MRCC_35 B3
J1.35 DGND DGND - - G - Digital ground
J1.37 IO_L11P_T1_SRCC_35 FPGA.IO_L11P_T1_SRCC_35 C6
J1.39 IO_L11N_T1_SRCC_35 FPGA.IO_L11N_T1_SRCC_35 C5
J1.41 IO_L9P_T1_DQS_AD3P_35 FPGA.IO_L9P_T1_DQS_AD3P_35 A7
J1.43 IO_L9N_T1_DQS_AD3N_35 FPGA.IO_L9N_T1_DQS_AD3N_35 A6
J1.45 IO_L7P_T1_AD2P_35 FPGA.IO_L7P_T1_AD2P_35 C8
J1.47 IO_L7N_T1_AD2N_35 FPGA.IO_L7N_T1_AD2N_35 B8
J1.49 DGND DGND - - G - Digital ground
J1.51 IO_L5P_T0_AD9P_35 FPGA.IO_L5P_T0_AD9P_35 F5
J1.53 IO_L5N_T0_AD9N_35 FPGA.IO_L5N_T0_AD9N_35 E5
J1.55 IO_L3P_T0_DQS_AD1P_35 FPGA.IO_L3P_T0_DQS_AD1P_35 E8
J1.57 IO_L3N_T0_DQS_AD1N_35 FPGA.IO_L3N_T0_DQS_AD1N_35 D8
J1.59 DGND DGND - - G - Digital ground
J1.61 IO_L1P_T0_AD0P_35 FPGA.IO_L1P_T0_AD0P_35 F7
J1.63 IO_L1N_T0_AD0N_35 FPGA.IO_L1N_T0_AD0N_35 E7
J1.65 DGND DGND - - G - Digital ground
J1.67 VDDIO_BANK35 S
J1.69 XADC_AGND G XADC analog ground (internally connected to DGND)
J1.71 XADC_AGND G XADC analog ground (internally connected to DGND)
J1.73 PS_MIO45_501 CPU.PS_MIO45_501 B14 Bank 501 I/O 1.8V
J1.75 PS_MIO44_501 CPU.PS_MIO44_501 E10 Bank 501 I/O 1.8V
J1.77 PS_MIO43_501 CPU.PS_MIO43_501 B12 Bank 501 I/O 1.8V
J1.79 PS_MIO42_501 CPU.PS_MIO42_501 D15 Bank 501 I/O 1.8V
J1.81 PS_MIO41_501 CPU.PS_MIO41_501 C15 Bank 501 I/O 1.8V
J1.83 DGND DGND - - G - Digital ground
J1.85 PS_MIO40_501 CPU.PS_MIO40_501 E9 Bank 501 I/O 1.8V
J1.87 ETH_MDIO CPU.PS_MIO53_501 C11 Bank 501 I/O 1.8V 1kOhm pull-up
J1.89 ETH_MDC CPU.PS_MIO51_501 D13 Bank 501 I/O 1.8V
J1.91 ETH_LED1 LAN.LED1/PME_N1 17 - 1.8V 10kOhm pull-up
J1.93 ETH_LED2 LAN.LED2 15 - 1.8V 10kOhm pull-up
J1.95 DGND DGND - - G - Digital ground
J1.97 ETH_TXRX1_M LAN.TXRXM_B 6 D
J1.99 ETH_TXRX1_P LAN.TXRXP_B 5 D
J1.101 DGND DGND - - G - Digital ground
J1.103 ETH_TXRX0_M LAN.ETH_TXRX0_M 3 D
J1.105 ETH_TXRX0_P LAN.ETH_TXRX0_P 2 D
J1.107 DVDDH LAN.DVDDH 16
34
40
J1.109 RFU - - - - - Reserved fo future use. Must be left floating.
J1.111 USBOTG_CPEN USB.CPEN 7 3.3V
J1.113 OTG_VBUS USB.OTG_VBUS 2
J1.115 OTG_ID USB.ID 1
J1.117 DGND DGND - - G - Digital ground
J1.119 SPI0_DQ3/MODE0/NAND_IO0 CPU.PS_MIO5_500
NOR flash
NAND flash		 CPU.A20 Bank 500 I/O 3.3V This signal is pulled up or down by 20kOhm resistor to select proper bootstrap configuration.
J1.121 SPI0_DQ2/MODE2/NAND_IO2 CPU.PS_MIO4_500
NOR flash
NAND flash		 CPU.E19 Bank 500 I/O 3.3V This signal is pulled up or down by 20kOhm resistor to select proper bootstrap configuration.
J1.123 SPI0_DQ1/MODE1/NAND_WE CPU.PS_MIO3_500
NOR flash
NAND flash		 CPU.F17 Bank 500 I/O 3.3V This signal is pulled up or down by 20kOhm resistor to select proper bootstrap configuration.
J1.125 SPI0_DQ0/MODE3/NAND_ALE CPU.PS_MIO2_500
NOR flash
NAND flash		 CPU.A21 Bank 500 I/O 3.3V This signal is pulled up or down by 20kOhm resistor to select proper bootstrap configuration.
J1.127 DGND DGND - - G - Digital ground
J1.129 SPI0_SCLK/MODE4/NAND_IO1 CPU.PS_MIO6_500
NOR flash
NAND flash		 CPU.A19 Bank 500 I/O 3.3V This signal is pulled up or down by 20kOhm resistor to select proper bootstrap configuration.
J1.131 NAND_BUSY CPU.PS_MIO14_500
NOR flash
NAND flash		 CPU.B17 Bank 500 I/O 3.3V 10kOhm pull-up
J1.133 PS_MIO15_500 CPU.PS_MIO15_500
WDT.WDI		 CPU.E17
WDT.1		 Bank 500 I/O 3.3V See also this page
J1.135 RFU - - - - - Reserved fo future use. Must be left floating.
J1.137 MEM_WPn NAND.WP
NOR.WP/IO2		 NAND.19
NOR.C4		 3.3V
J1.139 DGND DGND - - G - Digital ground

J1 even pins (2 to 140)[edit | edit source]

Pin Pin Name Internal Connections Ball/pin # Supply Group Type Voltage Note
J1.2 VDDIO_BANK35 S
J1.4 DGND DGND - - - G Digital ground
J1.6 IO_L24P_T3_AD15P_35 FPGA.IO_L24P_T3_AD15P_35 H1 Bank 35 I/O User defined
J1.8 IO_L24N_T3_AD15N_35 FPGA.IO_L24N_T3_AD15N_35 G1 Bank 35 I/O User defined
J1.10 IO_L22P_T3_AD7P_35 FPGA.IO_L22P_T3_AD7P_35 G3 Bank 35 I/O User defined
J1.12 IO_L22N_T3_AD7N_35 FPGA.IO_L22N_T3_AD7N_35 G2 Bank 35 I/O User defined
J1.14 DGND DGND - - - G Digital ground
J1.16 IO_L20P_T3_AD6P_35 FPGA.IO_L20P_T3_AD6P_35 G4 Bank 35 I/O User defined
J1.18 IO_L20N_T3_AD6N_35 FPGA.IO_L20N_T3_AD6N_35 F4 Bank 35 I/O User defined
J1.20 IO_L18P_T2_AD13P_35 FPGA.IO_L20N_T3_AD6N_35 B2 Bank 35 I/O User defined
J1.22 IO_L18N_T2_AD13N_35 FPGA.IO_L18N_T2_AD13N_35 B1 Bank 35 I/O User defined
J1.24 DGND DGND - - - G Digital ground
J1.26 IO_L16P_T2_35 FPGA.IO_L16P_T2_35 D1 Bank 35 I/O User defined
J1.28 IO_L16N_T2_35 FPGA.IO_L16N_T2_35 C1 Bank 35 I/O User defined
J1.30 DGND DGND - - - G Digital ground
J1.32 IO_L14P_T2_AD4P_SRCC_35 FPGA.IO_L14P_T2_AD4P_SRCC_35 D3 Bank 35 I/O User defined
J1.34 IO_L14N_T2_AD4N_SRCC_35 FPGA.IO_L14N_T2_AD4N_SRCC_35 C3 Bank 35 I/O User defined
J1.36 IO_L12P_T1_MRCC_35 FPGA.IO_L12P_T1_MRCC_35 D5 Bank 35 I/O User defined
J1.38 DGND DGND - - - G Digital ground
J1.40 IO_L12N_T1_MRCC_35 FPGA.IO_L12N_T1_MRCC_35 C4 Bank 35 I/O User defined
J1.42 IO_L10P_T1_AD11P_35 FPGA.IO_L10P_T1_AD11P_35 A5 Bank 35 I/O User defined
J1.44 IO_L10N_T1_AD11N_35 FPGA.IO_L10N_T1_AD11N_35 A4 Bank 35 I/O User defined
J1.46 IO_L8P_T1_AD10P_35 FPGA.IO_L8P_T1_AD10P_35 B7 Bank 35 I/O User defined
J1.48 DGND DGND - - - G Digital ground
J1.50 IO_L8N_T1_AD10N_35 FPGA.IO_L8N_T1_AD10N_35 B6 Bank 35 I/O User defined
J1.52 IO_L6P_T0_35 FPGA.IO_L6P_T0_35 G6 Bank 35 I/O User defined
J1.54 IO_L6N_T0_VREF_35 FPGA.IO_L6N_T0_VREF_35 F6 Bank 35 I/O User defined
J1.56 IO_L4P_T0_35 FPGA.IO_L4P_T0_35 G8 Bank 35 I/O User defined
J1.58 IO_L4N_T0_35 FPGA.IO_L4N_T0_35 G7 Bank 35 I/O User defined
J1.60 DGND DGND - - - G Digital ground
J1.62 IO_L2P_T0_AD8P_35 FPGA.IO_L2P_T0_AD8P_35 D7 Bank 35 I/O User defined
J1.64 IO_L2N_T0_AD8N_35 FPGA.IO_L2N_T0_AD8N_35 D6 Bank 35 I/O User defined
J1.66 VDDIO_BANK35 S
J1.68 VDDIO_BANK35 S
J1.70 XADC_AGND G XADC analog ground (internally connected to DGND)
J1.72 XADC_AGND G XADC analog ground (internally connected to DGND)
J1.74 IO_0_VRN_35 FPGA.IO_0_35/IO_0_VRN_35 H6 Bank 35 I/O User defined Optional on-board pull-up
J1.76 RFU - - - - - Reserved fo future use. Must be left floating.
J1.78 RFU - - - - - Reserved fo future use. Must be left floating.
J1.80 PS_MIO49_501 CPU.PS_MIO49_501 C9 Bank 501 I/O 1.8V
J1.82 PS_MIO48_501 CPU.PS_MIO48_501 D12 Bank 501 I/O 1.8V
J1.84 PS_MIO47_501 CPU.PS_MIO47_501 B13 Bank 501 I/O 1.8V 10kOhm pull-up

TBD

J1.86 DGND DGND - - - G Digital ground
J1.88 PS_MIO46_501 CPU.PS_MIO46_501 D11 Bank 501 I/O 1.8V 10kOhm pull-up

TBD

J1.90 ETH_INTn Can be optionally connected to Ethernet PHY's INT_N / PME_N2
J1.92 DGND DGND - - - G Digital ground
J1.94 ETH_TXRX3_M LAN.TXRXM_D 11 D
J1.96 ETH_TXRX3_P LAN.TXRXP_D 10 D
J1.98 DGND DGND - - - G Digital ground
J1.100 ETH_TXRX2_M
J1.102 ETH_TXRX2_P
J1.104 DGND DGND - - - G Digital ground
J1.106 CLK125_NDO LAN.CLK125_NDO 41 O 1.8V 10kOhm pull-up
J1.108 RFU - - - - - Reserved fo future use. Must be left floating.
J1.110 RFU - - - - - Reserved fo future use. Must be left floating.
J1.112 DGND DGND - - - G Digital ground
J1.114 USBP1 USB.DP 6 D
J1.116 USBM1 USB.DM 5 D
J1.118 DGND DGND - - - G Digital ground
J1.120 SPI0_CS0n CPU.PS_MIO1_500
NOR flash		 CPU.A22 Bank 500 I/O 3.3V
J1.122 NAND_CS0/SPI0_CS1 CPU.PS_MIO0_500
NAND flash		 CPU.G17 Bank 500 I/O 3.3V 10kOhm pull-up
J1.124 NAND_IO3 CPU.PS_MIO13_500
NAND flash		 CPU.A17 Bank 500 I/O 3.3V
J1.126 NAND_IO4 CPU.PS_MIO9_500
NAND flash		 CPU.C19 Bank 500 I/O 3.3V
J1.128 NAND_IO5 CPU.PS_MIO10_500
NAND flash		 CPU.G16 Bank 500 I/O 3.3V
J1.130 DGND DGND - - - G Digital ground
J1.132 NAND_IO6 CPU.PS_MIO11_500
NAND flash		 CPU.B19 Bank 500 I/O 3.3V
J1.134 NAND_IO7 CPU.PS_MIO12_500
NAND flash		 CPU.C18 Bank 500 I/O 3.3V
J1.136 NAND_RD_B/VCFG1 CPU.PS_MIO8_500
NAND flash		 CPU.E18 Bank 500 I/O 3.3V This signal is pulled up or down by 20kOhm resistor to select proper bootstrap configuration.
J1.138 NAND_CLE/VCFG0 CPU.PS_MIO7_500
NAND flash		 CPU.D18 Bank 500 I/O 3.3V This signal is pulled up or down by 20kOhm resistor to select proper bootstrap configuration.
J1.140 DGND DGND - - - G Digital ground

J2 odd pins (1 to 139)[edit | edit source]

Pin Pin Name Internal Connections Ball/pin # Supply Group Type Voltage Note
J2.1 DGND DGND - - G - Digital ground
J2.3 DGND DGND - - G - Digital ground
J2.5 IO_L8P_T1_34 FPGA.IO_L8P_T1_34 J2 Bank 34 I/O User defined
J2.7 IO_L8N_T1_34 FPGA.IO_L8N_T1_34 J1 Bank 34 I/O User defined
J2.9 IO_L6P_T0_34 FPGA.IO_L6P_T0_34 M8 Bank 34 I/O User defined CAN_RX
J2.11 IO_L6N_T0_VREF_34 FPGA.IO_L6N_T0_VREF_34 M7 Bank 34 I/O User defined
J2.13 DGND DGND - - G - Digital ground
J2.15 IO_L3P_T0_DQS_PUDC_B_34 FPGA.IO_L3P_T0_DQS_PUDC_B_34 K7 Bank 34 I/O User defined Internally connected to VDDIO_BANK34 via 10K resistor
J2.17 IO_L3N_T0_DQS_34 FPGA.IO_L3N_T0_DQS_34 L7 Bank 34 I/O User defined
J2.19 IO_L2P_T0_34 FPGA.IO_L2P_T0_34 J7 Bank 34 I/O User defined
J2.21 IO_L2N_T0_34 FPGA.IO_L2N_T0_34 J6 Bank 34 I/O User defined
J2.23 DGND DGND - - G - Digital ground
J2.25 IO_L22P_T3_34 FPGA.IO_L22P_T3_34 M4 Bank 34 I/O User defined
J2.27 IO_L22N_T3_34 FPGA.IO_L22N_T3_34 M3 Bank 34 I/O User defined
J2.29 IO_L21P_T3_DQS_34 FPGA.IO_L21P_T3_DQS_34 N4 Bank 34 I/O User defined
J2.31 IO_L21N_T3_DQS_34 FPGA.IO_L21N_T3_DQS_34 N3 Bank 34 I/O User defined
J2.33 DGND DGND - - G - Digital ground
J2.35 IO_L19P_T3_34 FPGA.IO_L19P_T3_34 N6 Bank 34 I/O User defined CAN_TX
J2.37 IO_L19N_T3_VREF_34 FPGA.IO_L19N_T3_VREF_34 N5 Bank 34 I/O User defined
J2.39 IO_L18P_T2_34 FPGA.IO_L18P_T2_34 P3 Bank 34 I/O User defined
J2.41 IO_L18N_T2_34 FPGA.IO_L18N_T2_34 P2 Bank 34 I/O User defined
J2.43 DGND DGND - - G - Digital ground
J2.45 IO_L15P_T2_DQS_34 FPGA.IO_L15P_T2_DQS_34 M2 Bank 34 I/O User defined
J2.47 IO_L15N_T2_DQS_34 FPGA.IO_L15N_T2_DQS_34 M1 Bank 34 I/O User defined
J2.49 DGND DGND - - G - Digital ground
J2.51 IO_L13P_T1_MRCC_34 FPGA.IO_L13P_T1_MRCC_34 T2 Bank 34 I/O User defined
J2.53 IO_L13N_T1_MRCC_34 FPGA.IO_L13N_T1_MRCC_34 T1 Bank 34 I/O User defined
J2.55 DGND DGND - - G - Digital ground
J2.57 IO_L11P_T1_SRCC_34 FPGA.IO_L11P_T1_SRCC_34 K4 Bank 34 I/O User defined
J2.59 IO_L11N_T1_SRCC_34 FPGA.IO_L11N_T1_SRCC_34 K3 Bank 34 I/O User defined
J2.61 DGND DGND - - G - Digital ground
J2.63 IO_L10P_T1_34 FPGA.IO_L10P_T1_34 L2 Bank 34 I/O User defined
J2.65 IO_L10N_T1_34 FPGA.IO_L10N_T1_34 L1 Bank 34 I/O User defined
J2.67 IO_25_VRP_34 FPGA.IO_25_VRP_34 R8 Bank 34 I/O User defined Optional Internal Termination resistors for DCI
J2.69 IO_0_VRN_34 FPGA.IO_0_VRN_34 H8 Bank 34 I/O User defined Optional Internal Termination resistors for DCI
J2.71 DGND DGND - - G - Digital ground
J2.73 RFU - - - - - Reserved for future use. Must be left floating.
J2.75 RFU - - - - - Reserved for future use. Must be left floating.
J2.77 RFU - - - - - Reserved for future use. Must be left floating.
J2.79 RFU - - - - - Reserved for future use. Must be left floating.
J2.81 RFU - - - - - Reserved for future use. Must be left floating.
J2.83 ETH0_PHY_RST LAN.RESET_N 42 BANK 501 O 1.8V Internally connected to DGND via 10K resistor
J2.85 USB0_PHY_RST USB.RESETB 23 BANK 501 O 1.8V Internally connected to DGND via 10K resistor
J2.87 CAN_3STn LEVEL_SHIFTER.3ST# 6 BANK 34 I User defined TBD Internally connected to VDDIO_BANK34 via 10K resistor
J2.89 EXT_VMON2_V1 - - - - Reserved for future use. Must be left floating.
J2.91 EXT_VMON2_V2 - - - - Reserved for future use. Must be left floating.
J2.93 RTC_32KHZ RTC.32KHZ 1 3.3V O 3.3V
J2.95 RTC_RST RTC.~RST 4 3.3V I/O 3.3V
J2.97 XADC_VN_R FPGA.VN_0 L12 Bank 0 A
J2.99 XADC_VP_R FPGA.VP_0 M11 Bank 0 A
J2.101 RFU - - - - - Reserved for future use. Must be left floating.
J2.103 CONN_SPI_RSTn - - - - - Reserved for future use. Must be left floating.
J2.105 CAN_L CAN.CANL 6 - D -
J2.107 CAN_H CAN.CANH 7 - D -
J2.109 DGND DGND - - G - Digital ground
J2.111 RTC_INT/SQW RTC.RTC_INT/SQW 3 3.3V I/O 3.3V It can be left open if not used. When used, a proper pull-up resistor is required on the carrier board. For further details, please refer to the Maxim Integrated DS3232 datasheet.
J2.113 RTC_VBAT RTC.VBAT 6 - S - TBD
J2.115 VBAT CPU.VCCBATT_0 G14 - S - TBD
J2.117 DGND DGND - - G - Digital ground
J2.119 3.3VIN 3.3VIN - 3.3VIN S +3.3V SOM Power Supply
J2.121 3.3VIN 3.3VIN - 3.3VIN S +3.3V SOM Power Supply
J2.123 3.3VIN 3.3VIN - 3.3VIN S +3.3V SOM Power Supply
J2.125 DGND DGND - - G - Digital ground
J2.127 3.3VIN 3.3VIN - 3.3VIN S +3.3V SOM Power Supply
J2.129 3.3VIN 3.3VIN - 3.3VIN S +3.3V SOM Power Supply
J2.131 3.3VIN 3.3VIN - 3.3VIN S +3.3V SOM Power Supply
J2.133 3.3VIN 3.3VIN - 3.3VIN S +3.3V SOM Power Supply
J2.135 3.3VIN 3.3VIN - 3.3VIN S +3.3V SOM Power Supply
J2.137 3.3VIN 3.3VIN - 3.3VIN S +3.3V SOM Power Supply
J2.139 DGND DGND - - G - Digital ground

J2 even pins (2 to 140)[edit | edit source]

Pin Pin Name Internal Connections Ball/pin # Supply Group Type Voltage Note
J2.2 DGND DGND - - G - Digital ground
J2.4 IO_L9P_T1_DQS_34 FPGA.IO_L9P_T1_DQS_34 J3 Bank 34 I/O User defined
J2.6 IO_L9N_T1_DQS_34 FPGA.IO_L9N_T1_DQS_34 K2 Bank 34 I/O User defined
J2.8 IO_L7P_T1_34 FPGA.IO_L7P_T1_34 J5 Bank 34 I/O User defined
J2.10 IO_L7N_T1_34 FPGA.IO_L7N_T1_34 K5 Bank 34 I/O User defined
J2.12 DGND DGND - - G - Digital ground
J2.14 IO_L5P_T0_34 FPGA.IO_L5P_T0_34 N8 Bank 34 I/O User defined
J2.16 IO_L5N_T0_34 FPGA.IO_L5N_T0_34 P8 Bank 34 I/O User defined
J2.18 IO_L4P_T0_34 FPGA.IO_L4P_T0_34 L6 Bank 34 I/O User defined
J2.20 IO_L4N_T0_34 FPGA.IO_L4N_T0_34 M6 Bank 34 I/O User defined
J2.22 DGND DGND - - G - Digital ground
J2.24 IO_L24P_T3_34 FPGA.IO_L24P_T3_34 P7 Bank 34 I/O User defined
J2.26 IO_L24N_T3_34 FPGA.IO_L24N_T3_34 R7 Bank 34 I/O User defined
J2.28 IO_L23P_T3_34 FPGA.IO_L23P_T3_34 R5 Bank 34 I/O User defined
J2.30 IO_L23N_T3_34 FPGA.IO_L23N_T3_34 R4 Bank 34 I/O User defined
J2.32 DGND DGND - - G - Digital ground
J2.34 IO_L20P_T3_34 FPGA.IO_L20P_T3_34 P6 Bank 34 I/O User defined
J2.36 IO_L20N_T3_34 FPGA.IO_L20N_T3_34 P5 Bank 34 I/O User defined
J2.38 IO_L1P_T0_34 FPGA.IO_L1P_T0_34 J8 Bank 34 I/O User defined
J2.40 IO_L1N_T0_34 FPGA.IO_L1N_T0_34 K8 Bank 34 I/O User defined
J2.42 DGND DGND - - G - Digital ground
J2.44 IO_L17P_T2_34 FPGA.IO_L17P_T2_34 R3 Bank 34 I/O User defined
J2.46 IO_L17N_T2_34 FPGA.IO_L17N_T2_34 R2 Bank 34 I/O User defined
J2.48 IO_L16P_T2_34 FPGA.IO_L16P_T2_34 N1 Bank 34 I/O User defined
J2.50 IO_L16N_T2_34 FPGA.IO_L16N_T2_34 P1 Bank 34 I/O User defined
J2.52 DGND DGND - - G - Digital ground
J2.54 IO_L14P_T2_SRCC_34 FPGA.IO_L14P_T2_SRCC_34 U2 Bank 34 I/O User defined
J2.56 IO_L14N_T2_SRCC_34 FPGA.IO_L14N_T2_SRCC_34 U1 Bank 34 I/O User defined
J2.58 DGND DGND - - G - Digital ground
J2.60 IO_L12P_T1_MRCC_34 FPGA.IO_L12P_T1_MRCC_34 L5 Bank 34 I/O User defined
J2.62 IO_L12N_T1_MRCC_34 FPGA.IO_L12N_T1_MRCC_34 L4 Bank 34 I/O User defined
J2.64 DGND DGND - - G - Digital ground
J2.66 VDDIO_BANK34 FPGA.VCCO_34 K6

H2 L3 N7 P4 R1||Bank 34||S||User defined||Bank34 I/O Power Supply

J2.68 VDDIO_BANK34 FPGA.VCCO_34 K6

H2 L3 N7 P4 R1||Bank 34||S||User defined||Bank34 I/O Power Supply

J2.70 VDDIO_BANK34 FPGA.VCCO_34 K6

H2 L3 N7 P4 R1||Bank 34||S||User defined||Bank34 I/O Power Supply

J2.72 VDDIO_BANK34 FPGA.VCCO_34 K6

H2 L3 N7 P4 R1||Bank 34||S||User defined||Bank34 I/O Power Supply

J2.74 RFU - - - - - Reserved for future use. Must be left floating.
J2.76 RFU - - - - - Reserved for future use. Must be left floating.
J2.78 RFU - - - - - Reserved for future use. Must be left floating.
J2.80 JTAG_TDO CPU.TDO_0 G9 BANK 0 O 3.3V
J2.82 JTAG_TDI CPU.TDI_0 H9 BANK 0 I 3.3V
J2.84 JTAG_TMS CPU.TMS_0 H10 BANK 0 I 3.3V
J2.86 JTAG_TCK CPU.TCK_0 H11 BANK 0 I 3.3V
J2.88 DGND DGND - - G - Digital ground
J2.90 FPGA_INIT_B FPGA.INIT_B_0 T8 BANK 0 I/O 3.3V
J2.92 FPGA_PROGRAM_B FPGA.PROGRAM_B_0 V10 BANK 0 I 3.3V
J2.94 FPGA_DONE FPGA.DONE0 T10 BANK 0 I/O 3.3V
J2.96 WD_SET2 WDT.SET2 6 3.3V I 3.3V
J2.98 WD_SET1 WDT.SET1 5 3.3V I 3.3V
J2.100 WD_SET0 WDT.SET0 4 3.3V I 3.3V
J2.102 DGND DGND - - G - Digital ground
J2.104 PS_MIO50_501 CPU.PS_MIO50_501

USBOTG.RESETB||D10 22||BANK 501||I/O||1.8V||For further details, please refer to Reset_scheme_(BoraXpress)#PS_MIO50_501

J2.106 PS_MIO51_501 CPU.PS_MIO51_501

ETHPHY1GB.RESET_N||C13 42||BANK 501||I/O||1.8V||For further details, please refer to Reset_scheme_(BoraXpress)#PS_MIO51_501

J2.108 SOM_PGOOD SOM_PGOOD_LOGIC.OUT n.a. 3.3V O 3.3V Internally connected to DGND via 100K resistor
J2.110 CB_PWR_GOOD 1.0VREGULATOR.ENABLE

SOM_PGOOD_LOGIC.IN||n.a.||3.3VIN||I||3.3V||Internally connected to 3.3VIN via 10K resistor

J2.112 SYS_RSTn CPU.PS_SRST_B_501 C14 BANK 501 I 1.8V Internally connected to 1.8V via 20K resistor
J2.114 PORSTn CPU.PS_POR_B_500

SV1.~RST SV2.~RST WD.~WDO NOR.~RESET/RFU||B18 5 5 7 A4||BANK 500||I/O||3.3V||Internally connected to 3.3VIN via 2.2K resistor For further details, please refer to Reset_scheme_(BoraXpress)#PORSTn

J2.116 MRSTn SV1.~MR 6 3.3VIN I 3.3V Internally connected to 3.3VIN via 2.2K resistor

For further details, please refer to Reset_scheme_(BoraXpress)#MRSTn

J2.118 DGND DGND - - G - Digital ground
J2.120 3.3VIN 3.3VIN - 3.3VIN S +3.3V SOM Power Supply
J2.122 3.3VIN 3.3VIN - 3.3VIN S +3.3V SOM Power Supply
J2.124 DGND DGND - - G - Digital ground
J2.126 3.3VIN 3.3VIN - 3.3VIN S +3.3V SOM Power Supply
J2.128 3.3VIN 3.3VIN - 3.3VIN S +3.3V SOM Power Supply
J2.130 3.3VIN 3.3VIN - 3.3VIN S +3.3V SOM Power Supply
J2.132 3.3VIN 3.3VIN - 3.3VIN S +3.3V SOM Power Supply
J2.134 3.3VIN 3.3VIN - 3.3VIN S +3.3V SOM Power Supply
J2.136 3.3VIN 3.3VIN - 3.3VIN S +3.3V SOM Power Supply
J2.138 3.3VIN 3.3VIN - 3.3VIN S +3.3V SOM Power Supply
J2.140 DGND DGND - - G - Digital ground

J3 odd pins (1 to 139)[edit | edit source]

J3 even pins (2 to 140)[edit | edit source]

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