Bureaucrats, dave_user, Administrators
4,650
edits
Changes
→J1 odd pins (1 to 139)
| align="center" style="background:#f0f0f0;"|'''Note'''
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| J1.1||DGND||DGND||-||-||-G||-||
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| J1.3||IO_25_VRP_35||FPGA.IO_25_35/IO_25_VRP_35||H5||Bank 35||I/O||User defined||Optional on-board pull-down
| J1.17||IO_L19N_T3_VREF_35||FPGA.IO_L19N_T3_VREF_35||H3||Bank 35||I/O||User defined||
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| J1.19||DGND||DGND||-||-||-G||-||
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| J1.21||IO_L17P_T2_AD5P_35||FPGA.IO_L17P_T2_AD5P_35||E2||Bank 35||I/O||User defined||
| J1.27||IO_L15N_T2_DQS_AD12N_35||FPGA.IO_L15N_T2_DQS_AD12N_35||A1||||||||
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| J1.29||DGND||DGND||-||-||-G||-||
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| J1.31||IO_L13P_T2_MRCC_35||FPGA.IO_L13P_T2_MRCC_35||B4||||||||
| J1.33||IO_L13N_T2_MRCC_35||FPGA.IO_L13N_T2_MRCC_35||B3||||||||
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| J1.35||DGND||DGND||-||-||-G||-||
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| J1.37||IO_L11P_T1_SRCC_35||FPGA.IO_L11P_T1_SRCC_35||C6||||||||
| J1.47||IO_L7N_T1_AD2N_35||FPGA.IO_L7N_T1_AD2N_35||B8||||||||
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| J1.49||DGND||DGND||-||-||-G||-||
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| J1.51||IO_L5P_T0_AD9P_35||FPGA.IO_L5P_T0_AD9P_35||F5||||||||
| J1.57||IO_L3N_T0_DQS_AD1N_35||FPGA.IO_L3N_T0_DQS_AD1N_35||D8||||||||
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| J1.59||DGND||DGND||-||-||-G||-||
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| J1.61||IO_L1P_T0_AD0P_35||FPGA.IO_L1P_T0_AD0P_35||F7||||||||
| J1.63||IO_L1N_T0_AD0N_35||FPGA.IO_L1N_T0_AD0N_35||E7||||||||
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| J1.65||DGND||DGND||-||-||-G||-||
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| J1.67||VDDIO_BANK35||||||||S||||
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| J1.69||XADC_AGND||||||||G||||
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| J1.71||XADC_AGND||||||||G||||
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| J1.73||PS_MIO45_501||CPU.PS_MIO45_501||B14||Bank 501||I/O||1.8V||
| J1.81||PS_MIO41_501||CPU.PS_MIO41_501||C15||Bank 501||I/O||1.8V||
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| J1.83||DGND||DGND||-||-||-G||-||
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| J1.85||PS_MIO40_501||CPU.PS_MIO40_501||E9||Bank 501||I/O||1.8V||
| J1.93||ETH_LED2||LAN.LED2||15||-||||1.8V||10kOhm pull-up
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| J1.95||DGND||DGND||-||-||-G||-||
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| J1.97||ETH_TXRX1_M||LAN.TXRXM_B||6||||D||||
| J1.99||ETH_TXRX1_P||LAN.TXRXP_B||5||||D||||
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| J1.101||DGND||DGND||-||-||-G||-||
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| J1.103||ETH_TXRX0_M||LAN.ETH_TXRX0_M||3||||D||||
| J1.115||OTG_ID||USB.ID||1||||||||
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| J1.117||DGND||DGND||-||-||-G||-||
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| J1.119||SPI0_DQ3/MODE0/NAND_IO0||CPU.PS_MIO5_500<br>NOR flash<br>NAND flash||CPU.A20||Bank 500||I/O||3.3V||This signal is pulled up or down by 20kOhm resistor to select proper bootstrap configuration.
| J1.125||SPI0_DQ0/MODE3/NAND_ALE||CPU.PS_MIO2_500<br>NOR flash<br>NAND flash||CPU.A21||Bank 500||I/O||3.3V||This signal is pulled up or down by 20kOhm resistor to select proper bootstrap configuration.
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| J1.127||DGND||DGND||-||-||-G||-||
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| J1.129||SPI0_SCLK/MODE4/NAND_IO1||CPU.PS_MIO6_500<br>NOR flash<br>NAND flash||CPU.A19||Bank 500||I/O||3.3V||This signal is pulled up or down by 20kOhm resistor to select proper bootstrap configuration.
| J1.137||MEM_WPn||NAND.WP<br>NOR.WP/IO2||NAND.19<br>NOR.C4||||||3.3V||
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| J1.139||DGND||DGND||-||-||-G||-||
|}
