Difference between revisions of "Pinout (BORAXpress)"

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(→‎J1 odd pins (1 to 139))
(→‎J1 odd pins (1 to 139))
Line 42: Line 42:
 
| align="center" style="background:#f0f0f0;"|'''Note'''
 
| align="center" style="background:#f0f0f0;"|'''Note'''
 
|-
 
|-
−
| J1.1||DGND||DGND||-||-||-||-||
+
| J1.1||DGND||DGND||-||-||G||-||
 
|-
 
|-
 
| J1.3||IO_25_VRP_35||FPGA.IO_25_35/IO_25_VRP_35||H5||Bank 35||I/O||User defined||Optional on-board pull-down
 
| J1.3||IO_25_VRP_35||FPGA.IO_25_35/IO_25_VRP_35||H5||Bank 35||I/O||User defined||Optional on-board pull-down
Line 60: Line 60:
 
| J1.17||IO_L19N_T3_VREF_35||FPGA.IO_L19N_T3_VREF_35||H3||Bank 35||I/O||User defined||
 
| J1.17||IO_L19N_T3_VREF_35||FPGA.IO_L19N_T3_VREF_35||H3||Bank 35||I/O||User defined||
 
|-
 
|-
−
| J1.19||DGND||DGND||-||-||-||-||
+
| J1.19||DGND||DGND||-||-||G||-||
 
|-
 
|-
 
| J1.21||IO_L17P_T2_AD5P_35||FPGA.IO_L17P_T2_AD5P_35||E2||Bank 35||I/O||User defined||
 
| J1.21||IO_L17P_T2_AD5P_35||FPGA.IO_L17P_T2_AD5P_35||E2||Bank 35||I/O||User defined||
Line 70: Line 70:
 
| J1.27||IO_L15N_T2_DQS_AD12N_35||FPGA.IO_L15N_T2_DQS_AD12N_35||A1||||||||
 
| J1.27||IO_L15N_T2_DQS_AD12N_35||FPGA.IO_L15N_T2_DQS_AD12N_35||A1||||||||
 
|-
 
|-
−
| J1.29||DGND||DGND||-||-||-||-||
+
| J1.29||DGND||DGND||-||-||G||-||
 
|-
 
|-
 
| J1.31||IO_L13P_T2_MRCC_35||FPGA.IO_L13P_T2_MRCC_35||B4||||||||
 
| J1.31||IO_L13P_T2_MRCC_35||FPGA.IO_L13P_T2_MRCC_35||B4||||||||
Line 76: Line 76:
 
| J1.33||IO_L13N_T2_MRCC_35||FPGA.IO_L13N_T2_MRCC_35||B3||||||||
 
| J1.33||IO_L13N_T2_MRCC_35||FPGA.IO_L13N_T2_MRCC_35||B3||||||||
 
|-
 
|-
−
| J1.35||DGND||DGND||-||-||-||-||
+
| J1.35||DGND||DGND||-||-||G||-||
 
|-
 
|-
 
| J1.37||IO_L11P_T1_SRCC_35||FPGA.IO_L11P_T1_SRCC_35||C6||||||||
 
| J1.37||IO_L11P_T1_SRCC_35||FPGA.IO_L11P_T1_SRCC_35||C6||||||||
Line 90: Line 90:
 
| J1.47||IO_L7N_T1_AD2N_35||FPGA.IO_L7N_T1_AD2N_35||B8||||||||
 
| J1.47||IO_L7N_T1_AD2N_35||FPGA.IO_L7N_T1_AD2N_35||B8||||||||
 
|-
 
|-
−
| J1.49||DGND||DGND||-||-||-||-||
+
| J1.49||DGND||DGND||-||-||G||-||
 
|-
 
|-
 
| J1.51||IO_L5P_T0_AD9P_35||FPGA.IO_L5P_T0_AD9P_35||F5||||||||
 
| J1.51||IO_L5P_T0_AD9P_35||FPGA.IO_L5P_T0_AD9P_35||F5||||||||
Line 100: Line 100:
 
| J1.57||IO_L3N_T0_DQS_AD1N_35||FPGA.IO_L3N_T0_DQS_AD1N_35||D8||||||||
 
| J1.57||IO_L3N_T0_DQS_AD1N_35||FPGA.IO_L3N_T0_DQS_AD1N_35||D8||||||||
 
|-
 
|-
−
| J1.59||DGND||DGND||-||-||-||-||
+
| J1.59||DGND||DGND||-||-||G||-||
 
|-
 
|-
 
| J1.61||IO_L1P_T0_AD0P_35||FPGA.IO_L1P_T0_AD0P_35||F7||||||||
 
| J1.61||IO_L1P_T0_AD0P_35||FPGA.IO_L1P_T0_AD0P_35||F7||||||||
Line 106: Line 106:
 
| J1.63||IO_L1N_T0_AD0N_35||FPGA.IO_L1N_T0_AD0N_35||E7||||||||
 
| J1.63||IO_L1N_T0_AD0N_35||FPGA.IO_L1N_T0_AD0N_35||E7||||||||
 
|-
 
|-
−
| J1.65||DGND||DGND||-||-||-||-||
+
| J1.65||DGND||DGND||-||-||G||-||
 
|-
 
|-
 
| J1.67||VDDIO_BANK35||||||||S||||
 
| J1.67||VDDIO_BANK35||||||||S||||
 
|-
 
|-
−
| J1.69||XADC_AGND||||||||||||
+
| J1.69||XADC_AGND||||||||G||||
 
|-
 
|-
−
| J1.71||XADC_AGND||||||||||||
+
| J1.71||XADC_AGND||||||||G||||
 
|-
 
|-
 
| J1.73||PS_MIO45_501||CPU.PS_MIO45_501||B14||Bank 501||I/O||1.8V||
 
| J1.73||PS_MIO45_501||CPU.PS_MIO45_501||B14||Bank 501||I/O||1.8V||
Line 124: Line 124:
 
| J1.81||PS_MIO41_501||CPU.PS_MIO41_501||C15||Bank 501||I/O||1.8V||
 
| J1.81||PS_MIO41_501||CPU.PS_MIO41_501||C15||Bank 501||I/O||1.8V||
 
|-
 
|-
−
| J1.83||DGND||DGND||-||-||-||-||
+
| J1.83||DGND||DGND||-||-||G||-||
 
|-
 
|-
 
| J1.85||PS_MIO40_501||CPU.PS_MIO40_501||E9||Bank 501||I/O||1.8V||
 
| J1.85||PS_MIO40_501||CPU.PS_MIO40_501||E9||Bank 501||I/O||1.8V||
Line 136: Line 136:
 
| J1.93||ETH_LED2||LAN.LED2||15||-||||1.8V||10kOhm pull-up
 
| J1.93||ETH_LED2||LAN.LED2||15||-||||1.8V||10kOhm pull-up
 
|-
 
|-
−
| J1.95||DGND||DGND||-||-||-||-||
+
| J1.95||DGND||DGND||-||-||G||-||
 
|-
 
|-
 
| J1.97||ETH_TXRX1_M||LAN.TXRXM_B||6||||D||||
 
| J1.97||ETH_TXRX1_M||LAN.TXRXM_B||6||||D||||
Line 142: Line 142:
 
| J1.99||ETH_TXRX1_P||LAN.TXRXP_B||5||||D||||
 
| J1.99||ETH_TXRX1_P||LAN.TXRXP_B||5||||D||||
 
|-
 
|-
−
| J1.101||DGND||DGND||-||-||-||-||
+
| J1.101||DGND||DGND||-||-||G||-||
 
|-
 
|-
 
| J1.103||ETH_TXRX0_M||LAN.ETH_TXRX0_M||3||||D||||
 
| J1.103||ETH_TXRX0_M||LAN.ETH_TXRX0_M||3||||D||||
Line 158: Line 158:
 
| J1.115||OTG_ID||USB.ID||1||||||||
 
| J1.115||OTG_ID||USB.ID||1||||||||
 
|-
 
|-
−
| J1.117||DGND||DGND||-||-||-||-||
+
| J1.117||DGND||DGND||-||-||G||-||
 
|-
 
|-
 
| J1.119||SPI0_DQ3/MODE0/NAND_IO0||CPU.PS_MIO5_500<br>NOR flash<br>NAND flash||CPU.A20||Bank 500||I/O||3.3V||This signal is pulled up or down by 20kOhm resistor to select proper bootstrap configuration.
 
| J1.119||SPI0_DQ3/MODE0/NAND_IO0||CPU.PS_MIO5_500<br>NOR flash<br>NAND flash||CPU.A20||Bank 500||I/O||3.3V||This signal is pulled up or down by 20kOhm resistor to select proper bootstrap configuration.
Line 168: Line 168:
 
| J1.125||SPI0_DQ0/MODE3/NAND_ALE||CPU.PS_MIO2_500<br>NOR flash<br>NAND flash||CPU.A21||Bank 500||I/O||3.3V||This signal is pulled up or down by 20kOhm resistor to select proper bootstrap configuration.
 
| J1.125||SPI0_DQ0/MODE3/NAND_ALE||CPU.PS_MIO2_500<br>NOR flash<br>NAND flash||CPU.A21||Bank 500||I/O||3.3V||This signal is pulled up or down by 20kOhm resistor to select proper bootstrap configuration.
 
|-
 
|-
−
| J1.127||DGND||DGND||-||-||-||-||
+
| J1.127||DGND||DGND||-||-||G||-||
 
|-
 
|-
 
| J1.129||SPI0_SCLK/MODE4/NAND_IO1||CPU.PS_MIO6_500<br>NOR flash<br>NAND flash||CPU.A19||Bank 500||I/O||3.3V||This signal is pulled up or down by 20kOhm resistor to select proper bootstrap configuration.
 
| J1.129||SPI0_SCLK/MODE4/NAND_IO1||CPU.PS_MIO6_500<br>NOR flash<br>NAND flash||CPU.A19||Bank 500||I/O||3.3V||This signal is pulled up or down by 20kOhm resistor to select proper bootstrap configuration.
Line 180: Line 180:
 
| J1.137||MEM_WPn||NAND.WP<br>NOR.WP/IO2||NAND.19<br>NOR.C4||||||3.3V||
 
| J1.137||MEM_WPn||NAND.WP<br>NOR.WP/IO2||NAND.19<br>NOR.C4||||||3.3V||
 
|-
 
|-
−
| J1.139||DGND||DGND||-||-||-||-||
+
| J1.139||DGND||DGND||-||-||G||-||
 
|}
 
|}
  

Revision as of 08:50, 3 November 2015

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Info Box
BORA Xpress.png Applies to BORA Xpress

Introduction[edit | edit source]

This chapter contains the pinout description of the BORA Xpress module, grouped in six tables (two – odd and even pins – for each connector) that report the pin mapping of the three 140-pin BORA Xpress connectors. Each row in the pinout tables contains the following information:

  • Pin: reference to the connector pin
  • Pin Name: pin (signal) name on the BORA Xpress connectors
  • Internal connections: connections to the BORA Xpress components
    • CPU.<x> : pin connected to CPU (processing system) pad named <x>
    • FPGA.<x>: pin connected to FPGA (programmable logic) pad named <x>
    • CAN.<x> : pin connected to the CAN transceiver
    • LAN.<x> : pin connected to the LAN PHY
    • USB.<x> : pin connected to the USB transceiver
    • NAND.<x>: pin connected to the flash NAND
    • NOR.<x>: pin connected to the flash NOR
    • SV.<x>: pin connected to voltage supervisor
    • MTR: pin connected to voltage monitors
  • Ball/pin #: Component ball/pin number connected to signal
  • Supply Group: Power Supply Group
  • Type: pin type
    • I = Input
    • O = Output
    • D = Differential
    • Z = High impedance
    • S = Power supply voltage
    • G = Ground
    • A = Analog signal
  • Voltage: I/O voltage levels

J1 odd pins (1 to 139)[edit | edit source]

Pin Pin Name Internal Connections Ball/pin # Supply Group Type Voltage Note
J1.1 DGND DGND - - G -
J1.3 IO_25_VRP_35 FPGA.IO_25_35/IO_25_VRP_35 H5 Bank 35 I/O User defined Optional on-board pull-down
J1.5 IO_L23P_T3_35 FPGA.IO_L10P_T1_AD11P_35 F2 Bank 35 I/O User defined
J1.7 IO_L23N_T3_35 FPGA.IO_L23N_T3_35 F1 Bank 35 I/O User defined
J1.9 IO_L21P_T3_DQS_AD14P_35 FPGA.IO_L21P_T3_DQS_AD14P_35 E4 Bank 35 I/O User defined
J1.11 IO_L21N_T3_DQS_AD14N_35 FPGA.IO_L21N_T3_DQS_AD14N_35 E3 Bank 35 I/O User defined
J1.13 DGND DGND - - - -
J1.15 IO_L19P_T3_35 FPGA.IO_L19P_T3_35 H4 Bank 35 I/O User defined
J1.17 IO_L19N_T3_VREF_35 FPGA.IO_L19N_T3_VREF_35 H3 Bank 35 I/O User defined
J1.19 DGND DGND - - G -
J1.21 IO_L17P_T2_AD5P_35 FPGA.IO_L17P_T2_AD5P_35 E2 Bank 35 I/O User defined
J1.23 IO_L17N_T2_AD5N_35 FPGA.IO_L17N_T2_AD5N_35 D2
J1.25 IO_L15P_T2_DQS_AD12P_35 FPGA.IO_L15P_T2_DQS_AD12P_35 A2
J1.27 IO_L15N_T2_DQS_AD12N_35 FPGA.IO_L15N_T2_DQS_AD12N_35 A1
J1.29 DGND DGND - - G -
J1.31 IO_L13P_T2_MRCC_35 FPGA.IO_L13P_T2_MRCC_35 B4
J1.33 IO_L13N_T2_MRCC_35 FPGA.IO_L13N_T2_MRCC_35 B3
J1.35 DGND DGND - - G -
J1.37 IO_L11P_T1_SRCC_35 FPGA.IO_L11P_T1_SRCC_35 C6
J1.39 IO_L11N_T1_SRCC_35 FPGA.IO_L11N_T1_SRCC_35 C5
J1.41 IO_L9P_T1_DQS_AD3P_35 FPGA.IO_L9P_T1_DQS_AD3P_35 A7
J1.43 IO_L9N_T1_DQS_AD3N_35 FPGA.IO_L9N_T1_DQS_AD3N_35 A6
J1.45 IO_L7P_T1_AD2P_35 FPGA.IO_L7P_T1_AD2P_35 C8
J1.47 IO_L7N_T1_AD2N_35 FPGA.IO_L7N_T1_AD2N_35 B8
J1.49 DGND DGND - - G -
J1.51 IO_L5P_T0_AD9P_35 FPGA.IO_L5P_T0_AD9P_35 F5
J1.53 IO_L5N_T0_AD9N_35 FPGA.IO_L5N_T0_AD9N_35 E5
J1.55 IO_L3P_T0_DQS_AD1P_35 FPGA.IO_L3P_T0_DQS_AD1P_35 E8
J1.57 IO_L3N_T0_DQS_AD1N_35 FPGA.IO_L3N_T0_DQS_AD1N_35 D8
J1.59 DGND DGND - - G -
J1.61 IO_L1P_T0_AD0P_35 FPGA.IO_L1P_T0_AD0P_35 F7
J1.63 IO_L1N_T0_AD0N_35 FPGA.IO_L1N_T0_AD0N_35 E7
J1.65 DGND DGND - - G -
J1.67 VDDIO_BANK35 S
J1.69 XADC_AGND G
J1.71 XADC_AGND G
J1.73 PS_MIO45_501 CPU.PS_MIO45_501 B14 Bank 501 I/O 1.8V
J1.75 PS_MIO44_501 CPU.PS_MIO44_501 E10 Bank 501 I/O 1.8V
J1.77 PS_MIO43_501 CPU.PS_MIO43_501 B12 Bank 501 I/O 1.8V
J1.79 PS_MIO42_501 CPU.PS_MIO42_501 D15 Bank 501 I/O 1.8V
J1.81 PS_MIO41_501 CPU.PS_MIO41_501 C15 Bank 501 I/O 1.8V
J1.83 DGND DGND - - G -
J1.85 PS_MIO40_501 CPU.PS_MIO40_501 E9 Bank 501 I/O 1.8V
J1.87 ETH_MDIO CPU.PS_MIO53_501 C11 Bank 501 I/O 1.8V 1kOhm pull-up
J1.89 ETH_MDC CPU.PS_MIO51_501 D13 Bank 501 I/O 1.8V
J1.91 ETH_LED1 LAN.LED1/PME_N1 17 - 1.8V 10kOhm pull-up
J1.93 ETH_LED2 LAN.LED2 15 - 1.8V 10kOhm pull-up
J1.95 DGND DGND - - G -
J1.97 ETH_TXRX1_M LAN.TXRXM_B 6 D
J1.99 ETH_TXRX1_P LAN.TXRXP_B 5 D
J1.101 DGND DGND - - G -
J1.103 ETH_TXRX0_M LAN.ETH_TXRX0_M 3 D
J1.105 ETH_TXRX0_P LAN.ETH_TXRX0_P 2 D
J1.107 DVDDH LAN.DVDDH 16
34
40
J1.109 RFU - - - - - Reserved fo future use. Must be left floating.
J1.111 USBOTG_CPEN USB.CPEN 7 3.3V
J1.113 OTG_VBUS USB.OTG_VBUS 2
J1.115 OTG_ID USB.ID 1
J1.117 DGND DGND - - G -
J1.119 SPI0_DQ3/MODE0/NAND_IO0 CPU.PS_MIO5_500
NOR flash
NAND flash		 CPU.A20 Bank 500 I/O 3.3V This signal is pulled up or down by 20kOhm resistor to select proper bootstrap configuration.
J1.121 SPI0_DQ2/MODE2/NAND_IO2 CPU.PS_MIO4_500
NOR flash
NAND flash		 CPU.E19 Bank 500 I/O 3.3V This signal is pulled up or down by 20kOhm resistor to select proper bootstrap configuration.
J1.123 SPI0_DQ1/MODE1/NAND_WE CPU.PS_MIO3_500
NOR flash
NAND flash		 CPU.F17 Bank 500 I/O 3.3V This signal is pulled up or down by 20kOhm resistor to select proper bootstrap configuration.
J1.125 SPI0_DQ0/MODE3/NAND_ALE CPU.PS_MIO2_500
NOR flash
NAND flash		 CPU.A21 Bank 500 I/O 3.3V This signal is pulled up or down by 20kOhm resistor to select proper bootstrap configuration.
J1.127 DGND DGND - - G -
J1.129 SPI0_SCLK/MODE4/NAND_IO1 CPU.PS_MIO6_500
NOR flash
NAND flash		 CPU.A19 Bank 500 I/O 3.3V This signal is pulled up or down by 20kOhm resistor to select proper bootstrap configuration.
J1.131 NAND_BUSY CPU.PS_MIO14_500
NOR flash
NAND flash		 CPU.B17 Bank 500 I/O 3.3V 10kOhm pull-up
J1.133 PS_MIO15_500 CPU.PS_MIO15_500
WDT.WDI		 CPU.E17
WDT.1		 Bank 500 I/O 3.3V See also this page
J1.135 RFU - - - - - Reserved fo future use. Must be left floating.
J1.137 MEM_WPn NAND.WP
NOR.WP/IO2		 NAND.19
NOR.C4		 3.3V
J1.139 DGND DGND - - G -

J1 even pins (2 to 140)[edit | edit source]

J2 odd pins (1 to 139)[edit | edit source]

J2 even pins (2 to 140)[edit | edit source]

J3 odd pins (1 to 139)[edit | edit source]

J3 even pins (2 to 140)[edit | edit source]

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