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Pinout (BORAXpress)

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<section begin="Body" />=Introduction=Connectors and Pinout Table==
This chapter contains the pinout description of the BORA Xpress module, grouped in six tables (two – odd and even pins – for each connector) that report the pin mapping of the three 140-pin BORA Xpress connectors.
=== Connectors description ===
In the following table are described the interface connectors on [[BORA Xpress SOM| BORA Xpress]] SOM:
{| class="wikitable"
|-
!Connector name
!Connector Type
!Notes
!Carrier board counterpart
|-
|J1, J2, J3
|Hirose FX8C-140S-SV<br>3x140 pins 0.6mm pitch connectors
|
|Hirose FX8C-140P-SV''<x>''
where ''<x''> stays for:
* ''empty'' = 5 mm board-to-board height
* 1 = 6 mm board-to-board height
* 2 = 7 mm board-to-board height
* 4 = 9 mm board-to-board height
* 6 = 11 mm board-to-board height
|}
The dedicated carrier board must mount the mating connector and connect the desired peripheral interfaces according to BORA pinout specifications. See the images below for reference:
 
[[File:BORA_Xpress_BOTTOM.png|700px|thumb|BORA Xpress BOTTOM view - J1, J2, J3 connectors (pins 1-139, 2-140)|none]]
 
===Pinout table naming conventions ===
 
Each row in the pinout tables contains the following information:
* Pin: reference to the connector pin* Pin Name: pin (signal) name on the BORA Xpress connectors* Internal connections: connections to the BORA Xpress components** CPU.<x> : pin connected to CPU (processing system) pad named <x>** FPGA.<x>: pin connected to FPGA (programmable logic) pad named <x>** CAN.<x> : pin connected to the CAN transceiver** LAN.<x> : pin connected to the LAN PHY** USB.<x> : pin connected to the USB transceiver** NAND.<x>: pin connected to the flash NAND** NOR.<x>: pin connected to the flash NOR** SV.<x>: pin connected to voltage supervisor** MTR: pin connected to voltage monitors* {| class="wikitable" style="width:50%;"|-|'''Pin'''|reference to the connector pin|-|'''Pin Name''' | Pin (signal) name on the BORA Xpress connectors|-|'''Internal<br>connections''' | Connections to the BORA Xpress components|- |-|'''Ball/pin #: ''' | Component ball/pin number connected to signal|-|'''Voltage''' || I/O voltage levels* 1.8V* Supply Group: Power Supply Group3.3V* U.D. = User Defined|-|'''Type: pin ''' | Pin type** I = Input** O = Output** D = Differential** Z = High impedance** S = Power supply voltage** G = Ground** A = Analog signal* Voltage: IA/O voltage levelsG = Analog Ground|}
==SOM J1 odd ODD pins (1 to 139)declaration==
{| class="wikitable" {| {{table}}
| style="background:#f0f0f0;" align="center" |'''Pin'''
| J1.87||ETH_MDIO||CPU.PS_MIO53_501||C11||Bank 501||I/O||1.8V||1kOhm pull-up
|-
| J1.89||ETH_MDC||CPU.PS_MIO51_501PS_MIO52_501||D13||Bank 501||I/O||1.8V||
|-
| J1.91||ETH_LED1||LAN.LED1/PME_N1||17||-||||1.8V||10kOhm pull-up
| J1.105||ETH_TXRX0_P||LAN.ETH_TXRX0_P||2||||D||||
|-
| J1.107||DVDDHD.N.C||LAN.DVDDH-||16<br>34<br>40||||||1.8V||Do Not Connect (reserved for internal use)
|-
| J1.109||RFU||-||-||-||-||-||Reserved fo future use. Must be left floating.
| J1.121||SPI0_DQ2/MODE2/NAND_IO2||CPU.PS_MIO4_500<br>NOR flash<br>NAND flash||CPU.E19||Bank 500||I/O||3.3V||This signal is pulled up or down by 20kOhm resistor to select proper bootstrap configuration.<br><br>Default configuration: pull-down (BOOT_MODE[2]=0)
|-
| J1.123||SPI0_DQ1/MODE1/NAND_WENAND_WE_B||CPU.PS_MIO3_500<br>NOR flash<br>NAND flash||CPU.F17||Bank 500||I/O||3.3V||This signal is pulled up or down by 20kOhm resistor to select proper bootstrap configuration.<br><br>Default configuration: pull-down (BOOT_MODE[1]=0)
|-
| J1.125||SPI0_DQ0/MODE3/NAND_ALE||CPU.PS_MIO2_500<br>NOR flash<br>NAND flash||CPU.A21||Bank 500||I/O||3.3V||This signal is pulled up or down by 20kOhm resistor to select proper bootstrap configuration.<br><br>Default configuration: pull-down (BOOT_MODE[3]=0)
| J1.131||NAND_BUSY||CPU.PS_MIO14_500<br>NOR flash<br>NAND flash||CPU.B17||Bank 500||I/O||3.3V||10kOhm pull-up
|-
| J1.133||PS_MIO15_500||CPU.PS_MIO15_500<br>WDT.WDI||CPU.E17<br>WDT.1||Bank 500||I/O||3.3V||See also [[Reset scheme (BORAXpress)BORA_Xpress_SOM/BORA_Xpress_Hardware/Power_and_Reset/Reset_scheme_and_control_signals|this page]]
|-
| J1.135||RFU||-||-||-||-||-||Reserved fo future use. Must be left floating.
|}
==SOM J1 even EVEN pins (2 to 140)declaration ==
{| class="wikitable" {| {{table}}
| style="background:#f0f0f0;" align="center" |'''Pin'''
| J1.134||NAND_IO7||CPU.PS_MIO12_500<br>NAND flash||CPU.C18||Bank 500||I/O||3.3V||
|-
| J1.136||NAND_RD_BNAND_RE_B/VCFG1||CPU.PS_MIO8_500<br>NAND flash||CPU.E18||Bank 500||I/O||3.3V||This signal is pulled up or down by 20kOhm resistor to select proper bootstrap configuration.<br><br>Default configuration: pull-up (VMODE[1]=1)
|-
| J1.138||NAND_CLE/VCFG0||CPU.PS_MIO7_500<br>NAND flash||CPU.D18||Bank 500||I/O||3.3V||This signal is pulled up or down by 20kOhm resistor to select proper bootstrap configuration.<br><br>Default configuration: pull-down (VMODE[0]=0)
|-
| J1.140||DGND||DGND||-||-||-||G||Digital ground
|}
==SOM J2 odd ODD pins (1 to 139)declaration ==
{| class="wikitable" {| {{table}}
| style="background:#f0f0f0;" align="center" |'''Pin'''
|}
==SOM J2 even EVEN pins (2 to 140)declaration==
{| class="wikitable" {| {{table}}
| style="background:#f0f0f0;" align="center" |'''Pin'''
| J2.88||DGND||DGND||-||-||G||-||Digital ground
|-
| J2.90||FPGA_INIT_B||FPGA.INIT_B_0||T8||BANK 0||I/O||3.3V||Place external 4.7 kΩ (or stronger) pull-up resistor to BOARD_PGOOD driven +3.3V supplyFor more further details , please refer to Table 2-4 on [http://www.xilinx.com/support[BORA_Xpress_SOM/documentationBORA_Xpress_Hardware/user_guidesPower_and_Reset/ug470_7Series_Config.pdf 7 Series FPGAs ConfigurationPL_initialization_signals | PL initialization signals]]
|-
| J2.92||FPGA_PROGRAM_B||FPGA.PROGRAM_B_0||V10||BANK 0||I||3.3V||Place external 4.7 kΩ (or stronger) pull-up resistor to BOARD_PGOOD driven +3.3V supplyFor more further details , please refer to Table 2-4 on [http://www.xilinx.com/support[BORA_Xpress_SOM/documentationBORA_Xpress_Hardware/user_guidesPower_and_Reset/ug470_7Series_Config.pdf 7 Series FPGAs ConfigurationPL_initialization_signals | PL initialization signals]]
(10 kΩ pull-up resistor is already mounted on BORAX module)
|-
| J2.94||FPGA_DONE||FPGA.DONE0||T10||BANK 0||I/O||3.3V||Place external 300Ω pull-up resistor to BOARD_PGOOD driven +3.3V supplyFor more further details , please refer to Table 2-4 on [http://www.xilinx.com/support[BORA_Xpress_SOM/documentationBORA_Xpress_Hardware/user_guidesPower_and_Reset/ug470_7Series_Config.pdf 7 Series FPGAs ConfigurationPL_initialization_signals | PL initialization signals]]
|-
| J2.96||WD_SET2||WDT.SET2||6||3.3V||I||3.3V||
| J2.102||DGND||DGND||-||-||G||-||Digital ground
|-
| J2.104||PS_MIO50_501||CPU.PS_MIO50_501<br>USBOTG.RESETB||D10<br>22||BANK 501||I/O||1.8V||For further details, please refer to [[Reset_scheme_(BORAXpress) BORA_Xpress_SOM/BORA_Xpress_Hardware/Power_and_Reset/Reset_scheme_and_control_signals#PS_MIO50_501_.28J2.104.29 | Reset_scheme_(BoraXpress)Resetscheme#PS_MIO50_501]]
|-
| J2.106||PS_MIO51_501||CPU.PS_MIO51_501<br>ETHPHY1GB.RESET_N||C13<br>42||BANK 501||I/O||1.8V||For further details, please refer to [[Reset_scheme_(BORAXpress) BORA_Xpress_SOM/BORA_Xpress_Hardware/Power_and_Reset/Reset_scheme_and_control_signals#PS_MIO51_501_.28J2.106.29 | Reset_scheme_(BoraXpress)Reset scheme#PS_MIO51_501]]
|-
| J2.108||SOM_PGOOD||SOM_PGOOD_LOGIC.OUT||n.a.||3.3V||O||3.3V||Internally connected to DGND via 100K resistor
| J2.112||SYS_RSTn||CPU.PS_SRST_B_501 ||C14||BANK 501||I||1.8V||Internally connected to 1.8V via 20K resistor
|-
| J2.114||PORSTn||CPU.PS_POR_B_500<br>WD.~WDO<br>NOR.~RESET/RFU||B18<br>7<br>A4||BANK 500||I/O||3.3V||Internally connected to 3.3VIN via 2.2K resistor.<br>For further details, please refer to [[Reset_scheme_(BORAXpress) BORA_Xpress_SOM/BORA_Xpress_Hardware/Power_and_Reset/Reset_scheme_and_control_signals#PORSTn_.28J2.114.29 | Reset_scheme_(BoraXpress)Reset_scheme#PORSTn]]
|-
| J2.116||MRSTn||Voltage monitor||6||3.3VIN||I||3.3V||Internally connected to 3.3VIN via 2.2K resistor
For further details, please refer to [[Reset_scheme_(BORAXpress) BORA_Xpress_SOM/BORA_Xpress_Hardware/Power_and_Reset/Reset_scheme_and_control_signals | Reset_scheme_(BoraXpress)Reset scheme]]
|-
| J2.118||DGND||DGND||-||-||G||-||Digital ground
|}
==SOM J3 odd ODD pins (1 to 139)declaration==
{| class="wikitable" {| {{table}}
| style="background:#f0f0f0;" align="center" |'''Pin'''
|}
==SOM J3 even EVEN pins (2 to 140)declaration==
{| class="wikitable" {| {{table}}
| style="background:#f0f0f0;" align="center" |'''Pin'''
U0007
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