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Pinout (BORAXpress)

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<section begin="Body" />=~~Introduction~~=Connectors and Pinout Table==

This chapter contains the pinout description of the BORA Xpress module, grouped in six tables (two – odd and even pins – for each connector) that report the pin mapping of the three 140-pin BORA Xpress connectors.

=== Connectors description ===

In the following table are described the interface connectors on [[BORA Xpress SOM| BORA Xpress]] SOM:

{| class="wikitable"

|-

!Connector name

!Connector Type

!Notes

!Carrier board counterpart

|-

|J1, J2, J3

|Hirose FX8C-140S-SV 3x140 pins 0.6mm pitch connectors

|

|Hirose FX8C-140P-SV''<x>''

where ''<x''> stays for:

* ''empty'' = 5 mm board-to-board height

* 1 = 6 mm board-to-board height

* 2 = 7 mm board-to-board height

* 4 = 9 mm board-to-board height

* 6 = 11 mm board-to-board height

|}

The dedicated carrier board must mount the mating connector and connect the desired peripheral interfaces according to BORA pinout specifications. See the images below for reference:

[[File:BORA_Xpress_BOTTOM.png|700px|thumb|BORA Xpress BOTTOM view - J1, J2, J3 connectors (pins 1-139, 2-140)|none]]

===Pinout table naming conventions ===

Each row in the pinout tables contains the following information:

* Pin: reference to the connector pin* Pin Name: pin (signal) name on the BORA Xpress connectors* Internal connections: connections to the BORA Xpress components** CPU.<x> : pin connected to CPU (processing system) pad named <x>** FPGA.<x>: pin connected to FPGA (programmable logic) pad named <x>** CAN.<x> : pin connected to the CAN transceiver** LAN.<x> : pin connected to the LAN PHY** USB.<x> : pin connected to the USB transceiver** NAND.<x>: pin connected to the flash NAND** NOR.<x>: pin connected to the flash NOR** SV.<x>: pin connected to voltage supervisor** MTR: pin connected to voltage monitors* {| class="wikitable" style="width:50%;"|-|'''Pin'''|reference to the connector pin|-|'''Pin Name''' | Pin (signal) name on the BORA Xpress connectors|-|'''Internal connections''' | Connections to the BORA Xpress components|- |-|'''Ball/pin #: ''' | Component ball/pin number connected to signal|-|'''Voltage''' || I/O voltage levels* 1.8V* ~~Supply Group: Power Supply Group~~3.3V* U.D. = User Defined|-|'''Type~~: pin~~ ''' | Pin type** I = Input** O = Output** D = Differential** Z = High impedance** S = Power supply voltage** G = Ground** A = Analog signal* ~~Voltage: I~~A/~~O voltage levels~~G = Analog Ground|}

==SOM J1 ~~odd~~ ODD pins (1 to 139)declaration==

{| class="wikitable" {| {{table}}

|-

| J1.1||DGND||DGND||-||-||G||-||Digital ground

| J1.21||IO_L17P_T2_AD5P_35||FPGA.IO_L17P_T2_AD5P_35||E2||Bank 35||I/O||User defined||

|-

| J1.23||IO_L17N_T2_AD5N_35||FPGA.IO_L17N_T2_AD5N_35||D2||Bank 35||I/O||User defined||

|-

| J1.25||IO_L15P_T2_DQS_AD12P_35||FPGA.IO_L15P_T2_DQS_AD12P_35||A2||Bank 35||I/O||User defined||

|-

| J1.27||IO_L15N_T2_DQS_AD12N_35||FPGA.IO_L15N_T2_DQS_AD12N_35||A1||Bank 35||I/O||User defined||

|-

| J1.29||DGND||DGND||-||-||G||-||Digital ground

|-

| J1.31||IO_L13P_T2_MRCC_35||FPGA.IO_L13P_T2_MRCC_35||B4||Bank 35||I/O||User defined||

|-

| J1.33||IO_L13N_T2_MRCC_35||FPGA.IO_L13N_T2_MRCC_35||B3||Bank 35||I/O||User defined||

|-

| J1.35||DGND||DGND||-||-||G||-||Digital ground

|-

| J1.37||IO_L11P_T1_SRCC_35||FPGA.IO_L11P_T1_SRCC_35||C6||Bank 35||I/O||User defined||

|-

| J1.39||IO_L11N_T1_SRCC_35||FPGA.IO_L11N_T1_SRCC_35||C5||Bank 35||I/O||User defined||

|-

| J1.41||IO_L9P_T1_DQS_AD3P_35||FPGA.IO_L9P_T1_DQS_AD3P_35||A7||Bank 35||I/O||User defined||

|-

| J1.43||IO_L9N_T1_DQS_AD3N_35||FPGA.IO_L9N_T1_DQS_AD3N_35||A6||Bank 35||I/O||User defined||

|-

| J1.45||IO_L7P_T1_AD2P_35||FPGA.IO_L7P_T1_AD2P_35||C8||Bank 35||I/O||User defined||

|-

| J1.47||IO_L7N_T1_AD2N_35||FPGA.IO_L7N_T1_AD2N_35||B8||Bank 35||I/O||User defined||

|-

| J1.49||DGND||DGND||-||-||G||-||Digital ground

|-

| J1.51||IO_L5P_T0_AD9P_35||FPGA.IO_L5P_T0_AD9P_35||F5||Bank 35||I/O||User defined||

|-

| J1.53||IO_L5N_T0_AD9N_35||FPGA.IO_L5N_T0_AD9N_35||E5||Bank 35||I/O||User defined||

|-

| J1.55||IO_L3P_T0_DQS_AD1P_35||FPGA.IO_L3P_T0_DQS_AD1P_35||E8||Bank 35||I/O||User defined||

|-

| J1.57||IO_L3N_T0_DQS_AD1N_35||FPGA.IO_L3N_T0_DQS_AD1N_35||D8||Bank 35||I/O||User defined||

|-

| J1.59||DGND||DGND||-||-||G||-||Digital ground

|-

| J1.61||IO_L1P_T0_AD0P_35||FPGA.IO_L1P_T0_AD0P_35||F7||Bank 35||I/O||User defined||

|-

| J1.63||IO_L1N_T0_AD0N_35||FPGA.IO_L1N_T0_AD0N_35||E7||Bank 35||I/O||User defined||

|-

| J1.65||DGND||DGND||-||-||G||-||Digital ground

| J1.87||ETH_MDIO||CPU.PS_MIO53_501||C11||Bank 501||I/O||1.8V||1kOhm pull-up

|-

| J1.89||ETH_MDC||CPU.~~PS_MIO51_501~~PS_MIO52_501||D13||Bank 501||I/O||1.8V||

|-

| J1.91||ETH_LED1||LAN.LED1/PME_N1||17||-||||1.8V||10kOhm pull-up

| J1.105||ETH_TXRX0_P||LAN.ETH_TXRX0_P||2||||D||||

|-

| J1.107||~~DVDDH~~D.N.C||~~LAN.DVDDH~~-||~~16 34 40~~||||||||Do Not Connect (reserved for internal use)

|-

| J1.109||RFU||-||-||-||-||-||Reserved fo future use. Must be left floating.

| J1.117||DGND||DGND||-||-||G||-||Digital ground

|-

| J1.119||SPI0_DQ3/MODE0/NAND_IO0||CPU.PS_MIO5_500 NOR flash NAND flash||CPU.A20||Bank 500||I/O||3.3V||This signal is pulled up or down by 20kOhm resistor to select proper bootstrap configuration. Default configuration: pull-up (BOOT_MODE[0]=1)

|-

| J1.121||SPI0_DQ2/MODE2/NAND_IO2||CPU.PS_MIO4_500 NOR flash NAND flash||CPU.E19||Bank 500||I/O||3.3V||This signal is pulled up or down by 20kOhm resistor to select proper bootstrap configuration. Default configuration: pull-down (BOOT_MODE[2]=0)

|-

| J1.123||SPI0_DQ1/MODE1/~~NAND_WE~~NAND_WE_B||CPU.PS_MIO3_500 NOR flash NAND flash||CPU.F17||Bank 500||I/O||3.3V||This signal is pulled up or down by 20kOhm resistor to select proper bootstrap configuration. Default configuration: pull-down (BOOT_MODE[1]=0)

|-

| J1.125||SPI0_DQ0/MODE3/NAND_ALE||CPU.PS_MIO2_500 NOR flash NAND flash||CPU.A21||Bank 500||I/O||3.3V||This signal is pulled up or down by 20kOhm resistor to select proper bootstrap configuration. Default configuration: pull-down (BOOT_MODE[3]=0)

|-

| J1.127||DGND||DGND||-||-||G||-||Digital ground

|-

| J1.129||SPI0_SCLK/MODE4/NAND_IO1||CPU.PS_MIO6_500 NOR flash NAND flash||CPU.A19||Bank 500||I/O||3.3V||This signal is pulled up or down by 20kOhm resistor to select proper bootstrap configuration. Default configuration: pull-down (BOOT_MODE[4]=0)

|-

| J1.131||NAND_BUSY||CPU.PS_MIO14_500 NOR flash NAND flash||CPU.B17||Bank 500||I/O||3.3V||10kOhm pull-up

|-

| J1.133||PS_MIO15_500||CPU.PS_MIO15_500 WDT.WDI||CPU.E17 WDT.1||Bank 500||I/O||3.3V||See also [[~~Reset scheme (BORAXpress)~~BORA_Xpress_SOM/BORA_Xpress_Hardware/Power_and_Reset/Reset_scheme_and_control_signals|this page]]

|-

| J1.135||RFU||-||-||-||-||-||Reserved fo future use. Must be left floating.

|}

==SOM J1 ~~even~~ EVEN pins (2 to 140)declaration ==

{| class="wikitable" {| {{table}}

|-

| J1.2||VDDIO_BANK35||||||||S||||

| J1.134||NAND_IO7||CPU.PS_MIO12_500 NAND flash||CPU.C18||Bank 500||I/O||3.3V||

|-

| J1.136||~~NAND_RD_B~~NAND_RE_B/VCFG1||CPU.PS_MIO8_500 NAND flash||CPU.E18||Bank 500||I/O||3.3V||This signal is pulled up or down by 20kOhm resistor to select proper bootstrap configuration. Default configuration: pull-up (VMODE[1]=1)

|-

| J1.138||NAND_CLE/VCFG0||CPU.PS_MIO7_500 NAND flash||CPU.D18||Bank 500||I/O||3.3V||This signal is pulled up or down by 20kOhm resistor to select proper bootstrap configuration. Default configuration: pull-down (VMODE[0]=0)

|-

| J1.140||DGND||DGND||-||-||-||G||Digital ground

|}

==SOM J2 ~~odd~~ ODD pins (1 to 139)declaration ==

{| class="wikitable" {| {{table}}

|-

| J2.1||DGND||DGND||-||-||G||-||Digital ground

|}

==SOM J2 ~~even~~ EVEN pins (2 to 140)declaration==

{| class="wikitable" {| {{table}}

|-

| J2.2||DGND||DGND||-||-||G||-||Digital ground

| J2.88||DGND||DGND||-||-||G||-||Digital ground

|-

| J2.90||FPGA_INIT_B||FPGA.INIT_B_0||T8||BANK 0||I/O||3.3V||For further details, please refer to [[BORA_Xpress_SOM/BORA_Xpress_Hardware/Power_and_Reset/PL_initialization_signals | PL initialization signals]]

|-

| J2.92||FPGA_PROGRAM_B||FPGA.PROGRAM_B_0||V10||BANK 0||I||3.3V||For further details, please refer to [[BORA_Xpress_SOM/BORA_Xpress_Hardware/Power_and_Reset/PL_initialization_signals | PL initialization signals]] (10 kΩ pull-up resistor is already mounted on BORAX module)

|-

| J2.94||FPGA_DONE||FPGA.DONE0||T10||BANK 0||I/O||3.3V||For further details, please refer to [[BORA_Xpress_SOM/BORA_Xpress_Hardware/Power_and_Reset/PL_initialization_signals | PL initialization signals]]

|-

| J2.96||WD_SET2||WDT.SET2||6||3.3V||I||3.3V||

| J2.102||DGND||DGND||-||-||G||-||Digital ground

|-

| J2.104||PS_MIO50_501||CPU.PS_MIO50_501 USBOTG.RESETB||D10 22||BANK 501||I/O||1.8V||For further details, please refer to [[~~Reset_scheme_(BoraXpress)~~BORA_Xpress_SOM/BORA_Xpress_Hardware/Power_and_Reset/Reset_scheme_and_control_signals#PS_MIO50_501_.28J2.104.29 | ~~Reset_scheme_(BoraXpress)~~Resetscheme#PS_MIO50_501]]

|-

| J2.106||PS_MIO51_501||CPU.PS_MIO51_501 ETHPHY1GB.RESET_N||C13 42||BANK 501||I/O||1.8V||For further details, please refer to [[~~Reset_scheme_(BoraXpress)~~BORA_Xpress_SOM/BORA_Xpress_Hardware/Power_and_Reset/Reset_scheme_and_control_signals#PS_MIO51_501_.28J2.106.29 | ~~Reset_scheme_(BoraXpress)~~Reset scheme#PS_MIO51_501 ]]

|-

| J2.108||SOM_PGOOD||SOM_PGOOD_LOGIC.OUT||n.a.||3.3V||O||3.3V||Internally connected to DGND via 100K resistor

| J2.112||SYS_RSTn||CPU.PS_SRST_B_501 ||C14||BANK 501||I||1.8V||Internally connected to 1.8V via 20K resistor

|-

| J2.114||PORSTn||CPU.PS_POR_B_500 WD.~WDO NOR.~RESET/RFU||B18 7 A4||BANK 500||I/O||3.3V||Internally connected to 3.3VIN via 2.2K resistor. For further details, please refer to [[~~Reset_scheme_(BoraXpress)~~BORA_Xpress_SOM/BORA_Xpress_Hardware/Power_and_Reset/Reset_scheme_and_control_signals#PORSTn_.28J2.114.29 | ~~Reset_scheme_(BoraXpress)~~Reset_scheme#PORSTn ]]

|-

| J2.116||MRSTn||Voltage monitor||6||3.3VIN||I||3.3V||Internally connected to 3.3VIN via 2.2K resistor

For further details, please refer to [[~~Reset_scheme_(BoraXpress)#MRSTn_.28J2.116.29~~ BORA_Xpress_SOM/BORA_Xpress_Hardware/Power_and_Reset/Reset_scheme_and_control_signals | ~~Reset_scheme_(BoraXpress)#MRSTn~~ Reset scheme]]

|-

| J2.118||DGND||DGND||-||-||G||-||Digital ground

|}

==SOM J3 ~~odd~~ ODD pins (1 to 139)declaration==

{| class="wikitable" {| {{table}}

|-

| J3.1||DGND||DGND||-||-||G||-||Digital ground

| J3.93||DGND||DGND||-||-||G||-||Digital ground

|-

| J3.95||VDDIO_BANK13||FPGA.VCCO_13||AA13 AB20 T18 Y16 W19 V12 U15||Bank 13||S||User defined||Bank13 I/O Power Supply

|-

| J3.97||VDDIO_BANK13||FPGA.VCCO_13||AA13 AB20 T18 Y16 W19 V12 U15||Bank 13||S||User defined||Bank13 I/O Power Supply

|-

| J3.99||VDDIO_BANK13||FPGA.VCCO_13||AA13 AB20 T18 Y16 W19 V12 U15||Bank 13||S||User defined||Bank13 I/O Power Supply

|-

| J3.101||DGND||DGND||-||-||G||-||Digital ground

|}

==SOM J3 ~~even~~ EVEN pins (2 to 140)declaration=={| class="wikitable" {| {{table}}| style="background:#f0f0f0;" align="center" |'''Pin'''| style="background:#f0f0f0;" align="center" |'''Pin Name'''| style="background:#f0f0f0;" align="center" |'''Internal Connections'''| style="background:#f0f0f0;" align="center" |'''Ball/pin #'''| style="background:#f0f0f0;" align="center" |'''Supply Group'''| style="background:#f0f0f0;" align="center" |'''Type'''| style="background:#f0f0f0;" align="center" |'''Voltage'''| style="background:#f0f0f0;" align="center" |'''Note'''|-| J3.2||DGND||DGND||-||-||G||-||Digital ground |-| J3.4||DGND||DGND||-||-||G||-||Digital ground |-| J3.6||MGTREFCLK1N||FPGA.MGTREFCLK1N_112||V5||MGTAVCC||D|||||-| J3.8||MGTREFCLK1P||FPGA.MGTREFCLK1P_112||U5||MGTAVCC||D|||||-| J3.10||DGND||DGND||-||-||G||-||Digital ground |-| J3.12||MGTxRXP0||FPGA.MGTXRXP0_112||AA7||MGTAVCC||D|||||-| J3.14||MGTxRXN0||FPGA.MGTXRXN0_112||AB7||MGTAVCC||D|||||-| J3.16||DGND||DGND||-||-||G||-||Digital ground |-| J3.18||MGTxRXP1||FPGA.MGTXRXP1_112||W8||MGTAVCC||D|||||-| J3.20||MGTxRXN1||FPGA.MGTXRXN1_112||Y8||MGTAVCC||D|||||-| J3.22||DGND||DGND||-||-||G||-||Digital ground |-| J3.24||MGTxRXP2||FPGA.MGTXRXP2_112||AA9||MGTAVCC||D|||||-| J3.26||MGTxRXN2||FPGA.MGTXRXN2_112||AB9||MGTAVCC||D|||||-| J3.28||DGND||DGND||-||-||G||-||Digital ground |-| J3.30||MGTxRXP3||FPGA.MGTXRXP3_112||W6||MGTAVCC||D|||||-| J3.32||MGTxRXN3||FPGA.MGTXRXN3_112||Y6||MGTAVCC||D|||||-| J3.34||DGND||DGND||-||-||G||-||Digital ground |-| J3.36||DGND||DGND||-||-||G||-||Digital ground |-| J3.38||IO_L24P_T3_13||FPGA.IO_L24P_T3_13||W17||Bank 13||I/O||User defined|||-| J3.40||IO_L24N_T3_13||FPGA.IO_L24N_T3_13||Y17||Bank 13||I/O||User defined|||-| J3.42||DGND||DGND||-||-||G||-||Digital ground |-| J3.44||IO_L10P_T1_13||FPGA.IO_L10P_T1_13||Y12||Bank 13||I/O||User defined|||-| J3.46||IO_L10N_T1_13||FPGA.IO_L10N_T1_13||Y13||Bank 13||I/O||User defined|||-| J3.48||DGND||DGND||-||-||G||-||Digital ground |-| J3.50||IO_L8P_T1_13||FPGA.IO_L8P_T1_13||AA12||Bank 13||I/O||User defined|||-| J3.52||IO_L8N_T1_13||FPGA.IO_L8N_T1_13||AB12||Bank 13||I/O||User defined|||-| J3.54||DGND||DGND||-||-||G||-||Digital ground |-| J3.56||IO_L6P_T0_13||FPGA.IO_L6P_T0_13||U13||Bank 13||I/O||User defined|||-| J3.58||IO_L6N_T0_VREF_13||FPGA.IO_L6N_T0_VREF_13||U14||Bank 13||I/O||User defined|||-| J3.60||DGND||DGND||-||-||G||-||Digital ground |-| J3.62||MON_MGTAVCC||||||||A||||By default this pin must not be connected. Optionally it can route power voltage generated by BoraXpress PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.|-| J3.64||MON_MGTAVCCAUX||||||||A||||By default this pin must not be connected. Optionally it can route power voltage generated by BoraXpress PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.|-| J3.66||MON_MGTAVTT||||||||A||||By default this pin must not be connected. Optionally it can route power voltage generated by BoraXpress PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.|-| J3.68||DGND||DGND||-||-||G||-||Digital ground |-| J3.70||RFU||-||-||-||-||-||Reserved for future use. Must be left floating.|-| J3.72||MON_VCCPLL||||||||A||||By default this pin must not be connected. Optionally it can route power voltage generated by BoraXpress PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.|-| J3.74||MON_XADC_VCC||||||||A||||By default this pin must not be connected. Optionally it can route power voltage generated by BoraXpress PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.|-| J3.76||MON_FPGA_VDDIO_BANK35||||||||A||||By default this pin must not be connected. Optionally it can route power voltage generated by BoraXpress PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.|-| J3.78||MON_FPGA_VDDIO_BANK34||||||||A||||By default this pin must not be connected. Optionally it can route power voltage generated by BoraXpress PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.|-| J3.80||MON_FPGA_VDDIO_BANK13||||||||A||||By default this pin must not be connected. Optionally it can route power voltage generated by BoraXpress PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.|-| J3.82||MON_1.8V_IO||||||||A||||By default this pin must not be connected. Optionally it can route power voltage generated by BoraXpress PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.|-| J3.84||MON_3.3V||||||||A||||By default this pin must not be connected. Optionally it can route power voltage generated by BoraXpress PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.|-| J3.86||MON_1V2_ETH||||||||A||||By default this pin must not be connected. Optionally it can route power voltage generated by BoraXpress PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.|-| J3.88||MON_VDDQ_1V5||||||||A||||By default this pin must not be connected. Optionally it can route power voltage generated by BoraXpress PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.|-| J3.90||MON_1.8V||||||||A||||By default this pin must not be connected. Optionally it can route power voltage generated by BoraXpress PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.|-| J3.92||MON_1.0V||||||||A||||By default this pin must not be connected. Optionally it can route power voltage generated by BoraXpress PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.|-| J3.94||DGND||DGND||-||-||G||-||Digital ground |-| J3.96||VDDIO_BANK13||FPGA.VCCO_13||AA13 AB20 T18 Y16 W19 V12 U15||Bank 13||S||User defined||Bank13 I/O Power Supply|-| J3.98||VDDIO_BANK13||FPGA.VCCO_13||AA13 AB20 T18 Y16 W19 V12 U15||Bank 13||S||User defined||Bank13 I/O Power Supply|-| J3.100||RFU||-||-||-||-||-||Reserved for future use. Must be left floating.|-| J3.102||DGND||DGND||-||-||G||-||Digital ground |-| J3.104||IO_L22P_T3_13||FPGA.IO_L22P_T3_13||U17||Bank 13||I/O||User defined|||-| J3.106||IO_L22N_T3_13||FPGA.IO_L22N_T3_13||U18||Bank 13||I/O||User defined|||-| J3.108||DGND||DGND||-||-||G||-||Digital ground |-| J3.110||IO_L20P_T3_13||FPGA.IO_L20P_T3_13||U19||Bank 13||I/O||User defined|||-| J3.112||IO_L20N_T3_13||FPGA.IO_L20N_T3_13||V19||Bank 13||I/O||User defined|||-| J3.114||DGND||DGND||-||-||G||-||Digital ground |-| J3.116||IO_L17P_T2_13||FPGA.IO_L17P_T2_13||AB16||Bank 13||I/O||User defined|||-| J3.118||IO_L17N_T2_13||FPGA.IO_L17N_T2_13||AB17||Bank 13||I/O||User defined|||-| J3.120||DGND||DGND||-||-||G||-||Digital ground |-| J3.122||IO_L15P_T2_DQS_13||FPGA.IO_L15P_T2_DQS_13||AB21||Bank 13||I/O||User defined|||-| J3.124||IO_L15N_T2_DQS_13||FPGA.IO_L15N_T2_DQS_13||AB22||Bank 13||I/O||User defined|||-| J3.126||DGND||DGND||-||-||G||-||Digital ground |-| J3.128||IO_L13P_T2_MRCC_13||FPGA.IO_L13P_T2_MRCC_13||Y18||Bank 13||I/O||User defined|||-| J3.130||IO_L13N_T2_MRCC_13||FPGA.IO_L13N_T2_MRCC_13||Y19||Bank 13||I/O||User defined|||-| J3.132||DGND||DGND||-||-||G||-||Digital ground |-| J3.134||IO_L11P_T1_SRCC_13||FPGA.IO_L11P_T1_SRCC_13||AA14||Bank 13||I/O||User defined|||-| J3.136||IO_L11N_T1_SRCC_13||FPGA.IO_L11N_T1_SRCC_13||AA15||Bank 13||I/O||User defined|||-| J3.138||DGND||DGND||-||-||G||-||Digital ground |-| J3.140||DGND||DGND||-||-||G||-||Digital ground |}

U0007

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