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==Connectors and Pinout Table==
This chapter contains the pinout description of the BORA Xpress module, grouped in six tables (two – odd and even pins – for each connector) that report the pin mapping of the three 140-pin BORA Xpress connectors.
=== Connectors description ===
In the following table are described the interface connectors on [[:Category:Bora BORA Xpress SOM| BoraBORA Xpress]] SOM:
{| class="wikitable"
|-
Each row in the pinout tables contains the following information:
* CPU.<x> : pin connected to CPU (processing system) pad named <x>
* FPGA.<x>: pin connected to FPGA (programmable logic) pad named <x>
* CAN.<x> : pin connected to the CAN transceiver
* LAN.<x> : pin connected to the LAN PHY
* USB.<x> : pin connected to the USB transceiver
* NAND.<x>: pin connected to the flash NAND
* NOR.<x>: pin connected to the flash NOR
* SV.<x>: pin connected to voltage supervisor
* MTR: pin connected to voltage monitors
{| class="wikitable" style="width:50%;"
|-
| Connections to the BORA Xpress components
|-
|-
|'''Ball/pin #'''
|-
|'''Type'''
| Pin type
* I = Input
| J1.87||ETH_MDIO||CPU.PS_MIO53_501||C11||Bank 501||I/O||1.8V||1kOhm pull-up
|-
| J1.89||ETH_MDC||CPU.PS_MIO51_501PS_MIO52_501||D13||Bank 501||I/O||1.8V||
|-
| J1.91||ETH_LED1||LAN.LED1/PME_N1||17||-||||1.8V||10kOhm pull-up
| J1.105||ETH_TXRX0_P||LAN.ETH_TXRX0_P||2||||D||||
|-
| J1.107||DVDDHD.N.C||LAN.DVDDH-||16<br>34<br>40||||||1.8V||Do Not Connect (reserved for internal use)
|-
| J1.109||RFU||-||-||-||-||-||Reserved fo future use. Must be left floating.
| J1.121||SPI0_DQ2/MODE2/NAND_IO2||CPU.PS_MIO4_500<br>NOR flash<br>NAND flash||CPU.E19||Bank 500||I/O||3.3V||This signal is pulled up or down by 20kOhm resistor to select proper bootstrap configuration.<br><br>Default configuration: pull-down (BOOT_MODE[2]=0)
|-
| J1.123||SPI0_DQ1/MODE1/NAND_WENAND_WE_B||CPU.PS_MIO3_500<br>NOR flash<br>NAND flash||CPU.F17||Bank 500||I/O||3.3V||This signal is pulled up or down by 20kOhm resistor to select proper bootstrap configuration.<br><br>Default configuration: pull-down (BOOT_MODE[1]=0)
|-
| J1.125||SPI0_DQ0/MODE3/NAND_ALE||CPU.PS_MIO2_500<br>NOR flash<br>NAND flash||CPU.A21||Bank 500||I/O||3.3V||This signal is pulled up or down by 20kOhm resistor to select proper bootstrap configuration.<br><br>Default configuration: pull-down (BOOT_MODE[3]=0)
| J1.131||NAND_BUSY||CPU.PS_MIO14_500<br>NOR flash<br>NAND flash||CPU.B17||Bank 500||I/O||3.3V||10kOhm pull-up
|-
| J1.133||PS_MIO15_500||CPU.PS_MIO15_500<br>WDT.WDI||CPU.E17<br>WDT.1||Bank 500||I/O||3.3V||See also [[Reset scheme (BORAXpress)BORA_Xpress_SOM/BORA_Xpress_Hardware/Power_and_Reset/Reset_scheme_and_control_signals|this page]]
|-
| J1.135||RFU||-||-||-||-||-||Reserved fo future use. Must be left floating.
| J1.134||NAND_IO7||CPU.PS_MIO12_500<br>NAND flash||CPU.C18||Bank 500||I/O||3.3V||
|-
| J1.136||NAND_RD_BNAND_RE_B/VCFG1||CPU.PS_MIO8_500<br>NAND flash||CPU.E18||Bank 500||I/O||3.3V||This signal is pulled up or down by 20kOhm resistor to select proper bootstrap configuration.<br><br>Default configuration: pull-up (VMODE[1]=1)
|-
| J1.138||NAND_CLE/VCFG0||CPU.PS_MIO7_500<br>NAND flash||CPU.D18||Bank 500||I/O||3.3V||This signal is pulled up or down by 20kOhm resistor to select proper bootstrap configuration.<br><br>Default configuration: pull-down (VMODE[0]=0)
| J2.88||DGND||DGND||-||-||G||-||Digital ground
|-
| J2.90||FPGA_INIT_B||FPGA.INIT_B_0||T8||BANK 0||I/O||3.3V||For further details, please refer to [[PL_initialization_signals_(BoraBORA_Xpress_SOM/BoraXBORA_Xpress_Hardware/BoraLite) Power_and_Reset/PL_initialization_signals | PL initialization signals]]
|-
| J2.92||FPGA_PROGRAM_B||FPGA.PROGRAM_B_0||V10||BANK 0||I||3.3V||For further details, please refer to [[PL_initialization_signals_(BoraBORA_Xpress_SOM/BoraXBORA_Xpress_Hardware/BoraLite) Power_and_Reset/PL_initialization_signals | PL initialization signals]]
(10 kΩ pull-up resistor is already mounted on BORAX module)
|-
| J2.94||FPGA_DONE||FPGA.DONE0||T10||BANK 0||I/O||3.3V||For further details, please refer to [[PL_initialization_signals_(BoraBORA_Xpress_SOM/BoraXBORA_Xpress_Hardware/BoraLite) Power_and_Reset/PL_initialization_signals | PL initialization signals]]
|-
| J2.96||WD_SET2||WDT.SET2||6||3.3V||I||3.3V||
| J2.102||DGND||DGND||-||-||G||-||Digital ground
|-
| J2.104||PS_MIO50_501||CPU.PS_MIO50_501<br>USBOTG.RESETB||D10<br>22||BANK 501||I/O||1.8V||For further details, please refer to [[Reset_scheme_(BORAXpress) BORA_Xpress_SOM/BORA_Xpress_Hardware/Power_and_Reset/Reset_scheme_and_control_signals#PS_MIO50_501_.28J2.104.29 | Reset_scheme_(BoraXpress)Resetscheme#PS_MIO50_501]]
|-
| J2.106||PS_MIO51_501||CPU.PS_MIO51_501<br>ETHPHY1GB.RESET_N||C13<br>42||BANK 501||I/O||1.8V||For further details, please refer to [[Reset_scheme_(BORAXpress) BORA_Xpress_SOM/BORA_Xpress_Hardware/Power_and_Reset/Reset_scheme_and_control_signals#PS_MIO51_501_.28J2.106.29 | Reset_scheme_(BoraXpress)Reset scheme#PS_MIO51_501]]
|-
| J2.108||SOM_PGOOD||SOM_PGOOD_LOGIC.OUT||n.a.||3.3V||O||3.3V||Internally connected to DGND via 100K resistor
| J2.112||SYS_RSTn||CPU.PS_SRST_B_501 ||C14||BANK 501||I||1.8V||Internally connected to 1.8V via 20K resistor
|-
| J2.114||PORSTn||CPU.PS_POR_B_500<br>WD.~WDO<br>NOR.~RESET/RFU||B18<br>7<br>A4||BANK 500||I/O||3.3V||Internally connected to 3.3VIN via 2.2K resistor.<br>For further details, please refer to [[Reset_scheme_(BORAXpress) BORA_Xpress_SOM/BORA_Xpress_Hardware/Power_and_Reset/Reset_scheme_and_control_signals#PORSTn_.28J2.114.29 | Reset_scheme_(BoraXpress)Reset_scheme#PORSTn]]
|-
| J2.116||MRSTn||Voltage monitor||6||3.3VIN||I||3.3V||Internally connected to 3.3VIN via 2.2K resistor
For further details, please refer to [[Reset_scheme_(BORAXpress) BORA_Xpress_SOM/BORA_Xpress_Hardware/Power_and_Reset/Reset_scheme_and_control_signals | Reset_scheme_(BoraXpress)Reset scheme]]
|-
| J2.118||DGND||DGND||-||-||G||-||Digital ground