Difference between revisions of "Pinout (AxelUltra)"

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m (→‎J2 even pins (2 to 140))
 
(10 intermediate revisions by the same user not shown)
Line 295: Line 295:
 
|J1.103
 
|J1.103
 
|SW2_1.8V/3.3V
 
|SW2_1.8V/3.3V
−
|???
+
|
 
|
 
|
 
|-
 
|-
Line 390: Line 390:
 
|}
 
|}
  
 +
==J1 even pins (2 to 140)==
  
−
==J1 even pins (2 to 140)==
+
{| class="wikitable" {| {{table}}
 +
| align="center" style="background:#f0f0f0;"|'''Pin'''
 +
| align="center" style="background:#f0f0f0;"|'''Pin Name'''
 +
| align="center" style="background:#f0f0f0;"|'''Internal Connections'''
 +
| align="center" style="background:#f0f0f0;"|'''Ball/pin #'''
 +
|-
 +
|J1.2
 +
|LVDS0_TX0_N
 +
|CPU.LVDS0_TX0_N
 +
|U2
 +
|-
 +
|J1.4
 +
|LVDS0_TX0_P
 +
|CPU.LVDS0_TX0_P
 +
|U1
 +
|-
 +
|J1.6
 +
|LVDS0_TX1_N
 +
|CPU.LVDS0_TX1_N
 +
|U4
 +
|-
 +
|J1.8
 +
|LVDS0_TX1_P
 +
|CPU.LVDS0_TX1_P
 +
|U3
 +
|-
 +
|J1.10
 +
|DGND
 +
|DGND
 +
|-
 +
|-
 +
|J1.12
 +
|LVDS0_TX2_N
 +
|CPU.LVDS0_TX2_N
 +
|V2
 +
|-
 +
|J1.14
 +
|LVDS0_TX2_P
 +
|CPU.LVDS0_TX2_P
 +
|V1
 +
|-
 +
|J1.16
 +
|LVDS0_TX3_N
 +
|CPU.LVDS0_TX3_N
 +
|W2
 +
|-
 +
|J1.18
 +
|LVDS0_TX3_P
 +
|CPU.LVDS0_TX3_P
 +
|W1
 +
|-
 +
|J1.20
 +
|LVDS0_CLK_N
 +
|CPU.LVDS0_CLK_N
 +
|V4
 +
|-
 +
|J1.22
 +
|LVDS0_CLK_P
 +
|CPU.LVDS0_CLK_P
 +
|V3
 +
|-
 +
|J1.24
 +
|DGND
 +
|DGND
 +
|-
 +
|-
 +
|J1.26
 +
|CSI0_MCLK
 +
|CPU.CSI0_MCLK
 +
|P4
 +
|-
 +
|J1.28
 +
|DGND
 +
|DGND
 +
|-
 +
|-
 +
|J1.30
 +
|CSI0_PIXCLK
 +
|CPU.CSI0_PIXCLK
 +
|P1
 +
|-
 +
|J1.32
 +
|CSI0_VSYNC
 +
|CPU.CSI0_VSYNC
 +
|N2
 +
|-
 +
|J1.34
 +
|CSI0_DATA_EN
 +
|CPU.CSI0_DATA_EN
 +
|P3
 +
|-
 +
|J1.36
 +
|CSI0_DAT4
 +
|CPU.CSI0_DAT4
 +
|N1
 +
|-
 +
|J1.38
 +
|CSI0_DAT5
 +
|CPU.CSI0_DAT5
 +
|P2
 +
|-
 +
|J1.40
 +
|CSI0_DAT6
 +
|CPU.CSI0_DAT6
 +
|N4
 +
|-
 +
|J1.42
 +
|CSI0_DAT7
 +
|CPU.CSI0_DAT7
 +
|N3
 +
|-
 +
|J1.44
 +
|CSI0_DAT8
 +
|CPU.CSI0_DAT8
 +
|N6
 +
|-
 +
|J1.46
 +
|CSI0_DAT9
 +
|CPU.CSI0_DAT9
 +
|N5
 +
|-
 +
|J1.48
 +
|CSI0_DAT10
 +
|CPU.CSI0_DAT10
 +
|M1
 +
|-
 +
|J1.50
 +
|DGND
 +
|DGND
 +
|-
 +
|-
 +
|J1.52
 +
|CSI0_DAT11
 +
|CPU.CSI0_DAT11
 +
|M3
 +
|-
 +
|J1.54
 +
|CSI0_DAT12
 +
|CPU.CSI0_DAT12
 +
|M2
 +
|-
 +
|J1.56
 +
|CSI0_DAT13
 +
|CPU.CSI0_DAT13
 +
|L1
 +
|-
 +
|J1.58
 +
|CSI0_DAT14
 +
|CPU.CSI0_DAT14
 +
|M4
 +
|-
 +
|J1.60
 +
|CSI0_DAT15
 +
|CPU.CSI0_DAT15
 +
|M5
 +
|-
 +
|J1.62
 +
|CSI0_DAT16
 +
|CPU.CSI0_DAT16
 +
|L4
 +
|-
 +
|J1.64
 +
|CSI0_DAT17
 +
|CPU.CSI0_DAT17
 +
|L3
 +
|-
 +
|J1.66
 +
|CSI0_DAT18
 +
|CPU.CSI0_DAT18
 +
|M6
 +
|-
 +
|J1.68
 +
|CSI0_DAT19
 +
|CPU.CSI0_DAT19
 +
|L6
 +
|-
 +
|J1.70
 +
|DGND
 +
|DGND
 +
|-
 +
|-
 +
|J1.72
 +
|GPIO_0
 +
|CPU.GPIO_0
 +
|T5
 +
|-
 +
|J1.74
 +
|GPIO_1
 +
|CPU.GPIO_1
 +
|T4
 +
|-
 +
|J1.76
 +
|GPIO_2
 +
|CPU.GPIO_2
 +
|T1
 +
|-
 +
|J1.78
 +
|GPIO_3/I2C3_SCL
 +
|CPU.GPIO_3
 +
|R7
 +
|-
 +
|J1.80
 +
|GPIO_4
 +
|CPU.GPIO_4
 +
|R6
 +
|-
 +
|J1.82
 +
|GPIO_5
 +
|CPU.GPIO_5
 +
|R4
 +
|-
 +
|J1.84
 +
|GPIO_6/I2C3_SDA
 +
|CPU.GPIO_6
 +
|T3
 +
|-
 +
|J1.86
 +
|GPIO_7//FLEXCAN1_H
 +
|CPU.GPIO_7
 +
|R3
 +
|-
 +
|J1.88
 +
|GPIO_8//FLEXCAN1_L
 +
|CPU.GPIO_8
 +
|R5
 +
|-
 +
|J1.90
 +
|DGND
 +
|DGND
 +
|-
 +
|-
 +
|J1.92
 +
|GPIO_9
 +
|CPU.GPIO_9
 +
|T2
 +
|-
 +
|J1.94
 +
|GPIO_16
 +
|CPU.GPIO_16
 +
|R2
 +
|-
 +
|J1.96
 +
|GPIO_17
 +
|CPU.GPIO_17
 +
|R1
 +
|-
 +
|J1.98
 +
|GPIO_18/PMIC_INT_B
 +
|CPU.GPIO_18
 +
|P6
 +
|-
 +
|J1.100
 +
|GPIO_19
 +
|CPU.GPIO_19
 +
|P5
 +
|-
 +
|J1.102
 +
|KEY_COL0/ECSPI1_SCLK
 +
|CPU.KEY_COL0
 +
|W5
 +
|-
 +
|J1.104
 +
|KEY_ROW0/ECSPI1_MOSI
 +
|CPU.KEY_ROW0
 +
|V6
 +
|-
 +
|J1.106
 +
|KEY_COL1/ECSPI1_MISO
 +
|CPU.KEY_COL1
 +
|U7
 +
|-
 +
|J1.108
 +
|KEY_ROW1/ECSPI1_SS0
 +
|CPU.KEY_ROW1
 +
|U6
 +
|-
 +
|J1.110
 +
|DGND
 +
|DGND
 +
|-
 +
|-
 +
|J1.112
 +
|KEY_COL2/ECSPI1_SS1
 +
|CPU.KEY_COL2
 +
|W6
 +
|-
 +
|J1.114
 +
|KEY_ROW2
 +
|CPU.KEY_ROW2
 +
|W4
 +
|-
 +
|J1.116
 +
|KEY_COL3/I2C2_SCL
 +
|CPU.KEY_COL3
 +
|U5
 +
|-
 +
|J1.118
 +
|KEY_ROW3/I2C2_SDA
 +
|CPU.KEY_ROW3
 +
|T7
 +
|-
 +
|J1.120
 +
|VGEN4_1V8_I
 +
|
 +
|
 +
|-
 +
|J1.122
 +
|NVCC_AXEL_I/O_3.3V/1.8V (BOARD_PGOOD)
 +
|
 +
|P7
 +
|-
 +
|J1.124
 +
|RTC_VBAT
 +
|RTC.VBAT
 +
|6
 +
|-
 +
|J1.126
 +
|PMIC_LICELL
 +
|PMIC.LICELL
 +
|42
 +
|-
 +
|J1.128
 +
|SD2_CMD
 +
|CPU.SD2_CMD
 +
|F19
 +
|-
 +
|J1.130
 +
|DGND
 +
|DGND
 +
|-
 +
|-
 +
|J1.132
 +
|SD2_CLK
 +
|CPU.SD2_CLK
 +
|C21
 +
|-
 +
|J1.134
 +
|SD2_DATA0
 +
|CPU.SD2_DATA0
 +
|A22
 +
|-
 +
|J1.136
 +
|SD2_DATA1
 +
|CPU.SD2_DATA1
 +
|E20
 +
|-
 +
|J1.138
 +
|SD2_DATA2
 +
|CPU.SD2_DATA2
 +
|A23
 +
|-
 +
|J1.140
 +
|SD2_DATA3
 +
|CPU.SD2_DATA3
 +
|B22
 +
|-
 +
|}
  
 
==J2 odd pins (1 to 139)==
 
==J2 odd pins (1 to 139)==
 +
 +
{| class="wikitable" {| {{table}}
 +
| align="center" style="background:#f0f0f0;"|'''Pin'''
 +
| align="center" style="background:#f0f0f0;"|'''Pin Name'''
 +
| align="center" style="background:#f0f0f0;"|'''Internal Connections'''
 +
| align="center" style="background:#f0f0f0;"|'''Ball/pin #'''
 +
|-
 +
|-
 +
|J2.1
 +
|DGND
 +
|DGND
 +
|-
 +
|-
 +
|J2.3
 +
|EIM_DA0
 +
|CPU.EIM_DA0
 +
|L20
 +
|-
 +
|J2.5
 +
|EIM_DA1
 +
|CPU.EIM_DA1
 +
|J25
 +
|-
 +
|J2.7
 +
|EIM_DA2
 +
|CPU.EIM_DA2
 +
|L21
 +
|-
 +
|J2.9
 +
|EIM_DA3
 +
|CPU.EIM_DA3
 +
|K24
 +
|-
 +
|J2.11
 +
|EIM_DA4
 +
|CPU.EIM_DA4
 +
|L22
 +
|-
 +
|J2.13
 +
|EIM_DA5
 +
|CPU.EIM_DA5
 +
|L23
 +
|-
 +
|J2.15
 +
|EIM_DA6
 +
|CPU.EIM_DA6
 +
|K25
 +
|-
 +
|J2.17
 +
|EIM_DA7
 +
|CPU.EIM_DA7
 +
|L25
 +
|-
 +
|J2.19
 +
|EIM_DA8
 +
|CPU.EIM_DA8
 +
|L24
 +
|-
 +
|J2.21
 +
|DGND
 +
|DGND
 +
|-
 +
|-
 +
|J2.23
 +
|EIM_DA9
 +
|CPU.EIM_DA9
 +
|M21
 +
|-
 +
|J2.25
 +
|EIM_DA10
 +
|CPU.EIM_DA10
 +
|M22
 +
|-
 +
|J2.27
 +
|EIM_DA11
 +
|CPU.EIM_DA11
 +
|M20
 +
|-
 +
|J2.29
 +
|EIM_DA12
 +
|CPU.EIM_DA12
 +
|M24
 +
|-
 +
|J2.31
 +
|EIM_DA13
 +
|CPU.EIM_DA13
 +
|M23
 +
|-
 +
|J2.33
 +
|EIM_DA14
 +
|CPU.EIM_DA14
 +
|N23
 +
|-
 +
|J2.35
 +
|EIM_DA15
 +
|CPU.EIM_DA15
 +
|N24
 +
|-
 +
|J2.37
 +
|EIM_D16
 +
|CPU.EIM_D16
 +
|C25
 +
|-
 +
|J2.39
 +
|EIM_D17
 +
|CPU.EIM_D17
 +
|F21
 +
|-
 +
|J2.41
 +
|DGND
 +
|DGND
 +
|-
 +
|-
 +
|J2.43
 +
|EIM_D18
 +
|CPU.EIM_D18
 +
|D24
 +
|-
 +
|J2.45
 +
|EIM_D19
 +
|CPU.EIM_D19
 +
|G21
 +
|-
 +
|J2.47
 +
|EIM_D20
 +
|CPU.EIM_D20
 +
|G20
 +
|-
 +
|J2.49
 +
|EIM_D21
 +
|CPU.EIM_D21
 +
|H20
 +
|-
 +
|J2.51
 +
|EIM_D22
 +
|CPU.EIM_D22
 +
|E23
 +
|-
 +
|J2.53
 +
|EIM_D23
 +
|CPU.EIM_D23
 +
|D25
 +
|-
 +
|J2.55
 +
|EIM_D24
 +
|CPU.EIM_D24
 +
|F22
 +
|-
 +
|J2.57
 +
|EIM_D25
 +
|CPU.EIM_D25
 +
|G22
 +
|-
 +
|J2.59
 +
|EIM_D26
 +
|CPU.EIM_D26
 +
|E24
 +
|-
 +
|J2.61
 +
|DGND
 +
|DGND
 +
|-
 +
|-
 +
|J2.63
 +
|EIM_D27
 +
|CPU.EIM_D27
 +
|E25
 +
|-
 +
|J2.65
 +
|EIM_D28
 +
|CPU.EIM_D28
 +
|G23
 +
|-
 +
|J2.67
 +
|EIM_D29
 +
|CPU.EIM_D29
 +
|J19
 +
|-
 +
|J2.69
 +
|EIM_D30
 +
|CPU.EIM_D30
 +
|J20
 +
|-
 +
|J2.71
 +
|EIM_D31
 +
|CPU.EIM_D31
 +
|H21
 +
|-
 +
|J2.73
 +
|EIM_A16
 +
|CPU.EIM_A16
 +
|H25
 +
|-
 +
|J2.75
 +
|EIM_A17
 +
|CPU.EIM_A17
 +
|G24
 +
|-
 +
|J2.77
 +
|EIM_A18
 +
|CPU.EIM_A18
 +
|J22
 +
|-
 +
|J2.79
 +
|EIM_A19
 +
|CPU.EIM_A19
 +
|G25
 +
|-
 +
|J2.81
 +
|DGND
 +
|DGND
 +
|-
 +
|-
 +
|J2.83
 +
|EIM_A20
 +
|CPU.EIM_A20
 +
|H22
 +
|-
 +
|J2.85
 +
|EIM_A21
 +
|CPU.EIM_A21
 +
|H23
 +
|-
 +
|J2.87
 +
|EIM_A22
 +
|CPU.EIM_A22
 +
|F24
 +
|-
 +
|J2.89
 +
|EIM_A23
 +
|CPU.EIM_A23
 +
|J21
 +
|-
 +
|J2.91
 +
|EIM_A24
 +
|CPU.EIM_A24
 +
|F25
 +
|-
 +
|J2.93
 +
|EIM_A25
 +
|CPU.EIM_A25
 +
|H19
 +
|-
 +
|J2.95
 +
|EIM_LBA
 +
|CPU.EIM_LBA
 +
|K22
 +
|-
 +
|J2.97
 +
|EIM_OE
 +
|CPU.EIM_OE
 +
|J24
 +
|-
 +
|J2.99
 +
|EIM_RW
 +
|CPU.EIM_RW
 +
|K20
 +
|-
 +
|J2.101
 +
|DGND
 +
|DGND
 +
|-
 +
|-
 +
|J2.103
 +
|EIM_BCLK
 +
|CPU.EIM_BCLK
 +
|N22
 +
|-
 +
|J2.105
 +
|EIM_WAIT
 +
|CPU.EIM_WAIT
 +
|M25
 +
|-
 +
|J2.107
 +
|EIM_EB0
 +
|CPU.EIM_EB0
 +
|K21
 +
|-
 +
|J2.109
 +
|EIM_EB1
 +
|CPU.EIM_EB1
 +
|K23
 +
|-
 +
|J2.111
 +
|EIM_EB2
 +
|CPU.EIM_EB2
 +
|E22
 +
|-
 +
|J2.113
 +
|EIM_EB3
 +
|CPU.EIM_EB3
 +
|F23
 +
|-
 +
|J2.115
 +
|EIM_CS0
 +
|CPU.EIM_CS0
 +
|H24
 +
|-
 +
|J2.117
 +
|EIM_CS1
 +
|CPU.EIM_CS1
 +
|J23
 +
|-
 +
|J2.119
 +
|DGND
 +
|DGND
 +
|-
 +
|-
 +
|J2.121
 +
|PMIC_PROG_VPGM
 +
|PMIC.VDDOTP
 +
|47
 +
|-
 +
|J2.123
 +
|PMIC_PROG_GATE_CTRL
 +
|
 +
|-
 +
|-
 +
|J2.125
 +
|2V8-4V5
 +
|INPUT VOLTAGE
 +
|-
 +
|-
 +
|J2.127
 +
|2V8-4V5
 +
|INPUT VOLTAGE
 +
|-
 +
|-
 +
|J2.129
 +
|2V8-4V5
 +
|INPUT VOLTAGE
 +
|-
 +
|-
 +
|J2.131
 +
|2V8-4V5
 +
|INPUT VOLTAGE
 +
|-
 +
|-
 +
|J2.133
 +
|2V8-4V5
 +
|INPUT VOLTAGE
 +
|-
 +
|-
 +
|J2.135
 +
|2V8-4V5
 +
|INPUT VOLTAGE
 +
|-
 +
|-
 +
|J2.137
 +
|2V8-4V5
 +
|INPUT VOLTAGE
 +
|-
 +
|-
 +
|J2.139
 +
|2V8-4V5
 +
|INPUT VOLTAGE
 +
|-
 +
|-
 +
|}
  
 
==J2 even pins (2 to 140)==
 
==J2 even pins (2 to 140)==
 +
 +
{| class="wikitable" {| {{table}}
 +
| align="center" style="background:#f0f0f0;"|'''Pin'''
 +
| align="center" style="background:#f0f0f0;"|'''Pin Name'''
 +
| align="center" style="background:#f0f0f0;"|'''Internal Connections'''
 +
| align="center" style="background:#f0f0f0;"|'''Ball/pin #'''
 +
|-
 +
|-
 +
|J2.2
 +
|NANDF_CS0_B
 +
|CPU.NANDF_CS0_B
 +
|F15
 +
|-
 +
|J2.4
 +
|NANDF_CS1_B
 +
|CPU.NANDF_CS1_B
 +
|C16
 +
|-
 +
|J2.6
 +
|NANDF_CS2_B
 +
|CPU.NANDF_CS2_B
 +
|A17
 +
|-
 +
|J2.8
 +
|NANDF_CS3_B
 +
|CPU.NANDF_CS3_B
 +
|D16
 +
|-
 +
|J2.10
 +
|DGND
 +
|DGND
 +
|-
 +
|-
 +
|J2.12
 +
|NANDF_D0
 +
|CPU.NANDF_D0
 +
|A18
 +
|-
 +
|J2.14
 +
|NANDF_D1
 +
|CPU.NANDF_D1
 +
|C17
 +
|-
 +
|J2.16
 +
|NANDF_D2
 +
|CPU.NANDF_D2
 +
|F16
 +
|-
 +
|J2.18
 +
|NANDF_D3
 +
|CPU.NANDF_D3
 +
|D17
 +
|-
 +
|J2.20
 +
|NANDF_D4
 +
|CPU.NANDF_D4
 +
|A19
 +
|-
 +
|J2.22
 +
|NANDF_D5
 +
|CPU.NANDF_D5
 +
|B18
 +
|-
 +
|J2.24
 +
|NANDF_D6
 +
|CPU.NANDF_D6
 +
|E17
 +
|-
 +
|J2.26
 +
|NANDF_D7
 +
|CPU.NANDF_D7
 +
|C18
 +
|-
 +
|J2.28
 +
|SD4_CLK/NANDF_WE_B
 +
|CPU.SD4_CLK
 +
|E16
 +
|-
 +
|J2.30
 +
|DGND
 +
|DGND
 +
|-
 +
|-
 +
|J2.32
 +
|SD4_DATA0/NANDF_DQS
 +
|CPU.SD4_DATA
 +
|D18
 +
|-
 +
|J2.34
 +
|SD4_CMD/NANDF_RE_B
 +
|CPU.SD4_CMD
 +
|B17
 +
|-
 +
|J2.36
 +
|NANDF_ALE
 +
|CPU.NANDF_ALE
 +
|A16
 +
|-
 +
|J2.38
 +
|NANDF_CLE
 +
|CPU.NANDF_CLE
 +
|C15
 +
|-
 +
|J2.40
 +
|NANDF_WP_B
 +
|CPU.NANDF_WP_B
 +
|E15
 +
|-
 +
|J2.42
 +
|NANDF_RB0
 +
|CPU.NANDF_RB0
 +
|B16
 +
|-
 +
|J2.44
 +
|SD4_DATA1
 +
|CPU.SD4_DATA1
 +
|B19
 +
|-
 +
|J2.46
 +
|SD4_DATA2
 +
|CPU.SD4_DATA2
 +
|F17
 +
|-
 +
|J2.48
 +
|SD4_DATA3
 +
|CPU.SD4_DATA3
 +
|A20
 +
|-
 +
|J2.50
 +
|DGND
 +
|DGND
 +
|-
 +
|-
 +
|J2.52
 +
|SD4_DATA4
 +
|CPU.SD4_DATA4
 +
|E18
 +
|-
 +
|J2.54
 +
|SD4_DATA5
 +
|CPU.SD4_DATA5
 +
|C19
 +
|-
 +
|J2.56
 +
|SD4_DATA6
 +
|CPU.SD4_DATA6
 +
|B20
 +
|-
 +
|J2.58
 +
|SD4_DATA7
 +
|CPU.SD4_DATA7
 +
|D19
 +
|-
 +
|J2.60
 +
|PMIC_SDWNB
 +
|PMIC.SDWNB
 +
|2
 +
|-
 +
|J2.62
 +
|TEST_MODE
 +
|CPU.TEST_MODE
 +
|E12
 +
|-
 +
|J2.64
 +
|RTC_INTN/SQW
 +
|RTC.INT/SQW
 +
|3
 +
|-
 +
|J2.66
 +
|RTC_RSTN
 +
|RTC.RST
 +
|4
 +
|-
 +
|J2.68
 +
|RTC_32KHZ
 +
|RTC.32KHZ
 +
|1
 +
|-
 +
|J2.70
 +
|DGND
 +
|DGND
 +
|-
 +
|-
 +
|J2.72
 +
|PMIC_INT_B
 +
|PMIC.INTB
 +
|1
 +
|-
 +
|J2.74
 +
|PMIC_PWRON
 +
|PMIC.PWRON
 +
|56
 +
|-
 +
|J2.76
 +
|CPU_ONOFF
 +
|CPU.CPU_ONOFF
 +
|D12
 +
|-
 +
|J2.78
 +
|CPU_PORN
 +
|CPU.CPU_PORN
 +
|C11
 +
|-
 +
|J2.80
 +
|CPU_PMIC_STBY_REQ
 +
|CPU.CPU_PMIC_STBY_REQ
 +
|F11
 +
|-
 +
|J2.82
 +
|CPU_PMIC_ON_REQ
 +
|CPU.CPU_PMIC_ON_REQ
 +
|D11
 +
|-
 +
|J2.84
 +
|BOOT_MODE0
 +
|CPU.BOOT_MODE0
 +
|C12
 +
|-
 +
|J2.86
 +
|BOOT_MODE1
 +
|CPU.BOOT_MODE1
 +
|F12
 +
|-
 +
|J2.88
 +
|MRSTN
 +
|MTR.MR
 +
|6
 +
|-
 +
|J2.90
 +
|DGND
 +
|DGND
 +
|-
 +
|-
 +
|J2.92
 +
|JTAG_TCK
 +
|CPU.JTAG_TCK
 +
|H5
 +
|-
 +
|J2.94
 +
|JTAG_VREF
 +
|
 +
|-
 +
|-
 +
|J2.96
 +
|JTAG_TDI
 +
|CPU.JTAG_TDI
 +
|G5
 +
|-
 +
|J2.98
 +
|JTAG_TDO
 +
|CPU.JTAG_TDO
 +
|G6
 +
|-
 +
|J2.100
 +
|JTAG_TMS
 +
|CPU.JTAG_TMS
 +
|C3
 +
|-
 +
|J2.102
 +
|JTAG_NTRST
 +
|CPU.JTAG_TRST
 +
|C2
 +
|-
 +
|J2.104
 +
|NOR_WP
 +
|NOR_WP
 +
|6
 +
|-
 +
|J2.106
 +
|NVCC_CSI_EXT
 +
|
 +
|
 +
|-
 +
|J2.108
 +
|DGND
 +
|DGND
 +
|-
 +
|-
 +
|J2.110
 +
|NVCC_EIM_EXT
 +
|
 +
|
 +
|-
 +
|J2.112
 +
|DGND
 +
|DGND
 +
|-
 +
|-
 +
|J2.114
 +
|NVCC_SD3_EXT
 +
|
 +
|
 +
|-
 +
|J2.116
 +
|DGND
 +
|DGND
 +
|-
 +
|-
 +
|J2.118
 +
|NVCC_LCD_EXT
 +
|
 +
|
 +
|-
 +
|J2.120
 +
|DGND
 +
|DGND
 +
|-
 +
|-
 +
|J2.122
 +
|PMIC_PROG_SCL
 +
|
 +
|-
 +
|-
 +
|J2.124
 +
|PMIC_PROG_SDA
 +
|
 +
|-
 +
|-
 +
|J2.126
 +
|2V8-4V5
 +
|INPUT VOLTAGE
 +
|-
 +
|-
 +
|J2.128
 +
|2V8-4V5
 +
|INPUT VOLTAGE
 +
|-
 +
|-
 +
|J2.130
 +
|2V8-4V5
 +
|INPUT VOLTAGE
 +
|-
 +
|-
 +
|J2.132
 +
|2V8-4V5
 +
|INPUT VOLTAGE
 +
|-
 +
|-
 +
|J2.134
 +
|2V8-4V5
 +
|INPUT VOLTAGE
 +
|-
 +
|-
 +
|J2.136
 +
|2V8-4V5
 +
|INPUT VOLTAGE
 +
|-
 +
|-
 +
|J2.138
 +
|2V8-4V5
 +
|INPUT VOLTAGE
 +
|-
 +
|-
 +
|J2.140
 +
|2V8-4V5
 +
|INPUT VOLTAGE
 +
|-
 +
|-
 +
|}
  
 
==J3 odd pins (1 to 139)==
 
==J3 odd pins (1 to 139)==
 +
 +
{| class="wikitable" {| {{table}}
 +
| align="center" style="background:#f0f0f0;"|'''Pin'''
 +
| align="center" style="background:#f0f0f0;"|'''Pin Name'''
 +
| align="center" style="background:#f0f0f0;"|'''Internal Connections'''
 +
| align="center" style="background:#f0f0f0;"|'''Ball/pin #'''
 +
|-
 +
|J3.1
 +
|SD3_CLK
 +
|CPU.SD3_CLK
 +
|D14
 +
|-
 +
|J3.3
 +
|DGND
 +
|DGND
 +
|-
 +
|-
 +
|J3.5
 +
|SD3_CMD
 +
|CPU.SD3_CMD
 +
|B13
 +
|-
 +
|J3.7
 +
|SD3_RST
 +
|CPU.SD3_RST
 +
|D15
 +
|-
 +
|J3.9
 +
|DGND
 +
|DGND
 +
|-
 +
|-
 +
|J3.11
 +
|SD3_DATA0
 +
|CPU.SD3_DATA0
 +
|E14
 +
|-
 +
|J3.13
 +
|SD3_DATA1
 +
|CPU.SD3_DATA1
 +
|F14
 +
|-
 +
|J3.15
 +
|SD3_DATA2
 +
|CPU.SD3_DATA2
 +
|A15
 +
|-
 +
|J3.17
 +
|SD3_DATA3
 +
|CPU.SD3_DATA3
 +
|B15
 +
|-
 +
|J3.19
 +
|SD3_DATA4
 +
|CPU.SD3_DATA4
 +
|D13
 +
|-
 +
|J3.21
 +
|SD3_DATA5
 +
|CPU.SD3_DATA5
 +
|C13
 +
|-
 +
|J3.23
 +
|SD3_DATA6
 +
|CPU.SD3_DATA6
 +
|E13
 +
|-
 +
|J3.25
 +
|SD3_DATA7
 +
|CPU.SD3_DATA7
 +
|F13
 +
|-
 +
|J3.27
 +
|DGND
 +
|DGND
 +
|-
 +
|-
 +
|J3.29
 +
|MLB_CN
 +
|CPU.MLB_CN
 +
|A11
 +
|-
 +
|J3.31
 +
|MLB_CP
 +
|CPU.MLB_CP
 +
|B11
 +
|-
 +
|J3.33
 +
|DGND
 +
|DGND
 +
|-
 +
|-
 +
|J3.35
 +
|MLB_SN
 +
|CPU.MLB_SN
 +
|A9
 +
|-
 +
|J3.37
 +
|MLB_SP
 +
|CPU.MLB_SP
 +
|B9
 +
|-
 +
|J3.39
 +
|DGND
 +
|DGND
 +
|-
 +
|-
 +
|J3.41
 +
|MLB_DN
 +
|CPU.MLB_DN
 +
|B10
 +
|-
 +
|J3.43
 +
|MLB_DP
 +
|CPU.MLB_DP
 +
|A10
 +
|-
 +
|J3.45
 +
|DGND
 +
|DGND
 +
|-
 +
|-
 +
|J3.47
 +
|SATA_RXN
 +
|CPU.SATA_RXN
 +
|A14
 +
|-
 +
|J3.49
 +
|SATA_RXP
 +
|CPU.SATA_RXP
 +
|B14
 +
|-
 +
|J3.51
 +
|DGND
 +
|DGND
 +
|-
 +
|-
 +
|J3.53
 +
|SATA_TXN
 +
|CPU.SATA_TXN
 +
|B12
 +
|-
 +
|J3.55
 +
|SATA_TXP
 +
|CPU.SATA_TXP
 +
|A12
 +
|-
 +
|J3.57
 +
|DGND
 +
|DGND
 +
|-
 +
|-
 +
|J3.59
 +
|CPU_RGMII_TXC_CONN
 +
|CPU.RGMII_TXC
 +
|D21
 +
|-
 +
|J3.61
 +
|DGND
 +
|DGND
 +
|-
 +
|-
 +
|J3.63
 +
|CPU_RGMII_TD0_CONN
 +
|CPU.RGMII_TD0
 +
|C22
 +
|-
 +
|J3.65
 +
|CPU_RGMII_TD1_CONN
 +
|CPU.RGMII_TD1
 +
|F20
 +
|-
 +
|J3.67
 +
|CPU_RGMII_TD2_CONN
 +
|CPU.RGMII_TD2
 +
|E21
 +
|-
 +
|J3.69
 +
|CPU_RGMII_TD3_CONN
 +
|CPU.RGMII_TD3
 +
|A24
 +
|-
 +
|J3.71
 +
|CPU_RGMII_TX_CTL_CONN
 +
|CPU.RGMII_TX_CTL
 +
|C23
 +
|-
 +
|J3.73
 +
|DGND
 +
|DGND
 +
|-
 +
|-
 +
|J3.75
 +
|CPU_RGMII_RXC_CONN
 +
|CPU.RGMII_RXC
 +
|B25
 +
|-
 +
|J3.77
 +
|DGND
 +
|DGND
 +
|-
 +
|-
 +
|J3.79
 +
|CPU_RGMII_RD0_CONN
 +
|CPU.RGMII_RD0
 +
|C24
 +
|-
 +
|J3.81
 +
|CPU_RGMII_RD1_CONN
 +
|CPU.RGMII_RD1
 +
|B23
 +
|-
 +
|J3.83
 +
|CPU_RGMII_RD2_CONN
 +
|CPU.RGMII_RD2
 +
|B24
 +
|-
 +
|J3.85
 +
|CPU_RGMII_RD3_CONN
 +
|CPU.RGMII_RD3
 +
|D23
 +
|-
 +
|J3.87
 +
|CPU_RGMII_RX_CTL_CONN
 +
|CPU.RGMII_RX_CTL
 +
|D22
 +
|-
 +
|J3.89
 +
|DGND
 +
|DGND
 +
|-
 +
|-
 +
|J3.91
 +
|ETH0_CLK125_NDO
 +
|LAN.CLK125_NDO
 +
|41
 +
|-
 +
|J3.93
 +
|DGND
 +
|DGND
 +
|-
 +
|-
 +
|J3.95
 +
|ETH0_INTN
 +
|LAN.INT_N/PME_N2
 +
|38
 +
|-
 +
|J3.97
 +
|ENET_TX_EN/GPIO1_IO28
 +
|CPU.ENET_TX_EN
 +
|V21
 +
|-
 +
|J3.99
 +
|TAMPER
 +
|CPU.TAMPER
 +
|E11
 +
|-
 +
|J3.101
 +
|ENET_REF_CLK//VDDCORE
 +
|CPU.ENET_REF_CLK
 +
|V22
 +
|-
 +
|J3.103
 +
|ENET_RX_ER//VDDSOC
 +
|CPU.ENET_RX_ER
 +
|W23
 +
|-
 +
|J3.105
 +
|ENET_RXD0//DDR_1V5
 +
|CPU.ENET_RXD0
 +
|W21
 +
|-
 +
|J3.107
 +
|ENET_RXD1
 +
|CPU.ENET_RXD1
 +
|W22
 +
|-
 +
|J3.109
 +
|ENET_TXD0//BB_3.3V/2.5V
 +
|CPU.ENET_TXD0
 +
|U20
 +
|-
 +
|J3.111
 +
|ENET_TXD1//1V2_ETH
 +
|CPU.ENET_TXD1
 +
|W20
 +
|-
 +
|J3.113
 +
|KEY_COL4//ENET_CRS_DV//VDDHIGH_VPH
 +
|CPU.KEY_COL4
 +
|T6
 +
|-
 +
|J3.115
 +
|KEY_ROW4//VDDSOC_CAP
 +
|CPU.KEY_ROW4
 +
|V5
 +
|-
 +
|J3.117
 +
|WDT_WDI//VDDPU
 +
|WDT.WDI
 +
|1
 +
|-
 +
|J3.119
 +
|VDD_ARM23_CAP//VGEN4_1V8
 +
|
 +
|-
 +
|-
 +
|J3.121
 +
|VDD_ARM01_CAP//VGEN5_2V8//VDD_VBUS_CAP
 +
|
 +
|-
 +
|-
 +
|J3.123
 +
|VDD_SNVS_CAP//VGEN3_2V5//NVCC_PLL_OUT
 +
|
 +
|-
 +
|-
 +
|J3.125
 +
|VGEN1
 +
|
 +
|-
 +
|-
 +
|J3.127
 +
|VGEN2
 +
|
 +
|-
 +
|-
 +
|J3.129
 +
|VGEN6
 +
|
 +
|-
 +
|-
 +
|J3.131
 +
|SW4_XV/1.8V
 +
|
 +
|-
 +
|-
 +
|J3.133
 +
|PMIC_SWBST_SUPPLY
 +
|
 +
|-
 +
|-
 +
|J3.135
 +
|PMIC_SWBST_SUPPLY
 +
|
 +
|-
 +
|-
 +
|J3.137
 +
|PMIC_SWBST_SUPPLY
 +
|
 +
|-
 +
|-
 +
|J3.139
 +
|DGND
 +
|DGND
 +
|-
 +
|-
 +
|}
  
 
==J3 even pins (2 to 140)==
 
==J3 even pins (2 to 140)==
 +
 +
{| class="wikitable" {| {{table}}
 +
| align="center" style="background:#f0f0f0;"|'''Pin'''
 +
| align="center" style="background:#f0f0f0;"|'''Pin Name'''
 +
| align="center" style="background:#f0f0f0;"|'''Internal Connections'''
 +
| align="center" style="background:#f0f0f0;"|'''Ball/pin #'''
 +
|-
 +
|J3.2
 +
|DGND
 +
|DGND
 +
|-
 +
|-
 +
|J3.4
 +
|CSI_CLK0M
 +
|CPU.CSI_CLK0M
 +
|F4
 +
|-
 +
|J3.6
 +
|CSI_CLK0P
 +
|CPU.CSI_CLK0P
 +
|F3
 +
|-
 +
|J3.8
 +
|DGND
 +
|DGND
 +
|-
 +
|-
 +
|J3.10
 +
|CSI_D0M
 +
|CPU.CSI_D0M
 +
|E4
 +
|-
 +
|J3.12
 +
|CSI_D0P
 +
|CPU.CSI_D0P
 +
|E3
 +
|-
 +
|J3.14
 +
|DGND
 +
|DGND
 +
|-
 +
|-
 +
|J3.16
 +
|CSI_D1M
 +
|CPU.CSI_D1M
 +
|D1
 +
|-
 +
|J3.18
 +
|CSI_D1P
 +
|CPU.CSI_D1P
 +
|D2
 +
|-
 +
|J3.20
 +
|DGND
 +
|DGND
 +
|-
 +
|-
 +
|J3.22
 +
|CSI_D2M
 +
|CPU.CSI_D2M
 +
|E1
 +
|-
 +
|J3.24
 +
|CSI_D2P
 +
|CPU.CSI_D2P
 +
|E2
 +
|-
 +
|J3.26
 +
|DGND
 +
|DGND
 +
|-
 +
|-
 +
|J3.28
 +
|CSI_D3M
 +
|CPU.CSI_D3M
 +
|F2
 +
|-
 +
|J3.30
 +
|CSI_D3P
 +
|CPU.CSI_D3P
 +
|F1
 +
|-
 +
|J3.32
 +
|DGND
 +
|DGND
 +
|-
 +
|-
 +
|J3.34
 +
|DSI_CLK0M
 +
|CPU.DSI_CLK0M
 +
|H3
 +
|-
 +
|J3.36
 +
|DSI_CLK0P
 +
|CPU.DSI_CLK0P
 +
|H4
 +
|-
 +
|J3.38
 +
|DGND
 +
|DGND
 +
|-
 +
|-
 +
|J3.40
 +
|DSI_D0M
 +
|CPU.DSI_D0M
 +
|G2
 +
|-
 +
|J3.42
 +
|DSI_DOP
 +
|CPU.DSI_DOP
 +
|G1
 +
|-
 +
|J3.44
 +
|DGND
 +
|DGND
 +
|-
 +
|-
 +
|J3.46
 +
|DSI_D1M
 +
|CPU.DSI_D1M
 +
|H2
 +
|-
 +
|J3.48
 +
|DSI_D1P
 +
|CPU.DSI_D1P
 +
|H1
 +
|-
 +
|J3.50
 +
|DGND
 +
|DGND
 +
|-
 +
|-
 +
|J3.52
 +
|LVDS1_TX0_N
 +
|CPU.LVDS1_TX0_N
 +
|Y1
 +
|-
 +
|J3.54
 +
|LVDS1_TX0_P
 +
|CPU.LVDS1_TX0_P
 +
|Y2
 +
|-
 +
|J3.56
 +
|DGND
 +
|DGND
 +
|-
 +
|-
 +
|J3.58
 +
|LVDS1_TX1_N
 +
|CPU.LVDS1_TX1_N
 +
|AA2
 +
|-
 +
|J3.60
 +
|LVDS1_TX1_P
 +
|CPU.LVDS1_TX1_P
 +
|AA1
 +
|-
 +
|J3.62
 +
|DGND
 +
|DGND
 +
|-
 +
|-
 +
|J3.64
 +
|LVDS1_TX2_N
 +
|CPU.LVDS1_TX2_N
 +
|AB1
 +
|-
 +
|J3.66
 +
|LVDS1_TX2_P
 +
|CPU.LVDS1_TX2_P
 +
|AB2
 +
|-
 +
|J3.68
 +
|DGND
 +
|DGND
 +
|-
 +
|-
 +
|J3.70
 +
|LVDS1_CLK_N
 +
|CPU.LVDS1_CLK_N
 +
|Y3
 +
|-
 +
|J3.72
 +
|LVDS1_CLK_P
 +
|CPU.LVDS1_CLK_P
 +
|Y4
 +
|-
 +
|J3.74
 +
|DGND
 +
|DGND
 +
|-
 +
|-
 +
|J3.76
 +
|LVDS1_TX3_N
 +
|CPU.LVDS1_TX3_N
 +
|AA3
 +
|-
 +
|J3.78
 +
|LVDS1_TX3_P
 +
|CPU.LVDS1_TX3_P
 +
|AA4
 +
|-
 +
|J3.80
 +
|DGND
 +
|DGND
 +
|-
 +
|-
 +
|J3.82
 +
|HDMI_CLKN
 +
|CPU.HDMI_CLKN
 +
|J5
 +
|-
 +
|J3.84
 +
|HDMI_CLKP
 +
|CPU.HDMI_CLKP
 +
|J6
 +
|-
 +
|J3.86
 +
|DGND
 +
|DGND
 +
|-
 +
|-
 +
|J3.88
 +
|HDMI_D0N
 +
|CPU.HDMI_D0N
 +
|K5
 +
|-
 +
|J3.90
 +
|HDMI_D0P
 +
|CPU.HDMI_D0P
 +
|K6
 +
|-
 +
|J3.92
 +
|DGND
 +
|DGND
 +
|-
 +
|-
 +
|J3.94
 +
|HDMI_D1N
 +
|CPU.HDMI_D1N
 +
|J3
 +
|-
 +
|J3.96
 +
|HDMI_D1P
 +
|CPU.HDMI_D1P
 +
|J4
 +
|-
 +
|J3.98
 +
|DGND
 +
|DGND
 +
|-
 +
|-
 +
|J3.100
 +
|HDMI_D2N
 +
|CPU.HDMI_D2N
 +
|K3
 +
|-
 +
|J3.102
 +
|HDMI_D2P
 +
|CPU.HDMI_D2P
 +
|K4
 +
|-
 +
|J3.104
 +
|DGND
 +
|DGND
 +
|-
 +
|-
 +
|J3.106
 +
|HDMI_CEC_IN
 +
|CPU.HDMI_DDCCEC
 +
|K2
 +
|-
 +
|J3.108
 +
|HDMI_HPD
 +
|CPU.HDMI_HPD
 +
|K1
 +
|-
 +
|J3.110
 +
|DGND
 +
|DGND
 +
|-
 +
|-
 +
|J3.112
 +
|CLK1_N
 +
|CPU.CLK1_N
 +
|C7
 +
|-
 +
|J3.114
 +
|CLK1_P
 +
|CPU.CLK1_P
 +
|D7
 +
|-
 +
|J3.116
 +
|DGND
 +
|DGND
 +
|-
 +
|-
 +
|J3.118
 +
|CLK2_N
 +
|CPU.CLK2_N
 +
|C5
 +
|-
 +
|J3.120
 +
|CLK2_P
 +
|CPU.CLK2_P
 +
|D5
 +
|-
 +
|J3.122
 +
|DGND
 +
|DGND
 +
|-
 +
|-
 +
|J3.124
 +
|PCIE_RXN
 +
|CPU.PCIE_RXN
 +
|B1
 +
|-
 +
|J3.126
 +
|PCIE_RXP
 +
|CPU.PCIE_RXP
 +
|B2
 +
|-
 +
|J3.128
 +
|DGND
 +
|DGND
 +
|-
 +
|-
 +
|J3.130
 +
|PCIE_TXN
 +
|CPU.PCIE_TXN
 +
|A3
 +
|-
 +
|J3.132
 +
|PCIE_TXP
 +
|CPU.PCIE_TXP
 +
|B3
 +
|-
 +
|J3.134
 +
|DGND
 +
|DGND
 +
|-
 +
|-
 +
|J3.136
 +
|PMIC_5V
 +
|
 +
|-
 +
|-
 +
|J3.138
 +
|PMIC_5V
 +
|
 +
|-
 +
|-
 +
|J3.140
 +
|DGND
 +
|DGND
 +
|-
 +
|-
 +
|}

Latest revision as of 09:47, 22 April 2015

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Axel-04.png Applies to Axel Ultra

Introduction[edit | edit source]

This chapter contains the pinout description of the Axel Ultra module, grouped in six tables (two – odd and even pins – for each connector) that report the pin mapping of the three 140-pin Axel Ultra connectors.

Each row in the pinout tables contains the following information:

  • Pin: reference to the connector pin
  • Pin Name: pin (signal) name on the Axel Ultra connectors
  • Internal connections: connections to the Axel Ultra components
    • CPU.<x> : pin connected to CPU pad named <x>
    • CAN.<x> : pin connected to the CAN transceiver
    • PMIC.<x> : pin connected to the Power Manager IC
    • LAN.<x> : pin connected to the LAN PHY
    • NOR.<x>: pin connected to the flash NOR
    • SV.<x>: pin connected to voltage supervisor
    • MTR: pin connected to voltage monitors
  • Ball/pin #: Component ball/pin number connected to signal
  • Supply Group: Power Supply Group
  • Type: pin type
    • I = Input
    • O = Output
    • D = Differential
    • Z = High impedance
    • S = Power supply voltage
    • G = Ground
    • A = Analog signal
  • Voltage: I/O voltage levels

J1 odd pins (1 to 139)[edit | edit source]

Pin Pin Name Internal Connections Ball/pin #
J1.1 DGND DGND
J1.3 DI0_DISP_CLK CPU.DI0_DISP_CLK N19
J1.5 DI0_PIN2 CPU.DI0_PIN2 N25
J1.7 DI0_PIN3 CPU.DI0_PIN3 N20
J1.9 DI0_PIN4 CPU.DI0_PIN4 P25
J1.11 DI0_PIN15 CPU.DI0_PIN15 N21
J1.13 DISP0_DAT0 CPU.DISP0_DAT0 P24
J1.15 DISP0_DAT1 CPU.DISP0_DAT1 P22
J1.17 DISP0_DAT2 CPU.DISP0_DAT2 P23
J1.19 DISP0_DAT3 CPU.DISP0_DAT3 P21
J1.21 DGND DGND
J1.23 DISP0_DAT4 CPU.DISP0_DAT4 P20
J1.25 DISP0_DAT5 CPU.DISP0_DAT5 R25
J1.27 DISP0_DAT6 CPU.DISP0_DAT6 R23
J1.29 DISP0_DAT7 CPU.DISP0_DAT7 R24
J1.31 DISP0_DAT8 CPU.DISP0_DAT8 R22
J1.33 DISP0_DAT9 CPU.DISP0_DAT9 T25
J1.35 DISP0_DAT10 CPU.DISP0_DAT10 R21
J1.37 DISP0_DAT11 CPU.DISP0_DAT11 T23
J1.39 DISP0_DAT12 CPU.DISP0_DAT12 T24
J1.41 DGND DGND
J1.43 DISP0_DAT13 CPU.DISP0_DAT13 R20
J1.45 DISP0_DAT14 CPU.DISP0_DAT14 U25
J1.47 DISP0_DAT15 CPU.DISP0_DAT15 T22
J1.49 DISP0_DAT16 CPU.DISP0_DAT16 T21
J1.51 DISP0_DAT17 CPU.DISP0_DAT17 U24
J1.53 DISP0_DAT18 CPU.DISP0_DAT18 V25
J1.55 DISP0_DAT19 CPU.DISP0_DAT19 U23
J1.57 DISP0_DAT20 CPU.DISP0_DAT20 U22
J1.59 DISP0_DAT21 CPU.DISP0_DAT21 T20
J1.61 DGND DGND
J1.63 DISP0_DAT22 CPU.DISP0_DAT22 V24
J1.65 DISP0_DAT23 CPU.DISP0_DAT23 W24
J1.67 WD_SET0 WDT.SET0
J1.69 WD_SET1 WDT.SET0
J1.71 WD_SET2 WDT.SET0
J1.73 USB_OTG_CHDN CPU.USB_OTG_CHDN B8
J1.75 USB_OTG_VBUS CPU.USB_OTG_VBUS E9
J1.77 USB_OTG_DN CPU.USB_OTG_DN B6
J1.79 USB_OTG_DP CPU.USB_OTG_DP A6
J1.81 DGND DGND
J1.83 USB_HOST_DP CPU.USB_HOST_DP E10
J1.85 USB_HOST_DN CPU.USB_HOST_DN F10
J1.87 USB_H1_VBUS CPU.USB_H1_VBUS D10
J1.89 SD1_DAT0 CPU.SD1_DAT0 A21
J1.91 SD1_DAT1 CPU.SD1_DAT1 C20
J1.93 SD1_DAT2 CPU.SD1_DAT2 E19
J1.95 SD1_DAT3 CPU.SD1_DAT3 F18
J1.97 SD1_CMD CPU.SD1_CMD B21
J1.99 SD1_CLK CPU.SD1_CLK D20
J1.101 DGND DGND
J1.103 SW2_1.8V/3.3V
J1.105 ETH0_LED1 LAN.LED1/PME_N1 17
J1.107 ETH0_LED2 LAN.LED2 15
J1.109 DGND DGND
J1.111 ETH0_TXRX0_M LAN.TXRXM_A 3
J1.113 ETH0_TXRX0_P LAN.TXRXP_A 2
J1.115 DGND DGND
J1.117 ETH0_TXRX1_M LAN.TXRXM_B 6
J1.119 ETH0_TXRX1_P LAN.TXRXP_B 5
J1.121 DGND DGND
J1.123 ETH0_TXRX2_M LAN.TXRXM_C 8
J1.125 ETH0_TXRX2_P LAN.TXRXP_C 7
J1.127 DGND DGND
J1.129 ETH0_TXRX3_M LAN.TXRXM_D 11
J1.131 ETH0_TXRX3_P LAN.TXRXP_D 10
J1.133 DGND DGND
J1.135 RGMII_MDC CPU.ENET_MDC V20
J1.137 RGMII_MDIO CPU.ENET_MDIO V23
J1.139 PMIC_VSNVS CPU.VDD_SNVS_IN G11

J1 even pins (2 to 140)[edit | edit source]

Pin Pin Name Internal Connections Ball/pin #
J1.2 LVDS0_TX0_N CPU.LVDS0_TX0_N U2
J1.4 LVDS0_TX0_P CPU.LVDS0_TX0_P U1
J1.6 LVDS0_TX1_N CPU.LVDS0_TX1_N U4
J1.8 LVDS0_TX1_P CPU.LVDS0_TX1_P U3
J1.10 DGND DGND
J1.12 LVDS0_TX2_N CPU.LVDS0_TX2_N V2
J1.14 LVDS0_TX2_P CPU.LVDS0_TX2_P V1
J1.16 LVDS0_TX3_N CPU.LVDS0_TX3_N W2
J1.18 LVDS0_TX3_P CPU.LVDS0_TX3_P W1
J1.20 LVDS0_CLK_N CPU.LVDS0_CLK_N V4
J1.22 LVDS0_CLK_P CPU.LVDS0_CLK_P V3
J1.24 DGND DGND
J1.26 CSI0_MCLK CPU.CSI0_MCLK P4
J1.28 DGND DGND
J1.30 CSI0_PIXCLK CPU.CSI0_PIXCLK P1
J1.32 CSI0_VSYNC CPU.CSI0_VSYNC N2
J1.34 CSI0_DATA_EN CPU.CSI0_DATA_EN P3
J1.36 CSI0_DAT4 CPU.CSI0_DAT4 N1
J1.38 CSI0_DAT5 CPU.CSI0_DAT5 P2
J1.40 CSI0_DAT6 CPU.CSI0_DAT6 N4
J1.42 CSI0_DAT7 CPU.CSI0_DAT7 N3
J1.44 CSI0_DAT8 CPU.CSI0_DAT8 N6
J1.46 CSI0_DAT9 CPU.CSI0_DAT9 N5
J1.48 CSI0_DAT10 CPU.CSI0_DAT10 M1
J1.50 DGND DGND
J1.52 CSI0_DAT11 CPU.CSI0_DAT11 M3
J1.54 CSI0_DAT12 CPU.CSI0_DAT12 M2
J1.56 CSI0_DAT13 CPU.CSI0_DAT13 L1
J1.58 CSI0_DAT14 CPU.CSI0_DAT14 M4
J1.60 CSI0_DAT15 CPU.CSI0_DAT15 M5
J1.62 CSI0_DAT16 CPU.CSI0_DAT16 L4
J1.64 CSI0_DAT17 CPU.CSI0_DAT17 L3
J1.66 CSI0_DAT18 CPU.CSI0_DAT18 M6
J1.68 CSI0_DAT19 CPU.CSI0_DAT19 L6
J1.70 DGND DGND
J1.72 GPIO_0 CPU.GPIO_0 T5
J1.74 GPIO_1 CPU.GPIO_1 T4
J1.76 GPIO_2 CPU.GPIO_2 T1
J1.78 GPIO_3/I2C3_SCL CPU.GPIO_3 R7
J1.80 GPIO_4 CPU.GPIO_4 R6
J1.82 GPIO_5 CPU.GPIO_5 R4
J1.84 GPIO_6/I2C3_SDA CPU.GPIO_6 T3
J1.86 GPIO_7//FLEXCAN1_H CPU.GPIO_7 R3
J1.88 GPIO_8//FLEXCAN1_L CPU.GPIO_8 R5
J1.90 DGND DGND
J1.92 GPIO_9 CPU.GPIO_9 T2
J1.94 GPIO_16 CPU.GPIO_16 R2
J1.96 GPIO_17 CPU.GPIO_17 R1
J1.98 GPIO_18/PMIC_INT_B CPU.GPIO_18 P6
J1.100 GPIO_19 CPU.GPIO_19 P5
J1.102 KEY_COL0/ECSPI1_SCLK CPU.KEY_COL0 W5
J1.104 KEY_ROW0/ECSPI1_MOSI CPU.KEY_ROW0 V6
J1.106 KEY_COL1/ECSPI1_MISO CPU.KEY_COL1 U7
J1.108 KEY_ROW1/ECSPI1_SS0 CPU.KEY_ROW1 U6
J1.110 DGND DGND
J1.112 KEY_COL2/ECSPI1_SS1 CPU.KEY_COL2 W6
J1.114 KEY_ROW2 CPU.KEY_ROW2 W4
J1.116 KEY_COL3/I2C2_SCL CPU.KEY_COL3 U5
J1.118 KEY_ROW3/I2C2_SDA CPU.KEY_ROW3 T7
J1.120 VGEN4_1V8_I
J1.122 NVCC_AXEL_I/O_3.3V/1.8V (BOARD_PGOOD) P7
J1.124 RTC_VBAT RTC.VBAT 6
J1.126 PMIC_LICELL PMIC.LICELL 42
J1.128 SD2_CMD CPU.SD2_CMD F19
J1.130 DGND DGND
J1.132 SD2_CLK CPU.SD2_CLK C21
J1.134 SD2_DATA0 CPU.SD2_DATA0 A22
J1.136 SD2_DATA1 CPU.SD2_DATA1 E20
J1.138 SD2_DATA2 CPU.SD2_DATA2 A23
J1.140 SD2_DATA3 CPU.SD2_DATA3 B22

J2 odd pins (1 to 139)[edit | edit source]

Pin Pin Name Internal Connections Ball/pin #
J2.1 DGND DGND
J2.3 EIM_DA0 CPU.EIM_DA0 L20
J2.5 EIM_DA1 CPU.EIM_DA1 J25
J2.7 EIM_DA2 CPU.EIM_DA2 L21
J2.9 EIM_DA3 CPU.EIM_DA3 K24
J2.11 EIM_DA4 CPU.EIM_DA4 L22
J2.13 EIM_DA5 CPU.EIM_DA5 L23
J2.15 EIM_DA6 CPU.EIM_DA6 K25
J2.17 EIM_DA7 CPU.EIM_DA7 L25
J2.19 EIM_DA8 CPU.EIM_DA8 L24
J2.21 DGND DGND
J2.23 EIM_DA9 CPU.EIM_DA9 M21
J2.25 EIM_DA10 CPU.EIM_DA10 M22
J2.27 EIM_DA11 CPU.EIM_DA11 M20
J2.29 EIM_DA12 CPU.EIM_DA12 M24
J2.31 EIM_DA13 CPU.EIM_DA13 M23
J2.33 EIM_DA14 CPU.EIM_DA14 N23
J2.35 EIM_DA15 CPU.EIM_DA15 N24
J2.37 EIM_D16 CPU.EIM_D16 C25
J2.39 EIM_D17 CPU.EIM_D17 F21
J2.41 DGND DGND
J2.43 EIM_D18 CPU.EIM_D18 D24
J2.45 EIM_D19 CPU.EIM_D19 G21
J2.47 EIM_D20 CPU.EIM_D20 G20
J2.49 EIM_D21 CPU.EIM_D21 H20
J2.51 EIM_D22 CPU.EIM_D22 E23
J2.53 EIM_D23 CPU.EIM_D23 D25
J2.55 EIM_D24 CPU.EIM_D24 F22
J2.57 EIM_D25 CPU.EIM_D25 G22
J2.59 EIM_D26 CPU.EIM_D26 E24
J2.61 DGND DGND
J2.63 EIM_D27 CPU.EIM_D27 E25
J2.65 EIM_D28 CPU.EIM_D28 G23
J2.67 EIM_D29 CPU.EIM_D29 J19
J2.69 EIM_D30 CPU.EIM_D30 J20
J2.71 EIM_D31 CPU.EIM_D31 H21
J2.73 EIM_A16 CPU.EIM_A16 H25
J2.75 EIM_A17 CPU.EIM_A17 G24
J2.77 EIM_A18 CPU.EIM_A18 J22
J2.79 EIM_A19 CPU.EIM_A19 G25
J2.81 DGND DGND
J2.83 EIM_A20 CPU.EIM_A20 H22
J2.85 EIM_A21 CPU.EIM_A21 H23
J2.87 EIM_A22 CPU.EIM_A22 F24
J2.89 EIM_A23 CPU.EIM_A23 J21
J2.91 EIM_A24 CPU.EIM_A24 F25
J2.93 EIM_A25 CPU.EIM_A25 H19
J2.95 EIM_LBA CPU.EIM_LBA K22
J2.97 EIM_OE CPU.EIM_OE J24
J2.99 EIM_RW CPU.EIM_RW K20
J2.101 DGND DGND
J2.103 EIM_BCLK CPU.EIM_BCLK N22
J2.105 EIM_WAIT CPU.EIM_WAIT M25
J2.107 EIM_EB0 CPU.EIM_EB0 K21
J2.109 EIM_EB1 CPU.EIM_EB1 K23
J2.111 EIM_EB2 CPU.EIM_EB2 E22
J2.113 EIM_EB3 CPU.EIM_EB3 F23
J2.115 EIM_CS0 CPU.EIM_CS0 H24
J2.117 EIM_CS1 CPU.EIM_CS1 J23
J2.119 DGND DGND
J2.121 PMIC_PROG_VPGM PMIC.VDDOTP 47
J2.123 PMIC_PROG_GATE_CTRL
J2.125 2V8-4V5 INPUT VOLTAGE
J2.127 2V8-4V5 INPUT VOLTAGE
J2.129 2V8-4V5 INPUT VOLTAGE
J2.131 2V8-4V5 INPUT VOLTAGE
J2.133 2V8-4V5 INPUT VOLTAGE
J2.135 2V8-4V5 INPUT VOLTAGE
J2.137 2V8-4V5 INPUT VOLTAGE
J2.139 2V8-4V5 INPUT VOLTAGE

J2 even pins (2 to 140)[edit | edit source]

Pin Pin Name Internal Connections Ball/pin #
J2.2 NANDF_CS0_B CPU.NANDF_CS0_B F15
J2.4 NANDF_CS1_B CPU.NANDF_CS1_B C16
J2.6 NANDF_CS2_B CPU.NANDF_CS2_B A17
J2.8 NANDF_CS3_B CPU.NANDF_CS3_B D16
J2.10 DGND DGND
J2.12 NANDF_D0 CPU.NANDF_D0 A18
J2.14 NANDF_D1 CPU.NANDF_D1 C17
J2.16 NANDF_D2 CPU.NANDF_D2 F16
J2.18 NANDF_D3 CPU.NANDF_D3 D17
J2.20 NANDF_D4 CPU.NANDF_D4 A19
J2.22 NANDF_D5 CPU.NANDF_D5 B18
J2.24 NANDF_D6 CPU.NANDF_D6 E17
J2.26 NANDF_D7 CPU.NANDF_D7 C18
J2.28 SD4_CLK/NANDF_WE_B CPU.SD4_CLK E16
J2.30 DGND DGND
J2.32 SD4_DATA0/NANDF_DQS CPU.SD4_DATA D18
J2.34 SD4_CMD/NANDF_RE_B CPU.SD4_CMD B17
J2.36 NANDF_ALE CPU.NANDF_ALE A16
J2.38 NANDF_CLE CPU.NANDF_CLE C15
J2.40 NANDF_WP_B CPU.NANDF_WP_B E15
J2.42 NANDF_RB0 CPU.NANDF_RB0 B16
J2.44 SD4_DATA1 CPU.SD4_DATA1 B19
J2.46 SD4_DATA2 CPU.SD4_DATA2 F17
J2.48 SD4_DATA3 CPU.SD4_DATA3 A20
J2.50 DGND DGND
J2.52 SD4_DATA4 CPU.SD4_DATA4 E18
J2.54 SD4_DATA5 CPU.SD4_DATA5 C19
J2.56 SD4_DATA6 CPU.SD4_DATA6 B20
J2.58 SD4_DATA7 CPU.SD4_DATA7 D19
J2.60 PMIC_SDWNB PMIC.SDWNB 2
J2.62 TEST_MODE CPU.TEST_MODE E12
J2.64 RTC_INTN/SQW RTC.INT/SQW 3
J2.66 RTC_RSTN RTC.RST 4
J2.68 RTC_32KHZ RTC.32KHZ 1
J2.70 DGND DGND
J2.72 PMIC_INT_B PMIC.INTB 1
J2.74 PMIC_PWRON PMIC.PWRON 56
J2.76 CPU_ONOFF CPU.CPU_ONOFF D12
J2.78 CPU_PORN CPU.CPU_PORN C11
J2.80 CPU_PMIC_STBY_REQ CPU.CPU_PMIC_STBY_REQ F11
J2.82 CPU_PMIC_ON_REQ CPU.CPU_PMIC_ON_REQ D11
J2.84 BOOT_MODE0 CPU.BOOT_MODE0 C12
J2.86 BOOT_MODE1 CPU.BOOT_MODE1 F12
J2.88 MRSTN MTR.MR 6
J2.90 DGND DGND
J2.92 JTAG_TCK CPU.JTAG_TCK H5
J2.94 JTAG_VREF
J2.96 JTAG_TDI CPU.JTAG_TDI G5
J2.98 JTAG_TDO CPU.JTAG_TDO G6
J2.100 JTAG_TMS CPU.JTAG_TMS C3
J2.102 JTAG_NTRST CPU.JTAG_TRST C2
J2.104 NOR_WP NOR_WP 6
J2.106 NVCC_CSI_EXT
J2.108 DGND DGND
J2.110 NVCC_EIM_EXT
J2.112 DGND DGND
J2.114 NVCC_SD3_EXT
J2.116 DGND DGND
J2.118 NVCC_LCD_EXT
J2.120 DGND DGND
J2.122 PMIC_PROG_SCL
J2.124 PMIC_PROG_SDA
J2.126 2V8-4V5 INPUT VOLTAGE
J2.128 2V8-4V5 INPUT VOLTAGE
J2.130 2V8-4V5 INPUT VOLTAGE
J2.132 2V8-4V5 INPUT VOLTAGE
J2.134 2V8-4V5 INPUT VOLTAGE
J2.136 2V8-4V5 INPUT VOLTAGE
J2.138 2V8-4V5 INPUT VOLTAGE
J2.140 2V8-4V5 INPUT VOLTAGE

J3 odd pins (1 to 139)[edit | edit source]

Pin Pin Name Internal Connections Ball/pin #
J3.1 SD3_CLK CPU.SD3_CLK D14
J3.3 DGND DGND
J3.5 SD3_CMD CPU.SD3_CMD B13
J3.7 SD3_RST CPU.SD3_RST D15
J3.9 DGND DGND
J3.11 SD3_DATA0 CPU.SD3_DATA0 E14
J3.13 SD3_DATA1 CPU.SD3_DATA1 F14
J3.15 SD3_DATA2 CPU.SD3_DATA2 A15
J3.17 SD3_DATA3 CPU.SD3_DATA3 B15
J3.19 SD3_DATA4 CPU.SD3_DATA4 D13
J3.21 SD3_DATA5 CPU.SD3_DATA5 C13
J3.23 SD3_DATA6 CPU.SD3_DATA6 E13
J3.25 SD3_DATA7 CPU.SD3_DATA7 F13
J3.27 DGND DGND
J3.29 MLB_CN CPU.MLB_CN A11
J3.31 MLB_CP CPU.MLB_CP B11
J3.33 DGND DGND
J3.35 MLB_SN CPU.MLB_SN A9
J3.37 MLB_SP CPU.MLB_SP B9
J3.39 DGND DGND
J3.41 MLB_DN CPU.MLB_DN B10
J3.43 MLB_DP CPU.MLB_DP A10
J3.45 DGND DGND
J3.47 SATA_RXN CPU.SATA_RXN A14
J3.49 SATA_RXP CPU.SATA_RXP B14
J3.51 DGND DGND
J3.53 SATA_TXN CPU.SATA_TXN B12
J3.55 SATA_TXP CPU.SATA_TXP A12
J3.57 DGND DGND
J3.59 CPU_RGMII_TXC_CONN CPU.RGMII_TXC D21
J3.61 DGND DGND
J3.63 CPU_RGMII_TD0_CONN CPU.RGMII_TD0 C22
J3.65 CPU_RGMII_TD1_CONN CPU.RGMII_TD1 F20
J3.67 CPU_RGMII_TD2_CONN CPU.RGMII_TD2 E21
J3.69 CPU_RGMII_TD3_CONN CPU.RGMII_TD3 A24
J3.71 CPU_RGMII_TX_CTL_CONN CPU.RGMII_TX_CTL C23
J3.73 DGND DGND
J3.75 CPU_RGMII_RXC_CONN CPU.RGMII_RXC B25
J3.77 DGND DGND
J3.79 CPU_RGMII_RD0_CONN CPU.RGMII_RD0 C24
J3.81 CPU_RGMII_RD1_CONN CPU.RGMII_RD1 B23
J3.83 CPU_RGMII_RD2_CONN CPU.RGMII_RD2 B24
J3.85 CPU_RGMII_RD3_CONN CPU.RGMII_RD3 D23
J3.87 CPU_RGMII_RX_CTL_CONN CPU.RGMII_RX_CTL D22
J3.89 DGND DGND
J3.91 ETH0_CLK125_NDO LAN.CLK125_NDO 41
J3.93 DGND DGND
J3.95 ETH0_INTN LAN.INT_N/PME_N2 38
J3.97 ENET_TX_EN/GPIO1_IO28 CPU.ENET_TX_EN V21
J3.99 TAMPER CPU.TAMPER E11
J3.101 ENET_REF_CLK//VDDCORE CPU.ENET_REF_CLK V22
J3.103 ENET_RX_ER//VDDSOC CPU.ENET_RX_ER W23
J3.105 ENET_RXD0//DDR_1V5 CPU.ENET_RXD0 W21
J3.107 ENET_RXD1 CPU.ENET_RXD1 W22
J3.109 ENET_TXD0//BB_3.3V/2.5V CPU.ENET_TXD0 U20
J3.111 ENET_TXD1//1V2_ETH CPU.ENET_TXD1 W20
J3.113 KEY_COL4//ENET_CRS_DV//VDDHIGH_VPH CPU.KEY_COL4 T6
J3.115 KEY_ROW4//VDDSOC_CAP CPU.KEY_ROW4 V5
J3.117 WDT_WDI//VDDPU WDT.WDI 1
J3.119 VDD_ARM23_CAP//VGEN4_1V8
J3.121 VDD_ARM01_CAP//VGEN5_2V8//VDD_VBUS_CAP
J3.123 VDD_SNVS_CAP//VGEN3_2V5//NVCC_PLL_OUT
J3.125 VGEN1
J3.127 VGEN2
J3.129 VGEN6
J3.131 SW4_XV/1.8V
J3.133 PMIC_SWBST_SUPPLY
J3.135 PMIC_SWBST_SUPPLY
J3.137 PMIC_SWBST_SUPPLY
J3.139 DGND DGND

J3 even pins (2 to 140)[edit | edit source]

Pin Pin Name Internal Connections Ball/pin #
J3.2 DGND DGND
J3.4 CSI_CLK0M CPU.CSI_CLK0M F4
J3.6 CSI_CLK0P CPU.CSI_CLK0P F3
J3.8 DGND DGND
J3.10 CSI_D0M CPU.CSI_D0M E4
J3.12 CSI_D0P CPU.CSI_D0P E3
J3.14 DGND DGND
J3.16 CSI_D1M CPU.CSI_D1M D1
J3.18 CSI_D1P CPU.CSI_D1P D2
J3.20 DGND DGND
J3.22 CSI_D2M CPU.CSI_D2M E1
J3.24 CSI_D2P CPU.CSI_D2P E2
J3.26 DGND DGND
J3.28 CSI_D3M CPU.CSI_D3M F2
J3.30 CSI_D3P CPU.CSI_D3P F1
J3.32 DGND DGND
J3.34 DSI_CLK0M CPU.DSI_CLK0M H3
J3.36 DSI_CLK0P CPU.DSI_CLK0P H4
J3.38 DGND DGND
J3.40 DSI_D0M CPU.DSI_D0M G2
J3.42 DSI_DOP CPU.DSI_DOP G1
J3.44 DGND DGND
J3.46 DSI_D1M CPU.DSI_D1M H2
J3.48 DSI_D1P CPU.DSI_D1P H1
J3.50 DGND DGND
J3.52 LVDS1_TX0_N CPU.LVDS1_TX0_N Y1
J3.54 LVDS1_TX0_P CPU.LVDS1_TX0_P Y2
J3.56 DGND DGND
J3.58 LVDS1_TX1_N CPU.LVDS1_TX1_N AA2
J3.60 LVDS1_TX1_P CPU.LVDS1_TX1_P AA1
J3.62 DGND DGND
J3.64 LVDS1_TX2_N CPU.LVDS1_TX2_N AB1
J3.66 LVDS1_TX2_P CPU.LVDS1_TX2_P AB2
J3.68 DGND DGND
J3.70 LVDS1_CLK_N CPU.LVDS1_CLK_N Y3
J3.72 LVDS1_CLK_P CPU.LVDS1_CLK_P Y4
J3.74 DGND DGND
J3.76 LVDS1_TX3_N CPU.LVDS1_TX3_N AA3
J3.78 LVDS1_TX3_P CPU.LVDS1_TX3_P AA4
J3.80 DGND DGND
J3.82 HDMI_CLKN CPU.HDMI_CLKN J5
J3.84 HDMI_CLKP CPU.HDMI_CLKP J6
J3.86 DGND DGND
J3.88 HDMI_D0N CPU.HDMI_D0N K5
J3.90 HDMI_D0P CPU.HDMI_D0P K6
J3.92 DGND DGND
J3.94 HDMI_D1N CPU.HDMI_D1N J3
J3.96 HDMI_D1P CPU.HDMI_D1P J4
J3.98 DGND DGND
J3.100 HDMI_D2N CPU.HDMI_D2N K3
J3.102 HDMI_D2P CPU.HDMI_D2P K4
J3.104 DGND DGND
J3.106 HDMI_CEC_IN CPU.HDMI_DDCCEC K2
J3.108 HDMI_HPD CPU.HDMI_HPD K1
J3.110 DGND DGND
J3.112 CLK1_N CPU.CLK1_N C7
J3.114 CLK1_P CPU.CLK1_P D7
J3.116 DGND DGND
J3.118 CLK2_N CPU.CLK2_N C5
J3.120 CLK2_P CPU.CLK2_P D5
J3.122 DGND DGND
J3.124 PCIE_RXN CPU.PCIE_RXN B1
J3.126 PCIE_RXP CPU.PCIE_RXP B2
J3.128 DGND DGND
J3.130 PCIE_TXN CPU.PCIE_TXN A3
J3.132 PCIE_TXP CPU.PCIE_TXP B3
J3.134 DGND DGND
J3.136 PMIC_5V
J3.138 PMIC_5V
J3.140 DGND DGND
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