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→Pin Mux Configuration in u-boot
{{Applies To U-Boot}}
{{InfoBoxBottom}}
{{WarningMessage|text=Please note that pin mux configuration is a very critical step. Wrong configuration may lead to system instability, side effects or even damage the hardware permanently}}
=== Introduction ===
Software installation and generic usage documentation is available on [http://processors.wiki.ti.com/index.php/Pin_Mux_Utility_for_ARM_MPU_Processors this TI wiki page]
Pin Mux Utility also warn the user if there's a conflict in mux usage (e.g. the same pin configured for two function) and does not allow to export the source code when this kind of problems arise. Please take a look, for example, at [[Additional UART on Linux (Naon)]] article for a step-by-step guide in how to change pin mux configuration and how to fix conflicts.
[[File:UART2 Pin Mux Configuration 3.png|frame|400px|center|An example of Pin Mux Utility with mux conflic]]
=== Pin Mux Configuration in u-boot ===
Due the fact the correct configuration of pin mux usually should be applied as soon as possible and that's better if pin mux is done is only one place, Dave '''DAVE Embedded Systems''' choose to move all its initialization inside the startup code of [[:Category:U-Boot|U-Boot]]
Changing default pin mux configuration is just a matter of:
# open TI Pin Mux configuration
# load the Dave provided Naon default configurationprovided by '''DAVE Embedded Systems'''
# change the mux as needed
# export the generated source code into the [[:Category:U-Boot|U-Boot]] source tree
To update the default pin mux configuration with your changes just overwrite the <code>board/dave/naon/pinmux.h</code> file inside the U-Boot source tree with the generated one.
Please also note that, inside pinmux.h, user should change:
<cpp>
#define MUX_EVM() \
MUX_VAL(PINCNTL1, (IEN | IPU | FCN1 )) /* SD1_CLK */\
MUX_VAL(PINCNTL2, (IEN | IPU | FCN1 )) /* SD1_CMD_MUX0 */\
MUX_VAL(PINCNTL3, (IEN | IPU | FCN1 )) /* SD1_DAT[0] */\
</cpp>
into
<cpp>
#define MUX_NAON() \
MUX_VAL(PINCNTL1, (IEN | IPU | FCN1 )) /* SD1_CLK */\
MUX_VAL(PINCNTL2, (IEN | IPU | FCN1 )) /* SD1_CMD_MUX0 */\
MUX_VAL(PINCNTL3, (IEN | IPU | FCN1 )) /* SD1_DAT[0] */\
</cpp>
Before building and installing the new binaries we suggest to take a look at the [[wikipedia:Diff|diff]] between the original pinmux.h and the generated one. The changed should be restricted only on the user chosen pins
<diff>
diff --git a/board/dave/naon/pinmux.h b/board/dave/naon/pinmux.h
index c1fccd6..0e6b2e2 100644
--- a/board/dave/naon/pinmux.h
+++ b/board/dave/naon/pinmux.h
@@ -208,8 +208,8 @@ MUX_VAL(PINCNTL168, (IEN | IPU | DISABLED )) /* safe_mode */\
MUX_VAL(PINCNTL169, (IEN | IPD | DISABLED )) /* safe_mode */\
MUX_VAL(PINCNTL170, (IEN | IPD | DISABLED )) /* safe_mode */\
MUX_VAL(PINCNTL171, (IEN | IPD | DISABLED )) /* safe_mode */\
-MUX_VAL(PINCNTL172, (IEN | IPD | DISABLED )) /* safe_mode */\
-MUX_VAL(PINCNTL173, (IEN | IPU | DISABLED )) /* safe_mode */\
+MUX_VAL(PINCNTL172, (IDIS | IPD | FCN6 )) /* UART2_RXD_MUX0 */\
+MUX_VAL(PINCNTL173, (IDIS | IPD | FCN6 )) /* UART2_TXD_MUX1 */\
MUX_VAL(PINCNTL174, (IEN | IPD | DISABLED )) /* safe_mode */\
MUX_VAL(PINCNTL175, (IEN | IPD | FCN1 )) /* VOUT[0]_FLD_MUX1 */\
MUX_VAL(PINCNTL176, (IEN | IPD | FCN1 )) /* VOUT[0]_CLK */\
</diff>
{{Board Specific Information|text=To avoid timestamp problems and broken dependency, before building U-Boot we suggest to run '''u-boot_clean''' target:
</pre>
}}
{{Board Specific Information|text=Please note that, for NELK < 2.0.0, pin mux configuration is applied in both U-Boot stage (1st and 2nd). When changing pin mux configuration for your custom board, please be sure to update both binaries}}
=== Multiple Pin Mux Support ===
{{Board Specific Information|text=This paragraph applies to [[Naon Embedded Linux Kit (NELK)|NELK]] 2.0.0 or above}}
To allow greater flexibility, starting from u-boot released with [[Naon Embedded Linux Kit (NELK)|NELK]] 2.0.0 user can choose which pin mux to use by setting the '''naon_host''' U-Boot environment variable.
If this variable is empty or not correctly configured, U-Boot will warn the user and it does not apply any pin mux configuration (apart the default one configured by 1st stage).
<pre class="board-terminal">
...
## Starting application at 0x81000000 ...
U-Boot 2010.06-00011-gd371eb4 (Apr 22 2013 - 12:17:53) [nelk-4.0.0-Naon]
TI8148-GP rev 2.1
ARM clk: 600MHz
DDR clk: 400MHz
L3 clk: 200MHz
DSS clk: 200MHz
IVA clk: 266MHz
ISS clk: 400MHz
DSP clk: 500MHz
I2C: ready
DRAM: 512 MiB
NAND: HW ECC BCH8 Selected
1024 MiB
MMC: OMAP SD/MMC: 0
*** Warning - bad CRC, using default environment
WARNING!! no valid pin mux defined, please configure 'naon_host'
environment variable to the correct value, save the environment
and reboot or some peripheral may not work correctly
Net: <ethaddr> not set. Reading from E-fuse
Detected MACID:00:17:EB:52:6A:8A
cpsw
Hit any key to stop autoboot: 0
NAON#
</pre>
In this case, many peripheral will not work correctly, but the user is safe to plug the [[Category:Naon|Naon]] module in any board, due the fact that all pin are muxed in safe mode.
To configure, e.g., for [[Category:NaonEVB-Mid|NaonEVB-Mid]] the user should set the ''naon_host'' environment variable accordingly:
<pre class="board-terminal">
NAON#setenv naon_host evb_mid
NAON#saveenv
Saving Environment to SPI Flash...
Erasing SPI flash...Writing to SPI flash...done
</pre>
{{Board Specific Information|text=Please note that pin mux is applied only at boot time, for this reason, after configuring the environment variable, the user should reset the board to apply the settings.}}
<pre class="board-terminal">
U-Boot 2010.06-00011-gd371eb4 (Apr 22 2013 - 12:17:17) [nelk-4.0.0-Naon-min]
TI8148-GP rev 2.1
ARM clk: 600MHz
DDR clk: 400MHz
L3 clk: 200MHz
DSS clk: 200MHz
IVA clk: 266MHz
ISS clk: 400MHz
DSP clk: 500MHz
DRAM: 512 MiB
Using default environment
Hit any key to stop autoboot: 0
8192 KiB AT45DB642D at 0:0 is now current device
## Starting application at 0x81000000 ...
U-Boot 2010.06-00011-gd371eb4 (Apr 22 2013 - 12:17:53) [nelk-4.0.0-Naon]
TI8148-GP rev 2.1
ARM clk: 600MHz
DDR clk: 400MHz
L3 clk: 200MHz
DSS clk: 200MHz
IVA clk: 266MHz
ISS clk: 400MHz
DSP clk: 500MHz
I2C: ready
DRAM: 512 MiB
NAND: HW ECC BCH8 Selected
1024 MiB
MMC: OMAP SD/MMC: 0
MUX: configuring for evb_mid
Net: Detected MACID:00:17:EB:52:6A:8A
cpsw
NAON#
</pre>