PL initialization signals (Bora/BoraX/BoraLite)
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This page provides information about the Programmable Logic (PL) initialization signals: PROGRAM_B, INIT_B, and DONE.
Please refer to Zynq Technical Reference Manual UG-585 for more information about usage and configuration of initialization circuit and signals.
As described in Table 6-24: PL Initialization Signals of Zynq-7000 SoC Technical Reference Manual (UG585), the user can initialize the PL using these signals.
BORA, BORAX, and BORALite SOM are configured in the following way:
- PROGRAM_B has an internal 10kΩ pull-up to VCCO_0 as indicated on Xilinx AR#56272
- INIT_B has no pull-up/down
- DONE has no pull-up/down. It does not require any external pull-up or pull-down but can be used for connecting a user led for a configuration completed indication (see for example BoraXEVB schematics).
External pull-ups[edit | edit source]
- PROGRAM_B: UG-585 indicates to use a 4.7kΩ pull-up resistor for this signal. This value was not known when the Xilinx Zynq 7000 family was released. Nevertheless, an external pull-up to a 3.3V controlled power domain can be put in parallel with the internal 10kΩ resistor to get a stronger pull-up.
- INIT_B: for using this signal as PL initializing signal Low-to-High transition, place an external pull-up to a 3.3V controlled power domain.
"3.3V controlled power domain" means that this domain has to be designed in order to meet the power sequences described here. Typically, this is achieved by using a cheap power switch that is enabled by the BOARD_PGOOD signal as illustrated in the following example:
Please, take into account that a similar switch is used on the SOM to generate the VCCO_0 voltage. The input of that switch is connected to the 3.3V rail used to power the SOM itself. Also, that switch is configured in order to have a 654μs delay. The external switch shown in the picture does not have to enable before the internal switch. Thus, its delay has not to be less than 654μs.
