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PL initialization signals (Bora/BoraX/BoraLite)

613 bytes removed, 15:19, 21 December 2020
→‎External pull-ups
= External pull-ups =
* PROGRAM_B: UG-585 indicates to use a 4.7kΩ pull-up resistor for this signal. This value was not known when the Xilinx Zynq 7000 family was released. Nevertheless, to date, no issues have been reported although this pull'up a little bit weaker. In any case, an external pull-up to a 3.3V controlled power domain can be put in parallel with the internal 10kΩ resistor to get a stronger pull-up. For more details, please contact [mailto:helpdesk@dave.eu the technical support].
* INIT_B: for using this signal as ''PL initializing signal Low-to-High transition'', place an external pull-up to a 3.3V controlled power domain.
 
"3.3V controlled power domain" means that this domain has to be designed in order to meet the power sequences described [[Power (Bora/BoraLite)|here]]. Typically, this is achieved by using a cheap power switch that is enabled by the BOARD_PGOOD signal as illustrated in the following example:
 
 
[[File:BORA_BOARD_PGOOD_3V3.png|center|thumb|3.3V power rail controlled via the BOARD_PGOOD signal]]
 
 
Please, take into account that a similar switch is used on the SOM to generate the VCCO_0 voltage. The input of that switch is connected to the 3.3V rail used to power the SOM itself. Also, that switch is configured in order to have a 654μs delay. The external switch shown in the picture does not have to enable before the internal switch. Thus, its delay has not to be less than 654μs.
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