PL initialization signals (Bora/BoraX/BoraLite)

Info Box Applies to Bora Applies to BORA Xpress Applies to BORA Lite

This page provides information about the Programmable Logic (PL) initialization signals: PROGRAM_B, INIT_B, and DONE.

Please refer to Zynq Technical Reference Manual UG-585 for more information about usage and configuration of initialization circuit and signals.

As described in Table 6-24: PL Initialization Signals of Zynq-7000 SoC Technical Reference Manual (UG585), the user can initialize the PL using these signals.

BORA, BORAX, and BORALite SOM are configured in the following way:

• PROGRAM_B has an internal 10kΩ pull-up to VCCO_0 as indicated on Xilinx AR#56272
• INIT_B has no pull-up/down
• DONE has no pull-up/down. It does not require any external pull-up or pull-down but can be used for connecting a user led for a configuration completed indication (see for example BoraXEVB schematics).

External pull-ups

• PROGRAM_B: for a stronger pull-up, as indicated in the UG-585, place an external pull-up to a 3.3V controlled power domain in order to put it in parallel with the internal 10kΩ pull-up.
• INIT_B: for using this signal as PL initializing signal Low-to-High transition, place an external pull-up to a 3.3V controlled power domain.

"3.3V controlled power domain" means that this domain has to be designed in order to meet the power sequences described here. Typically, this is achieved by using a cheap power switch that is enabled by the BOARD_PGOOD signal as illustrated in the following example:

File:BORA BOARD PGOOD 3V3.png

3.3V power rail controlled via the BOARD_PGOOD signal

Please, take into account that a similar switch is used on the SOM to generate the VCCO_0 voltage. The input of that switch is connected to the 3.3V rail used to power the SOM itself. Also, that switch is configured in order to have a 654μs delay. Thus, the external switch shown in the picture does not have to enable before the internal switch. In other words, its delay has not to be less than 654μs.