Bureaucrats, dave_user, Administrators
4,650
edits
Changes
no edit summary
{{InfoBoxBottom}}
Please refer to [https://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf#page=218 Zynq Technical Reference Manual UG-585] for more information about usage and configuration of initialization circuit and signals.
As written described in UG-585 ''the Table 6-24: PL Initialization Signals'' of ''Zynq-7000 SoC Technical Reference Manual (UG585)'', the user can initialize the PL using the these signals.
BORA, BORAX, and BORALite SOM are configured in the following way:
* PROGRAM_B has an internal 10kΩ pull-up to VCCO_0 as indicated on Xilinx [https://www.xilinx.com/support/answers/56272.html AR#56272]
* INIT_B has no pull-up/down
* PROGRAM_B: for a stronger pull-up, as indicated in the UG-585, place an external pull-up to a 3.3V controlled power domain in order to put it in parallel with the internal 10kΩ pull-up.
* INIT_B: for using this signal as ''PL initializing signal Low-to-High transition'', place an external pull-up to a 3.3V controlled power domain.
"3.3V controlled power domain" means that this rail domain has to be designed in order to meet the power sequences described [[Power (Bora/BoraLite)|here]]. UsuallyTypically, this is achieved by using a cheap power switch that is enabled by the BOARD_PGOOD signal as illustrated in the following example:
