Difference between revisions of "PL initialization signals (Bora/BoraX/BoraLite)"
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= Introduction = | = Introduction = | ||
| − | This page provides | + | This page provides information about the PL initialization signals: PROGRAM_B, INIT_B, and DONE. |
= PL Logic = | = PL Logic = | ||
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* PROGRAM_B has an internal 10kΩ pull-up to VCCO_0 as indicated on Xilinx [https://www.xilinx.com/support/answers/56272.html AR#56272] | * PROGRAM_B has an internal 10kΩ pull-up to VCCO_0 as indicated on Xilinx [https://www.xilinx.com/support/answers/56272.html AR#56272] | ||
* INIT_B has no pull-up/down | * INIT_B has no pull-up/down | ||
| − | * DONE has no pull-up/down. It does not require | + | * DONE has no pull-up/down. It does not require any external pull-up or pull-down but can be used for connecting a user led for a configuration completed indication (see for example [https://mirror.dave.eu/bora/hw/BoraXEVB/S-EVBBX0000C0R-1.6.1_color.pdf#page=4 BoraXEVB schematics]). |
= External pull-ups = | = External pull-ups = | ||
* PROGRAM_B: for a stronger pull-up, as indicated in the UG-585, place an external pull-up to a 3.3V controlled power domain in order to put it in parallel with the internal 10kΩ pull-up. | * PROGRAM_B: for a stronger pull-up, as indicated in the UG-585, place an external pull-up to a 3.3V controlled power domain in order to put it in parallel with the internal 10kΩ pull-up. | ||
* INIT_B: for using this signal as ''PL initializing signal Low-to-High transition'', place an external pull-up to a 3.3V controlled power domain. | * INIT_B: for using this signal as ''PL initializing signal Low-to-High transition'', place an external pull-up to a 3.3V controlled power domain. | ||
| − | "3.3V controlled power domain" means that this rail has to designed in order to meet the power sequences described [[Power (Bora/BoraLite)|here]]. | + | "3.3V controlled power domain" means that this rail has to be designed in order to meet the power sequences described [[Power (Bora/BoraLite)|here]]. Usually, this is achieved by using a cheap power switch that is enabled by the BOARD_PGOOD signal as illustrated in the following example: |
| − | |||
| − | + | [[File:BORA_BOARD_PGOOD_3V3.png|center|thumb|3.3V power rail controlled via the BOARD_PGOOD signal]] | |
| − | |||
| − | + | Please, take into account that a similar switch is used on the SOM to generate the VCCO_0 voltage on the SOM. The input of that switch is connected to the 3.3V rail used to power the SOM itself. This switch is configured in order to have a 654us delay. Thus, the external switch shown in the picture does not have to enable before the internal switch. In other words, its delay has not to be less than 654us. | |
| − | |||
| − | Please, take into account that a similar | ||
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Introduction[edit | edit source]
This page provides information about the PL initialization signals: PROGRAM_B, INIT_B, and DONE.
PL Logic[edit | edit source]
Please refer to Zynq Technical Reference Manual UG-585 for more information about usage and configuration of initialization circuit and signals.
As written in UG-585 the Table 6-24: PL Initialization Signals, the user can initialize the PL using the signals.
BORA, BORAX, and BORALite SOM are configured in the following way:
- PROGRAM_B has an internal 10kΩ pull-up to VCCO_0 as indicated on Xilinx AR#56272
- INIT_B has no pull-up/down
- DONE has no pull-up/down. It does not require any external pull-up or pull-down but can be used for connecting a user led for a configuration completed indication (see for example BoraXEVB schematics).
External pull-ups[edit | edit source]
- PROGRAM_B: for a stronger pull-up, as indicated in the UG-585, place an external pull-up to a 3.3V controlled power domain in order to put it in parallel with the internal 10kΩ pull-up.
- INIT_B: for using this signal as PL initializing signal Low-to-High transition, place an external pull-up to a 3.3V controlled power domain.
"3.3V controlled power domain" means that this rail has to be designed in order to meet the power sequences described here. Usually, this is achieved by using a cheap power switch that is enabled by the BOARD_PGOOD signal as illustrated in the following example:
File:BORA BOARD PGOOD 3V3.png
3.3V power rail controlled via the BOARD_PGOOD signal
Please, take into account that a similar switch is used on the SOM to generate the VCCO_0 voltage on the SOM. The input of that switch is connected to the 3.3V rail used to power the SOM itself. This switch is configured in order to have a 654us delay. Thus, the external switch shown in the picture does not have to enable before the internal switch. In other words, its delay has not to be less than 654us.
