Difference between revisions of "PL initialization signals (Bora/BoraX/BoraLite)"
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= Introduction = | = Introduction = | ||
| − | This page provides the information about the PL initialization signals: PROGRAM_B, INIT_B, DONE | + | This page provides the information about the PL initialization signals: PROGRAM_B, INIT_B, and DONE |
= PL Logic = | = PL Logic = | ||
| Line 15: | Line 15: | ||
As written in UG-585 ''the Table 6-24: PL Initialization Signals'', the user can initialize the PL using the signals. | As written in UG-585 ''the Table 6-24: PL Initialization Signals'', the user can initialize the PL using the signals. | ||
| − | BORA, BORAX and BORALite SOM are configured in the following way: | + | BORA, BORAX, and BORALite SOM are configured in the following way: |
| − | * PROGRAM_B has an internal | + | * PROGRAM_B has an internal 10kΩ pull-up to VCCO_0 as indicated on Xilinx [https://www.xilinx.com/support/answers/56272.html AR#56272] |
| − | * INIT_B | + | * INIT_B has no pull-up/down |
| − | * DONE does not require and external pull-up or pull-down but can be used for connecting a user led for a configuration completed indication (see for example [https://mirror.dave.eu/bora/hw/BoraXEVB/S-EVBBX0000C0R-1.6.1_color.pdf#page=4 BoraXEVB schematics]) | + | * DONE has no pull-up/down. It does not require and external pull-up or pull-down but can be used for connecting a user led for a configuration completed indication (see for example [https://mirror.dave.eu/bora/hw/BoraXEVB/S-EVBBX0000C0R-1.6.1_color.pdf#page=4 BoraXEVB schematics]). |
= External pull-ups = | = External pull-ups = | ||
| − | * PROGRAM_B: for | + | * PROGRAM_B: for a stronger pull-up, as indicated in the UG-585, place an external pull-up to a 3.3V controlled power domain in order to put it in parallel with the internal 10kΩ pull-up. |
| − | * INIT_B: for using this signal as ''PL initializing signal Low-to-High transition'', place an external pull-up to a | + | * INIT_B: for using this signal as ''PL initializing signal Low-to-High transition'', place an external pull-up to a 3.3V controlled power domain. |
| + | "3.3V controlled power domain" means that this rail has to designed in order to meet the power sequences described [[Power (Bora/BoraLite)|here]]. For this purpose, the BOARD_PGOOD signal can be used as illustrated in the following example: | ||
== 3V3 on Carrier board == | == 3V3 on Carrier board == | ||
Revision as of 15:25, 14 December 2020
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Introduction[edit | edit source]
This page provides the information about the PL initialization signals: PROGRAM_B, INIT_B, and DONE
PL Logic[edit | edit source]
Please refer to Zynq Technical Reference Manual UG-585 for more information about usage and configuration of initialization circuit and signals.
As written in UG-585 the Table 6-24: PL Initialization Signals, the user can initialize the PL using the signals.
BORA, BORAX, and BORALite SOM are configured in the following way:
- PROGRAM_B has an internal 10kΩ pull-up to VCCO_0 as indicated on Xilinx AR#56272
- INIT_B has no pull-up/down
- DONE has no pull-up/down. It does not require and external pull-up or pull-down but can be used for connecting a user led for a configuration completed indication (see for example BoraXEVB schematics).
External pull-ups[edit | edit source]
- PROGRAM_B: for a stronger pull-up, as indicated in the UG-585, place an external pull-up to a 3.3V controlled power domain in order to put it in parallel with the internal 10kΩ pull-up.
- INIT_B: for using this signal as PL initializing signal Low-to-High transition, place an external pull-up to a 3.3V controlled power domain.
"3.3V controlled power domain" means that this rail has to designed in order to meet the power sequences described here. For this purpose, the BOARD_PGOOD signal can be used as illustrated in the following example:
3V3 on Carrier board[edit | edit source]
Attention: the 3V3 Carrier power domain, has to be driven and controlled via BOARD_PGOOD signal as indicated on Power page
A controlled switch can be placed in the Carrier board following the schematics example here below:
Please, take into account that a similar internal switch (from 3V3_VIN to 3V3 used by SOM's internal circuit) has a 654 us switch delay.
