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== PL initialization signals ==This page provides information about the Programmable Logic =(PL) initialization signals: PROGRAM_B, INIT_B, and DONE.
Please refer to [https://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf#page=218 Zynq Technical Reference Manual UG-585] for more information about usage and configuration of initialization circuit and signals.
As written described in UG-585 ''the Table 6-24: PL Initialization Signals'' of ''Zynq-7000 SoC Technical Reference Manual (UG585)'', the user can initialize the PL using the these signals.
BORA, BORAX, and BORALite SOM are configured in the following way:
* PROGRAM_B has an internal 10kΩ pull-up to VCCO_0 as indicated on Xilinx [https://www.xilinx.com/support/answers/56272.html AR#56272]
* INIT_B has no pull-up/down
* DONE has no pull-up/down. It does not require and any external pull-up or pull-down but can be used for connecting a user led for a configuration completed indication (see for example [https://mirror.dave.eu/bora/hw/BoraXEVB/S-EVBBX0000C0R-1.6.1_color.pdf#page=4 BoraXEVB schematics]).
=== External pull-ups ===* PROGRAM_B: for UG-585 indicates to use a stronger 4.7kΩ pull-upresistor for this signal. This value was not known when the Xilinx Zynq 7000 family was released. Nevertheless, to date, as indicated in the UGno issues have been reported although this pull-585up is a little bit weaker. In any case, place an external pull-up to a 3.3V controlled power domain in order to can be put it in parallel with the internal 10kΩ resistor to get a stronger pull-up. For more details, please contact [mailto:helpdesk@dave.eu the technical support].
* INIT_B: for using this signal as ''PL initializing signal Low-to-High transition'', place an external pull-up to a 3.3V controlled power domain.