Changes

JTAG signals are routed to a dedicated connector (J2) on the BORA Lite PCB. The connector is placed on the top side of the PCB, at the upper-right corner (please see the picture below).

== J2 - Connector's pinout ==

For more details please refer to Table 2-4 on [http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf 7 Series FPGAs Configuration]

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|10 || 3V3 || - || 3.3VIN enabled with BOARD_PGOOD

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