Difference between revisions of "On board JTAG connector (BoraLite)"
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| − | == | + | __FORCETOC__ |
| + | |||
| + | == On board JTAG connector== | ||
JTAG signals are routed to a dedicated connector (J2) on the BORA Lite PCB. The connector is placed on the top side of the PCB, at the upper-right corner (please see the picture below). | JTAG signals are routed to a dedicated connector (J2) on the BORA Lite PCB. The connector is placed on the top side of the PCB, at the upper-right corner (please see the picture below). | ||
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[[File:BORAlite-jtag-conn1.png|500px|frameless|border]] | [[File:BORAlite-jtag-conn1.png|500px|frameless|border]] | ||
| − | == J2 - Connector's pinout == | + | === J2 - Connector's pinout === |
J2 footprint mates with Samtec FSI-110-03-G-S connector. The following table reports the connector's pinout: | J2 footprint mates with Samtec FSI-110-03-G-S connector. The following table reports the connector's pinout: | ||
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|5 || JTAG_TDI || - || - | |5 || JTAG_TDI || - || - | ||
|- | |- | ||
| − | |6 || FPGA_INIT_B || - || | + | |6 || FPGA_INIT_B || - || For further details, please refer to [[PL_initialization_signals_(Bora/BoraX/BoraLite) | PL initialization signals]] |
| − | For | ||
|- | |- | ||
| − | |7 || FPGA_PROGRAM_B || - || | + | |7 || FPGA_PROGRAM_B || - || For further details, please refer to [[PL_initialization_signals_(Bora/BoraX/BoraLite) | PL initialization signals]] |
| − | + | (10 kΩ pull-up resistor is already mounted on BORA module) | |
| − | For | ||
|- | |- | ||
| − | |8 || FPGA_DONE || - || | + | |8 || FPGA_DONE || - || For further details, please refer to [[PL_initialization_signals_(Bora/BoraX/BoraLite) | PL initialization signals]] |
| − | |||
| − | For | ||
|- | |- | ||
| − | |9 || N.C. || - || | + | |9 || D.N.C. || - || RESERVED |
|- | |- | ||
|10 || 3V3 || - || 3.3VIN enabled with BOARD_PGOOD | |10 || 3V3 || - || 3.3VIN enabled with BOARD_PGOOD | ||
|- | |- | ||
|} | |} | ||
Revision as of 15:53, 21 December 2020
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On board JTAG connector[edit | edit source]
JTAG signals are routed to a dedicated connector (J2) on the BORA Lite PCB. The connector is placed on the top side of the PCB, at the upper-right corner (please see the picture below).
J2 - Connector's pinout[edit | edit source]
J2 footprint mates with Samtec FSI-110-03-G-S connector. The following table reports the connector's pinout:
| Pin# | Pin name | Function | Notes |
|---|---|---|---|
| 1 | DGND | - | - |
| 2 | JTAG_TCK | - | - |
| 3 | JTAG_TMS | - | - |
| 4 | JTAG_TDO | - | - |
| 5 | JTAG_TDI | - | - |
| 6 | FPGA_INIT_B | - | For further details, please refer to PL initialization signals |
| 7 | FPGA_PROGRAM_B | - | For further details, please refer to PL initialization signals
(10 kΩ pull-up resistor is already mounted on BORA module) |
| 8 | FPGA_DONE | - | For further details, please refer to PL initialization signals |
| 9 | D.N.C. | - | RESERVED |
| 10 | 3V3 | - | 3.3VIN enabled with BOARD_PGOOD |
