View source for On board JTAG connector (BoraLite)

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== On board JTAG connector==

JTAG signals are routed to a dedicated connector (J2) on the BORA Lite PCB. The connector is placed on the top side of the PCB, at the upper-right corner (please see the picture below).

[[File:BORAlite-jtag-conn1.png|500px|frameless|border]]

=== J2 - Connector's pinout ===

J2 footprint mates with Samtec FSI-110-03-G-S connector. The following table reports the connector's pinout: 

{| class="wikitable" 
|-
!Pin# 
!Pin name
!Function
!Notes
|-
|1 || DGND || - || -
|-
|2 || JTAG_TCK || - || -
|-
|3 || JTAG_TMS || - || -
|-
|4 || JTAG_TDO || - || -
|-
|5 || JTAG_TDI || - || -
|-
|6 || FPGA_INIT_B || - || For further details, please refer to [[PL_initialization_signals_(Bora/BoraX/BoraLite) | PL initialization signals]]
|-
|7 || FPGA_PROGRAM_B || - || For further details, please refer to [[PL_initialization_signals_(Bora/BoraX/BoraLite) | PL initialization signals]]
(10 kΩ pull-up resistor is already mounted on BORA module) 
|-
|8 || FPGA_DONE || - || For further details, please refer to [[PL_initialization_signals_(Bora/BoraX/BoraLite) | PL initialization signals]]
|-
|9 || D.N.C. || - || RESERVED
|-
|10 || 3V3 || - || 3.3VIN enabled with BOARD_PGOOD
|-
|}
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