Difference between revisions of "On board JTAG connector (AxelLite)"

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m (Reverted edits by U0007 (talk) to last revision by DevWikiAdmin)
(Tag: Rollback)
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== Introduction ==
 
== Introduction ==
  
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JTAG signals are routed to a dedicated connector (J2) on the BORA Lite PCB. The connector is placed on the top side of the PCB, at the upper-right corner (please see the picture below).
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JTAG signals are routed to a dedicated connector (J7) on the Axel Lite PCB. The connector is placed on the top side of the PCB, at the upper-right corner (please see the picture below).
  
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[[File:BORAlite-jtag-conn.png|500px|frameless|border]]
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[[File:Axellite-jtag-conn.png|500px|frameless|border]]
  
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== J2 - Connector's pinout ==
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== J7 - Connector's pinout ==
  
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J2 footprint mates with Samtec FSI-110-03-G-S connector. The following table reports the connector's pinout:  
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J7 footprint mates with Samtec FSI-110-03-G-S connector. The following table reports the connector's pinout:  
  
 
{| class="wikitable"  
 
{| class="wikitable"  
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|5 || JTAG_TDI || - || -
 
|5 || JTAG_TDI || - || -
 
|-
 
|-
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|6 || FPGA_INIT_B || - || Place external 4.7 kO (or stronger) pull-up resistor to BOARD_PGOOD driven +3.3V supply
+
|6 || JTAG_nTRST || - || -
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For more details please refer to Table 2-4 on [http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf 7 Series FPGAs Configuration]
 
 
|-
 
|-
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|7 || FPGA_PROGRAM_B || - || Place external 4.7 kO (or stronger) pull-up resistor to BOARD_PGOOD driven +3.3V supply
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|7 || CPU_PORn || - || -
−
 
 
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For more details please refer to Table 2-4 on [http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf 7 Series FPGAs Configuration]
 
 
|-
 
|-
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|8 || FPGA_DONE || - || Place external 300O pull-up resistor to BOARD_PGOOD driven +3.3V supply
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|8 || N.C. || - || -
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For more details please refer to Table 2-4 on [http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf 7 Series FPGAs Configuration]
 
 
|-
 
|-
 
|9 || N.C. || - || -
 
|9 || N.C. || - || -
 
|-
 
|-
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|10 || 3V3 || - || 3.3VIN enabled with BOARD_PGOOD
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|10 || JTAG_VREF || - || -
 
|-
 
|-
 
|}
 
|}

Revision as of 14:27, 15 October 2019

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Axel-lite 02.png Applies to Axel Lite

Introduction[edit | edit source]

JTAG signals are routed to a dedicated connector (J7) on the Axel Lite PCB. The connector is placed on the top side of the PCB, at the upper-right corner (please see the picture below).

Axellite-jtag-conn.png

J7 - Connector's pinout[edit | edit source]

J7 footprint mates with Samtec FSI-110-03-G-S connector. The following table reports the connector's pinout:

Pin# Pin name Function Notes
1 DGND - -
2 JTAG_TCK - -
3 JTAG_TMS - -
4 JTAG_TDO - -
5 JTAG_TDI - -
6 JTAG_nTRST - -
7 CPU_PORn - -
8 N.C. - -
9 N.C. - -
10 JTAG_VREF - -
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