ORCA SOM/ORCA Hardware/Power and Reset/Reset scheme and control signals

History
Version	Issue Date	Notes
1.0.0	Jan 2021	First release

Reset scheme and control signals

The following picture shows the simplified block diagram of reset scheme and voltage monitoring.

NVCC_VSNVS_1V8

Some signals that are related to reset circuitry are pulled-up to NVCC_VSNVS_1V8 (1.8V internal rail).

Hence it is recommended that system designer takes into account these factors in order to properly manage these signals at carrier board level.

PMIC_RST_B

EXT_RESET is internally pulled-up with a 100kΩ to NVCC_VSNVS_1V8. Connect EXT_RESET signal to GND (for example with a button or an open-collector circuit) causes the PMIC to assert its POR_B output.

When this signal is pulled low all the power supplies except for the SNVS domain will be OFF.

The RESETn will keep asserted for 250 ms after PMIC_RST_B is released, thus providing enough time for the power supplies to be completely powered down. During this time, the CPU_PORb driven by the PMIC will also keep asserted (low).

After RESETn is released, the power supplies will start to ramp up in defined sequence. When all the power supplies have reached their operating voltages, POR_B will be de-asserted, and the CPU may begin booting from reset.

PMIC_ON_REQ//VMON_RST

This pin is routed by default to the PMIC_ON_REQ internal signal. It can be optionally routed to the voltage monitor master reset to issue a reset without involving the PMIC.

The PMIC_ON_REQ signal is driven by iMX8MPlus SoC to place the system in power down mode.

CPU_PORn

PMIC can assert this active-low signal. Other internal IC, such as ethernet PHY or boot memory devices, could be connected to this signal. This guarantees that they are in a known state when reset signal is released.

CPU_ONOFF

CPU_ONOFF is internally pulled-up with a 100kΩ to NVCC_VSNVS_1V8. This input signal is connected directly to the ONOFF input of the CPU.

BOARD_PGOOD

BOARD_PGOOD is the output of the voltage monitor on the internal NVCC_3V3 rail (I/O pins supply) and must be used as power enable for all the electronics on MITO 8M carrier board.

When the I/O pins power rail on MITO 8M is not ready (BOARD_PGOOD low) all the integrated circuits connected to the CPU must be powered off in order to avoid back-powering or other issue related to a wrong power-up sequence.

BOOT_MODE_[0-2]

BOOT_MODE_x pins can be internally pulled-up with 10kΩ to NVCC_3V3 or pulled-down with 10kΩ to DGND to provide the default boot mode. The previous block diagram shows the SD3 eMMC boot option.

To overwrite the boot configuration these pins can be pulled low or high with 1kΩ resistor, the pull-up rail has to be a 3.3V enabled by BOARD_PGOOD signal.

WDOG_B

WDOG_B is a PMIC input signal that is configured by default to generate a system reset. It is internally connected to processor's watchdog output.

Handling CPU-initiated software reset

Section not completed yet

By default, MX8 processor does not assert any external signal when it initiates a software reset sequence. Also default software reset implementation does not guarantee that all processor registers are reset properly.

For these reasons, it is strongly recommended to use a different approach that, in combination with the use of a processor's watchdog timer (WDT), provides a full hardware reset in case a software reset is issued.

This technique is implemented in DESK-MX8M-L. At software level, U-Boot and Linux kernel software reset routines make use of processor's WDT to assert the WDOG1_WDOG_B reset signal. This signal in turn is routed to GPIO1_IO02 pad (MUX mode = 1, internal connection only). At hardware level, this signal is connected to the PMIC WDOG_B input that generates a system POR.

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