<section begin="History" />

!colspan="4" style="width:100%; text-align:left"; border-bottom:solid 2px #ededed"|History

!style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Version!style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Issue Date!style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Notes

|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|X1.Y0.Z0|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|Month YearJan 2021|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|TBDFirst release

<section end="History" /><section begin="Body" />

=== NVCC_VSNVS_1V8 ===Some signals that are related to reset circuitry are pulled-up to NVCC_VSNVS_1V8 (1.8V internal rail). Hence '''it is recommended that system designer takes into account these factors in order to properly manage these signals at carrier board level.'''TBD: qui di seguito vanno inserite le sezioni che includano la descrizione dei segnali coinvolti nella fase di Reset, ad esempio:

* MRST=== PMIC_RST_B ===* POR* SNVS* SYSRST* EXT_RESET is internally pulled-up with a 100kΩ to NVCC_VSNVS_1V8.Connect EXT_RESET signal to GND (for example with a button or an open-collector circuit) causes the PMIC to assert its POR_B output..'''

=== PMIC_VSNVS ===Some signals that are related After RESETn is released, the power supplies will start to reset circuitry are pulled-ramp up to PMIC_VSNVS. This voltage is generated by PMIC PF0100's VSNVS LDO/Switch and its actual value depends on:* voltage applied to PMICS's VIN pin** in case of AxelLite this pin is connected to 3defined sequence.3VIN When all the power rail* voltage applied to PMICS's LICELL pin** in case of AxelLite this pin is connected to pin 14 of SODIMM connector (PMIC_LICELL)* PMIC's VSNVSCTL register configuration.Hence '''it is recommended that system designer takes into account these factors in order to properly manage these signals at carrier board level'''supplies have reached their operating voltages, POR_B will be de-asserted, and the CPU may begin booting from reset.

For more details please refer === PMIC_ON_REQ//VMON_RST ===This pin is routed by default to the PMIC_ON_REQ internal signal. It can be optionally routed to the voltage monitor master reset to section ''VSNVS LDO/Switch'' of ''MMPF0100 Advance Information'' documentissue a reset without involving the PMIC. The PMIC_ON_REQ signal is driven by iMX8MPlus SoC to place the system in power down mode.

The following devices can assert this active-low signal:=== CPU_ONOFF ===* PMIC* multipleCPU_ONOFF is internally pulled-voltage monitor: this device monitors critical power voltages and triggers up with a reset pulse in case any 100kΩ to NVCC_VSNVS_1V8. This input signal is connected directly to the ONOFF input of these exhibits a brownout condition the CPU.

Since SPI NOR flash can === BOARD_PGOOD ===BOARD_PGOOD is the output of the voltage monitor on the internal NVCC_3V3 rail (I/O pins supply) and must be used as boot device, CPU_PORn is connected to this device too. This guarantees it is in a known state when reset signal is releasedpower enable for all the electronics on MITO 8M carrier board.

'''By default, MX6 MX8 processor does not assert any external signal when it initiates a software reset sequence. Also default software reset implementation does not guarantee that all processor registers are reset properly'''.

''TBD'' This technique is implemented in [[DESK-iMX8MPlusMX8-L]]. At software level, U-Boot and Linux kernel software reset routines make use of processor's WDT #2 to assert the WDOG2_B reset signal. This signal in turn is routed to GPIO_1 pad (MUX mode = 1). At hardware level, this signal is AC-coupled to a 3-state output buffer (please refer to U22 chip of [[AxelEVB-Lite]] carrier board), driving PMIC_PWRON.