Difference between revisions of "ORCA SOM/ORCA Hardware/General Information/Processor and memory subsystem"
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{| class="wikitable" | | {| class="wikitable" | | ||
| align="center" style="background:#f0f0f0;" |'''Processor''' | | align="center" style="background:#f0f0f0;" |'''Processor''' | ||
| − | | align="center" style="background:#f0f0f0;" |'''i.MX8M Plus''' | + | | align="center" style="background:#f0f0f0;" |'''i.MX8M Plus Dual''' |
| + | | align="center" style="background:#f0f0f0;" |'''i.MX8M Plus Quad''' | ||
|- | |- | ||
|# Cores | |# Cores | ||
| − | |4x Arm® Cortex®-A53 <br>1x Arm® Cortex®-M7<br>1x Hi-Fi4 DSP | + | |2x Arm® Cortex®-A53<br>1x Arm® Cortex®-M7<br>1x Hi-Fi4 DSP |
| + | |4x Arm® Cortex®-A53<br>1x Arm® Cortex®-M7<br>1x Hi-Fi4 DSP | ||
|- | |- | ||
| − | |Clock | + | |Clock || colspan="2" | 1.8 GHz |
| − | |1.8 GHz | ||
|- | |- | ||
| − | |L2 | + | |L2 Cache|| colspan="2" | 512 KB |
| − | Cache | + | |- |
| − | |512 KB | + | |LPDDR4 || colspan="2" | 32 bit @ 2000 MHz<br>(LPDDR4-4000) |
| − | |- | ||
| − | |LPDDR4 | ||
| − | | 32 bit @ 2000 MHz | ||
| − | (LPDDR4-4000) | ||
|- | |- | ||
|GPU | |GPU | ||
| − | | 3D: Vivante GC 7000UL (2 Shader)<br>2D: Vivante GC520L<br> | + | | colspan="2" | 3D: Vivante GC 7000UL (2 Shader)<br>2D: Vivante GC520L<br> |
OpenGL ES 3.1<br>Vulkan<br>Open VG 1.1<br>Open CL 1.2 | OpenGL ES 3.1<br>Vulkan<br>Open VG 1.1<br>Open CL 1.2 | ||
|- | |- | ||
|VPU | |VPU | ||
| − | | 1080p60 H.265, H.264, VP9, VP8 decoder<br>1080p60 H.265, H.264 encoder | + | | colspan="2" | 1080p60 H.265, H.264, VP9, VP8 decoder<br>1080p60 H.265, H.264 encoder |
|- | |- | ||
|NPU | |NPU | ||
| − | | 2.25 TOP/s Neural Processing Unit | + | | colspan="2" | 2.25 TOP/s Neural Processing Unit |
|- | |- | ||
|Display Controller | |Display Controller | ||
| − | | Dual Channel LVDS up to 1080p60 | + | | colspan="2" | Dual Channel LVDS up to 1080p60 |
|- | |- | ||
|Video Output | |Video Output | ||
| − | | 1x HDMI 2.0a<br>1x MIPI-DSI (4-lanes) | + | | colspan="2" | 1x HDMI 2.0a<br>1x MIPI-DSI (4-lanes) |
|- | |- | ||
|Camera Input | |Camera Input | ||
| − | | colspan="2" |2x MIPI CSI (4-lanes each)<br>2x ISP | + | | colspan="2" | colspan="2" |2x MIPI CSI (4-lanes each)<br>2x ISP |
|- | |- | ||
|Ethernet | |Ethernet | ||
| − | | 2x 10/100/1000 Mbit/s controller with AVB and IEEE1588 | + | | colspan="2" | 2x 10/100/1000 Mbit/s controller with AVB and IEEE1588 |
|- | |- | ||
|PCIe | |PCIe | ||
| − | | 1x PCIe 3 (1-lane) | + | | colspan="2" | 1x PCIe 3 (1-lane) |
|- | |- | ||
|USB | |USB | ||
| − | | 2x USB 2.0/3.0 | + | | colspan="2" | 2x USB 2.0/3.0 |
|- | |- | ||
| − | |+ align="bottom" style="caption-side: bottom" | Table: i.MX8M Plus | + | |+ align="bottom" style="caption-side: bottom" | Table: i.MX8M Plus models comparison |
|} | |} | ||
Revision as of 15:05, 24 February 2021
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Contents
Processor and memory subsystem[edit | edit source]
The heart of ORCA module is composed by the following components:
- i.MX8M Plus SoC application processor
- Power supply unit
- LPDDR4 memory bank
- eMMC or NAND flash banks
- Connectors:
- 1 x 260 pins SO-DIMM edge connector with interfaces signals
This chapter shortly describes the main ORCA components.
Processor Info[edit | edit source]
| Processor | i.MX8M Plus Dual | i.MX8M Plus Quad |
| # Cores | 2x Arm® Cortex®-A53 1x Arm® Cortex®-M7 1x Hi-Fi4 DSP |
4x Arm® Cortex®-A53 1x Arm® Cortex®-M7 1x Hi-Fi4 DSP |
| Clock | 1.8 GHz | |
| L2 Cache | 512 KB | |
| LPDDR4 | 32 bit @ 2000 MHz (LPDDR4-4000) | |
| GPU | 3D: Vivante GC 7000UL (2 Shader) 2D: Vivante GC520L OpenGL ES 3.1 | |
| VPU | 1080p60 H.265, H.264, VP9, VP8 decoder 1080p60 H.265, H.264 encoder | |
| NPU | 2.25 TOP/s Neural Processing Unit | |
| Display Controller | Dual Channel LVDS up to 1080p60 | |
| Video Output | 1x HDMI 2.0a 1x MIPI-DSI (4-lanes) | |
| Camera Input | colspan="2" |2x MIPI CSI (4-lanes each) 2x ISP | |
| Ethernet | 2x 10/100/1000 Mbit/s controller with AVB and IEEE1588 | |
| PCIe | 1x PCIe 3 (1-lane) | |
| USB | 2x USB 2.0/3.0 | |
RAM memory bank[edit | edit source]
LPDD4 SDRAM memory bank is composed by 1x 32-bit width chip. The following table reports the SDRAM specifications:
| CPU connection | Multi-mode DDR controller (MMDC) |
| Size max | 8 GB |
| Width | 32 bit |
| Speed | 2000 MHz |
eMMC flash bank[edit | edit source]
On board main storage memory eMMC is connected to the SDIO3 interface and it can act as boot peripheral. The following table reports the eMMC flash specifications:
| CPU connection | SDIO3 |
| Size min | 4 GB |
| Size max | 64 GB |
| Bootable | Yes |
NAND flash bank[edit | edit source]
|
Section not completed yet |
Alternative option for main storage memory can be a 8-bit wide NAND flash connected to the CPU's Raw NAND flash controller. It can act as boot peripheral. The following table reports the NAND flash specifications:
| CPU connection | Raw NAND flash controller |
| Page size | TBD |
| Size min | TBD |
| Size max | TBD |
| Width | 8 bit |
| Chip select | TBD |
| Bootable | Yes |
Memory map[edit | edit source]
For detailed information, please refer to chapter 2 “Memory Maps” of the i.MX8M Plus Applications Processor Reference Manual
Power supply unit[edit | edit source]
ORCA embeds all the elements required for powering the unit, therefore power sequencing is self-contained and simplified. Nevertheless, power must be provided from carrier board, and therefore users should be aware of the ranges power supply can assume as well as all other parameters.
