ORCA SOM/ORCA Evaluation Kit/Interfaces and Connectors/LVDS

History
Version	Issue Date	Notes
1.0.0	Sep 2021	First release

LVDS interface

Description

The LVDS interface available on the Evaluation Kit at the connector J13

J13 is a 20x2x1.25mm DF13E-40DP-1.25V(51) Hirose header connector.

On this connector are routed two separate LVDS interfaces that can operate in dual-channel mode to drive high resolution displays.

[[File:{Template:Nome-som-EVB-LVDS-connector.png|thumb|center|500px|LVDS connector]]

Signals

The following table describes the interfaces signals:

Pin#	SOM Pin#	Pin name	Pin function	Pin Notes
1, 3	-	3V3_LCD	Power output	GPIO driven rail
7	J15.49	LVDS0_D0_N	LVDS Data 0 -
9	J15.51	LVDS0_D0_P	LVDS Data 0 +
2	J15.45	LVDS0_D1_N	LVDS Data 1 -
4	J15.47	LVDS0_D1_P	LVDS Data 1 +
13	J15.37	LVDS0_D2_N	LVDS Data 2 -
15	J15.39	LVDS0_D2_P	LVDS Data 2 +
19	J15.41	LVDS0_CLK_N	LVDS Clock -
21	J15.43	LVDS0_CLK_P	LVDS Clock +
8	J15.33	LVDS0_D3_N	LVDS Data 3 -
10	J15.35	LVDS0_D3_P	LVDS Data 3 +
5, 6, 11, 12, 17, 18, 23, 26, 29, 32, 35	-	DGND	Ground
25	J15.71	LVDS1_D0_N	LVDS Data 0 -
27	J15.73	LVDS1_D0_P	LVDS Data 0 +
31	J15.67	LVDS1_D1_N	LVDS Data 1 -
33	J15.69	LVDS1_D1_P	LVDS Data 1 +
28	J15.59	LVDS1_D2_N	LVDS Data 2 -
30	J15.61	LVDS1_D2_P	LVDS Data 2 +
34	J15.63	LVDS1_CLK_N	LVDS Clock -	Can be terminated on board for dual-channel mode
36	J15.65	LVDS1_CLK_P	LVDS Clock +
37	J15.55	LVDS1_D3_N	LVDS Data 3 -
39	J15.57	LVDS1_D3_P	LVDS Data 3 +
14, 16, 18	-	5V_LCD	Power output	GPIO driven rail
20	-	VIN_BL_AUX1	Power output	Default connected to VIN_BL. Can be connected to an external controller to generate custom rails.
22	-	VIN_BL_AUX2	Power output
24	-	VIN_BL	Power output	GPIO driven rail
38	J15.240	LCD_BKLT_PWM	PWM output	Default routed to PWM1 Can be routed to PWM2
40	J15.213	LCD_EN	GPIO

Device mapping

TODO: verify against SW implementation

• LVDS0 is mapped to /dev/fb0 device in Linux
• LVDS1 is mapped to the corresponding device driver in Linux, depending on the ldb peripheral configuration in the device tree. The default value is disabled but can be mapped to /dev/fb2 (second and independent LCD panel) or can be the second LVDS channel for a dual-channel LCD panel configuration (like a 1920x1080 DUAL LVDS channel LCD panel)

Power sequence

Most of the LCD panels has many supplies and need a specific timing to power the rails and start the the signals.

The Evaluation Kit provides GPIO controlled power rails that can be leveraged both at bootloader and kernel level to meet any specifications.

The following sections describe the available rails:

3V3_LCD

The most common voltage to supply the LCD panel internal logic. This rail is enabled by GPIO1_IO06 that is connected to J15.233

5V_LCD

The most common voltage to supply the LCD panel backlight. This rail is enabled by GPIO1_IO08 that is connected to J15.209

VIN_LCD

The voltage of this rail is the system input voltage, see Power Supply section for more details. This rail is enabled by GPIO1_IO07 that is connected to J15.225

VIN_LCD_AUX

There are two more pins to deliver higher current on the rail VIN_LCD. These two pins can be instead separately routed to the expansion connector J40.

J40 is a 6x1x2.54mm strip header connector, not mounted by default. This connector can house an external controller that generates up to 2 custom rails, controlled by GPIOs.

J40 Signals

The following table describes the interface signals:

Pin#	SOM Pin#	Pin name	Pin function	Pin Notes
1	-	VIN	Power output	This is the power supply voltage
2	J15.240	LCD_BKLT_PWM	PWM output	Default routed to PWM1 Can be routed to PWM2
3	J15.225	GPIO1_IO07	GPIO
4	-	VIN_BL_AUX2	Power input
5	-	VIN_BL_AUX1	Power input
6	-	DGND	Ground

Device usage

The display power sequence can be leveraged by a DAVE custom code that allow to set the timings both in U-boot and in Linux kernel sources.

The associated framebuffer device is accessed in Linux through the standard graphic access.

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