<section begin="History" />
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|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|Month Year
|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|TBD
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<section end="History" /><section begin="Body" />
==LVDS interface ==
''TBD: sostituire le sezioni con le informazioni sull'uso della periferica e del suo connettore''''Nell'esempio di seguito c'è la descrizione dell'interfaccia UART/console''=== Description ===
=== Description ===The LVDS interface available on the Evaluation Kit at the connector J13
The LVDS interface available on the Evaluation Kit at the J13 is a 20x2x1.25mm DF13E-40DP-1.25V(51) Hirose header connector ''TBD:Jxxx''.
''Jxx'' is a ''TBD:On this connector-type'' header connector for the RS232 are routed twoseparate LVDS interfaces that can operate in dual-wires UART3 port, used for debug purposes (bootloader and operating system serial console)channel mode to drive high resolution displays.
[[File:{{{nomeORCA-som}}-EVBEVK-LVDS-connector.png|thumb|center|500px|LVDS connector]]
===Signals ===
The following table describes the interface interfaces signals:
{| class="wikitable"
! latexfontsize="scriptsize"| Pin#! latexfontsize="scriptsize"| SOM Pin#! latexfontsize="scriptsize"| Pin name! latexfontsize="scriptsize"| Pin function! latexfontsize="scriptsize"| Pin Notes
|-
|1,2,4,6,,7,8,103
| -
| N3V3_LCD|Power output|GPIO driven rail|-|7|J15.A49|LVDS0_D0_N|LVDS Data 0 -||-|9|J15.51|LVDS0_D0_P| N.C.LVDS Data 0 +| Not connected
|-
| 32| J1J15.18945| RS232_RXLVDS0_D1_N| Receive lineLVDS Data 1 -|
|-
| 34| J1J15.18747| RS232_TXLVDS0_D1_P| Transmit lineLVDS Data 1 +|
|-
| 913|J15.37|LVDS0_D2_N|LVDS Data 2 -||-|15|J15.39|LVDS0_D2_P|LVDS Data 2 +||-|19|J15.41|LVDS0_CLK_N|LVDS Clock -||-|21|J15.43|LVDS0_CLK_P|LVDS Clock +||-|8|J15.33|LVDS0_D3_N|LVDS Data 3 -||-|10|J15.35|LVDS0_D3_P|LVDS Data 3 +||-|5, 6, 11, 12, 17, 18, 23, 26, 29, 32, 35
| -
| DGND| Ground||-|25|J15.71|LVDS1_D0_N|LVDS Data 0 -||-|27|J15.73|LVDS1_D0_P|LVDS Data 0 +||-|31|J15.67|LVDS1_D1_N|LVDS Data 1 -||-|33|J15.69|LVDS1_D1_P|LVDS Data 1 +||-|28|J15.59|LVDS1_D2_N|LVDS Data 2 -||-|30|J15.61|LVDS1_D2_P|LVDS Data 2 +||-|34|J15.63|LVDS1_CLK_N|LVDS Clock -| rowspan="2" |Can be terminated on boardfor dual-channel mode|-|36|J15.65|LVDS1_CLK_P|LVDS Clock +|-|37|J15.55|LVDS1_D3_N|LVDS Data 3 -||-|39|J15.57|LVDS1_D3_P|LVDS Data 3 +||-|14, 16, 18| -|5V_LCD|Power output|GPIO driven rail|-|20| -|VIN_BL_AUX1|Power output| rowspan="2" |Default connected to VIN_BL.Can be connected to an external controller to generate custom rails. |-|22| -|VIN_BL_AUX2|Power output|-|24| -|VIN_BL|Power output|GPIO driven rail|-|38|J15.240|LCD_BKLT_PWM|PWM output|Default routed to PWM1Can be routed to PWM2|-|40|J15.213|LCD_EN|GPIO|
|}
=== Device mapping ===
UART3 * LVDS0 is ''typically'' mapped to <code>/dev/ttymxc2fb0</code> device in Linux* LVDS1 is mapped to the corresponding device driver in Linux, depending on the <code>ldb</code> peripheral configuration in the device tree. The peripheral default value is used as ''disabled'' but can be mapped to <code>/dev/fb2</code> (second and independent LCD panel) or can be the default serial console, both second LVDS channel for a dual-channel LCD panel configuration (like a 1920x1080 DUAL LVDS channel LCD panel) === Power sequence ===Most of the LCD panels has many supplies and need a specific timing to power the rails and start the the signals. The Evaluation Kit provides GPIO controlled power rails that can be leveraged both at bootloader and kernel level to meet any specifications. The following sections describe the available rails: ==== 3V3_LCD ====The most common voltage to supply the LCD panel internal logic. This rail is enabled by <code>GPIO1_IO06</code> that is connected to J15.233 ==== 5V_LCD ====The most common voltage to supply the LCD panel backlight. This rail is enabled by <code>GPIO1_IO08</code> that is connected to J15.209 ==== VIN_LCD ====The voltage of this rail is the system input voltage, see [[ORCA SOM/ORCA Evaluation Kit/Interfaces and Connectors/Power Supply|Power Supply]] section for more details. This rail is enabled by <code>GPIO1_IO07</code> that is connected to J15.225 ==== VIN_LCD_AUX ====There are two more pins to deliver higher current on the rail VIN_LCD. These two pins can be instead separately routed to the kernelexpansion connector J40. J40 is a 6x1x2.54mm strip header connector, not mounted by default. This connector can house an external controller that generates up to 2 custom rails, controlled by GPIOs. ===== J40 Signals =====The following table describes the interface signals:{| class="wikitable" ! latexfontsize="scriptsize" | Pin#! latexfontsize="scriptsize" | SOM Pin#! latexfontsize="scriptsize" | Pin name! latexfontsize="scriptsize" | Pin function! latexfontsize="scriptsize" | Pin Notes|-|1| -|VIN|Power output|This is the power supply voltage|-|2|J15.240|LCD_BKLT_PWM|PWM output|Default routed to PWM1Can be routed to PWM2|-|3|J15.225|GPIO1_IO07|GPIO||-|4| -|VIN_BL_AUX2|Power input||-|5| -|VIN_BL_AUX1|Power input||-|6| -|DGND|Ground||}
=== Device usage ===
The display power sequence can be leveraged by a DAVE custom code that allow to set the timings both in U-boot and in Linux kernel sources.
To connect to The associated framebuffer device is accessed in Linux through the debug serial port: # connect the DB9 adapter bracket to the J22 connector on the SBCX board# connect a serial cable between DB9 connector and PC COM port through a NULL-modem cable (not provided)# start your favorite terminal emulator software on PC (eg: PuTTY); communication parameters are: 115200,N,8,1standard graphic access.
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[[Category:ORCA SOM]]