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Memory organization (Naon)

998 bytes added, 13:34, 3 May 2012
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=== Introduction ===Naon memory organization and mapping is quite complex, due to DM8148's multiprocessor nature and the availability of several memory devices on connected to the processor. This section will provide an overview of such architecture while following sections will describe in more detail memory map for each device. Please refer to [Naon_SOM#Module_overview|Naon block diagram].
Memory Map for Naon Module About system RAM, DM8148 provides two controllers. Each one can be interfaced to one SDRAM bank through a physical interface called EMIF (EMIF0 and EMIF1). EMIF0 is quite complexconnected to 32-bit DDR2 SDRAM bank (up to 512 MByte). EMIF1 is not connected to any device, due it's multiprocessor naturehence is permanently disabled.
Before start reading regarding About non-volatile memories, the following devices populate Naon module:* SPI NOR flash** connected to SPI0 port** by default acts as boot memory map in details, please take a look at generic [http** maximum size://processors.wiki.ti.com/index.php/EZSDK_Memory_Map EZSDK Memory Map] on Texas Instruments Wikiup to 64 MByte* NAND flash** connected to GPMC bus (CS0n)** optionally can act as boot memory* EEPROM** connected to I2C3 bus.
==NELK memory maps==
This section describes in detail default memories mapping configuration used in Naon Embedded Linux Kit.
=== RAM Memory Map ===
Before start reading memory map in detail, please take a look at generic [http://processors.wiki.ti.com/index.php/EZSDK_Memory_Map EZSDK Memory Map] on Texas Instruments Wiki.
RAM memory map is the most complex part of this architecture, because the user should allocate the different area used by Cortex-A8 processor (which runs the [[:Category:Linux|Linux]] OS), the two media controller (Cortex-M3, that take care of the whole video processing subsystem) and DSP.