3,260
edits
Changes
Created page with "= Memory Organization = The processor module is equipped with: * 128 or 256 MB SDRAM * up to 128 MB NOR Flash * NAND Flash (typical sizes are 128/256/512/1024 MB) The follo..."
= Memory Organization =
The processor module is equipped with:
* 128 or 256 MB SDRAM
* up to 128 MB NOR Flash
* NAND Flash (typical sizes are 128/256/512/1024 MB)
The following table shows simplified chip selects organization. This, along with memory mapping, is strictly related to bootstrap configuration thus reading of pate xxx is recommended.
AM3517/05 provides 8 chip selects. By default, chip select #0 (boot) is connected to on-board NOR flash. Therefore this device acts as boot memory. NAND flash memory is by default connected to chip select #7 . Please note that NAND flash and NOR flash chip selects can be optionally switched in order to make NAND flash the boot memory. For more information about this option, please contact technical support at support-lizard@dave.eu.
{|class="wikitable"
|-
! style="width:90px;" | Chip Select #
! style="width:90px;" | Device
! style="width:90px;" | Physical Address
! style="width:90px;" | Size
|-
| 0 (GPMC)
| on-board NOR flash
| 0x0800:0000
| 128 MB
|-
| 1 (GPMC)
| user available
| user defined
| user defined
|-
| 2 (GPMC)
| user available
| user defined
| user defined
|-
| 3 (GPMC)
| user available
| user defined
| user defined
|-
| 4 (GPMC)
| user available
| user defined
| user defined
|-
| 5 (GPMC)
| user available
| user defined
| user defined
|-
| 6 (GPMC)
| on-board CPLD
| 0x2000:0000
| 16 MB
|-
| 7 (GPMC)
| on-board NANDflash
| 0x3000:0000
| 1024 MB
|-
| 0 (SDRC)
| on-board DDR2 SDRAM
| 0x8000:0000
| 256 MB
|-
|}
The processor module is equipped with:
* 128 or 256 MB SDRAM
* up to 128 MB NOR Flash
* NAND Flash (typical sizes are 128/256/512/1024 MB)
The following table shows simplified chip selects organization. This, along with memory mapping, is strictly related to bootstrap configuration thus reading of pate xxx is recommended.
AM3517/05 provides 8 chip selects. By default, chip select #0 (boot) is connected to on-board NOR flash. Therefore this device acts as boot memory. NAND flash memory is by default connected to chip select #7 . Please note that NAND flash and NOR flash chip selects can be optionally switched in order to make NAND flash the boot memory. For more information about this option, please contact technical support at support-lizard@dave.eu.
{|class="wikitable"
|-
! style="width:90px;" | Chip Select #
! style="width:90px;" | Device
! style="width:90px;" | Physical Address
! style="width:90px;" | Size
|-
| 0 (GPMC)
| on-board NOR flash
| 0x0800:0000
| 128 MB
|-
| 1 (GPMC)
| user available
| user defined
| user defined
|-
| 2 (GPMC)
| user available
| user defined
| user defined
|-
| 3 (GPMC)
| user available
| user defined
| user defined
|-
| 4 (GPMC)
| user available
| user defined
| user defined
|-
| 5 (GPMC)
| user available
| user defined
| user defined
|-
| 6 (GPMC)
| on-board CPLD
| 0x2000:0000
| 16 MB
|-
| 7 (GPMC)
| on-board NANDflash
| 0x3000:0000
| 1024 MB
|-
| 0 (SDRC)
| on-board DDR2 SDRAM
| 0x8000:0000
| 256 MB
|-
|}