Changes

| rowspan="24" style="width:16%; text-align:left; padding:10px; border-left:solid 0px #73B2C7; font-size:12px; background-color:#ffffff" | '''DIN BAR profile 4 modules'''|-| style="width:10%; border-left:solid 2px #73B2C7;border-right:solid 0px #73B2C7;border-top:solid 0px #73B2C7;border-bottom:solid 0px #73B2C7; text-align:left; padding:10px; background-color:#ffffff" | [[RIALTO SBC|'''SBC RIALTO<br />CPU: based on NXP i.MX6UL''']]| style="width:10%; border-left:solid 0px #73B2C7;border-right:solid 0px #73B2C7;border-top:solid 0px #73B2C7;border-bottom:solid 0px #73B2C7; text-align:center; background-color:#ffffff" | [[File:RIALTO_SBC.png | 80x80px |link=RIALTO SBC | Details]]| style="width:10%; border-left:solid 2px #73B2C7;border-right:solid 0px #73B2C7;border-top:solid 0px #73B2C7;border-bottom:solid 0px #73B2C7; text-align:center; background-color:#ffffff" || style="width:10%; border-left:solid 0px #73B2C7;border-right:solid 0px #73B2C7;border-top:solid 0px #73B2C7;border-bottom:solid 0px #73B2C7; text-align:center; background-color:#ffffff" || style="width:10%; border-left:solid 2px #73B2C7;border-right:solid 0px #73B2C7;border-top:solid 0px #73B2C7;border-bottom:solid 0px #73B2C7; text-align:center; background-color:#ffffff" | [[ETRA SBC | '''SBC ETRA<br />CPU: based on ST STM32MP1''']]| style="width:10%; border-left:solid 0px #73B2C7;border-right:solid 0px #73B2C7;border-top:solid 0px #73B2C7;border-bottom:solid 0px #73B2C7; text-align:center; background-color:#ffffff" | [[File:ETRA_SBC_top.png | 80x80px |link=ETRA SBC | Details]]| style="width:10%; border-left:solid 2px #73B2C7;border-right:solid 0px #73B2C7;border-top:solid 0px #73B2C7;border-bottom:solid 0px #73B2C7; text-align:center; background-color:#ffffff" || style="width:10%; border-left:solid 0px #73B2C7;border-right:solid 0px #73B2C7;border-top:solid 0px #73B2C7;border-bottom:solid 0px #73B2C7; text-align:center; background-color:#ffffff" |

| style="width:10%; border-left:solid 2px #73B2C7;border-right:solid 0px #73B2C7;border-top:solid 0px #73B2C7;border-bottom:solid 0px #73B2C7; text-align:center; background-color:#ffffff" | [[ETRA SBC | style="width:10%; border-left:solid 0px #73B2C7;border-right:solid 0px #73B2C7;border-top:solid 0px #73B2C7;border-bottom:solid 0px #73B2C7; text-align:center; background-color:#ffffff" || style="width:10%; border-left:solid 2px #73B2C7;border-right:solid 0px #73B2C7;border-top:solid 0px #73B2C7;border-bottom:solid 0px #73B2C7; text-align:center; background-color:#ffffff" || style="width:10%; border-left:solid 0px #73B2C7;border-right:solid 0px #73B2C7;border-top:solid 0px #73B2C7;border-bottom:solid 0px #73B2C7; text-align:center; background-color:#ffffff" ||-| style="width:10%; border-left:solid 2px #73B2C7;border-right:solid 0px #73B2C7;border-top:solid 0px #73B2C7;border-bottom:solid 0px #73B2C7; text-align:center; background-color:#ffffff" || style="width:10%; border-left:solid 0px #73B2C7;border-right:solid 0px #73B2C7;border-top:solid 0px #73B2C7;border-bottom:solid 0px #73B2C7; text-align:center; background-color:#ffffff" || '''SBC ETRA<br />CPUstyle="width:10%; border-left:solid 2px #73B2C7;border-right:solid 0px #73B2C7;border-top:solid 0px #73B2C7;border-bottom:solid 0px #73B2C7; text-align:center; background-color: based on ST STM32MP1''']]#ffffff" || style="width:10%; border-left:solid 0px #73B2C7;border-right:solid 0px #73B2C7;border-top:solid 0px #73B2C7;border-bottom:solid 0px #73B2C7; text-align:center; background-color:#ffffff" | [[File| style="width:10%; border-left:ETRA_SBC.png solid 2px #73B2C7;border-right:solid 0px #73B2C7;border-top:solid 0px #73B2C7;border-bottom:solid 0px #73B2C7; text-align:center; background-color:#ffffff" | 100x100px |linkstyle=ETRA SBC "width:10%; border-left:solid 0px #73B2C7;border-right:solid 0px #73B2C7;border-top:solid 0px #73B2C7;border-bottom:solid 0px #73B2C7; text-align:center; background-color:#ffffff" | Details]]