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For this first attempt, 5 panels are prepared, each one containing 4 PCBs of the same type and with same template project i.e. the bill of materials (BOM) for the [https://www.dave.eu/en/solutions/system-on-modules/diva-som ''DIVA series 2'']. In this case, it has been decided to mount components only on ''top'' side of the PCB. Furthermore, in order to reduce complexity and simplify the problem for this test, anomalies generation is restricted to 2 contacts SMD passive components i.e. resistors, capacitors, and inductors. The table below reports all plausible anomalies that can be generated by editing the standard template project containing all the positions of the components for the P&P machine, decreasing or increasing the quantity of solder deposited by the serigraphy on the panel or that can be generated directly by the operator.
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|- style="font-weight:bold;"
|+'''Anomalies, generation process and numerosity'''
For labeling the images [https://www.makesense.ai/ ''makesense−ai''] tool was used.
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|+'''Total number of samples for each defect category'''
! Acceptable
! Missing
==Results validation==
A total of 6 proGAN models were built and trained, each one with the required number of ''straight-through'' and ''fade-in'' model stages, to generate several typologies of synthesized images at the desired target resolution, belonging to ''missing'' and ''tombstoning'' classes, more specifically ''full'' images (512 × 512 resolution), ''upper'' and ''lower'' soldering region images (256 × 256 resolution). The training was executed mainly on cloud, initially with the free services provided by Google Colab and finally on AWS SageMaker. {| class="wikitable" style="text-align:center; margin: auto;"
|- style="font-weight:bold;"
|+'''ProGANs training time on Google Colab and AWS SageMaker'''
! Class
! Synth image
|}
In the two figures below there are shown some examples taken from the generated sets of ''missing'' and ''tombstoning'' classes. For each image, from left to right, there are displayed samples of 512×512 and 256×256 resolution ''full'' typology and further on the right, from top to bottom, 256×256 ''upper'' and ''lower'' soldering region typology. {| style="background:transparent; color:black" border="0" align="center" cellpadding="10px" cellspacing="0px" height="550" valign="bottom"|- align="center"||[[File:Missing synthesized images.png|center|thumb|500x500px|Synthesized images for ''missing'' class]]||[[File:Tombstoning synthesized images.png|center|thumb|500x500px|Synthesized images for ''tombstoning'' class]]||} The synthesized images can be effectively used to train a SMC defects classification model for a future ML-based PCB-AVI application, only if they have a similar probability distribution function with respect to the original ones. In particular, it is interesting to verify if there is a clear separation in the data. To this end, it is possible to employ the t-distributed stochastic neighbor embedding (t-SNE), which is a ML algorithm for visualization, based on Stochastic Neighbor Embedding (SNE) algorithm. Since the way this algorithm operates is computationally expensive, it is highly recommended to use another dimensionality reduction technique before applying t-SNE algorithm, in order to reduce the number of dimensions to a reasonable amount. For this purpose, it is possible to employ an autoencoder (AE). IMMAGINE AUTOENCODER 5 × 10−4
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