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→Introduction
This Technical Note (TN for short) belongs to the series introduced [[ML-TN-003 — AI at the edge: visual inspection of assembled PCBs for defect detection — Part 1|here]]. Specifically, it illustrates the first issue to be considered to implement a device capable to spot mounting defects on an assembled PCB. In ML terminology, we are dealing again with a classification problem.
From an engineering perspective, one of the main goals of this work is still the evaluation of the Xilinx's DPU performances on inference tasks in terms of latency and throughput as Xilinx devices are in principle good candidates for implementing an automatic visual inspection machine as described in the [[ML-TN-003 — AI at the edge: visual inspection of assembled PCBs for defect detection — Part 1|opening article]] of this series. It is worth remembering that this matter was the characterization of Xilinx DPU used for solving a classification task is covered in [[ML-TN-001_-_AI_at_the_edge:_comparison_of_different_embedded_platforms_-_Part_3|this TN]] as well. HoweverNevertheless, coping with another classification problem task also allowed to evaluate how different deep CNN models perform on the same problem.
==Test Bed==
