Bureaucrats, dave_user, Administrators
4,650
edits
Changes
→Test bed
|For more details, please refer to the following sections.
|}
The target was configured in order to leverage the hardware acceleration provided by the [https://www.xilinx.com/products/intellectual-property/dpu.html Xilinx Deep Learning Processor Unit (DPU)], which is an IP instantiated in the Programmable Logic (PL) as depicted in the following block diagram.
[[File:ML-TN-001-MPSoC-PL1.png|thumb|center|600px|Top-level architecture of the system implemented in the SoC]]
[[File:ML-TN-001-MPSoC-PL2.png|thumb|center|600px|DPU-related subsystem]]
