The target was configured in order to leverage the hardware acceleration provided by the [https://www.xilinx.com/products/intellectual-property/dpu.html Xilinx Deep Learning Processor Unit (DPU)]. This , which is an IP was instantiated in the Programmable Logic (PL)as depicted in the following block diagram. TBD In particular, this is the DPU-related subsystem: TBD Interestingly, to some extent, the DPU can be customized in order to find the optimal trade-off between performances and resource allocation. The default configuration of the DPU used for the initial testing is shown in the following images. {| class="wikitable"|+DPU default configuration!|-|TBD|-|TBD|-|TBD|}