MITO 8M SOM/MITO 8M Hardware/pdf

General Information

MITO 8M SOM Block Diagram

[[File:Mito-bd-1.0.0-300dpi.png|thumb|MITO 8M Block diagram|none]]

MITO 8M SOM TOP View

[[File:DMI-Mito-top.png|thumb|MITO 8M TOP View|none]]

MITO 8M SOM BOTTOM View

[[File:DMI-Mito-bottom-300dpi.png|thumb|MITO 8M BOTTOM View|none]] {{#lst:MITO 8M SOM/MITO 8M Hardware/General Information/Processor and memory subsystem|Body}} {{#lst:MITO 8M SOM/MITO 8M Hardware/General Information/Hardware versioning and tracking|Body}} {{#lst:{{{nome-som}}} SOM/{{{nome-som}}} Hardware/SOM P/N composition|Body}}

Pinout Table

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Power and reset

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Reset scheme and control signals

The following picture shows the simplified block diagram of reset scheme and voltage monitoring.

NVCC_VSNVS

Some signals that are related to reset circuitry are pulled-up to NVCC_VSNVS (aka 3.3VIN).

Hence it is recommended that system designer takes into account these factors in order to properly manage these signals at carrier board level.

EXT_RESET

EXT_RESET is internally pulled-up with a 90kΩ to NVCC_VSNVS. Connect EXT_RESET signal to GND (for example with a button or an open-collector circuit) causes the internal supervisor IC to assert its RESETn output.

This will power down the VDD_SOC_0V9 and make PMIC_ON pulled low by PG (Power Good) of VDD_SOC_0V9 regulator.

Since PMIC_ON serves as the enable signal of PMIC and other discrete power supply chips, all the power supplies except for the SNVS domain will be OFF.

The RESETn will keep asserted for 270 ms after EXT_RESET is released, thus providing enough time for the power supplies to be completely powered down. During this time, the POR_B driven by the PMIC will also keep asserted (low).

After RESETn is released, the power supplies will start to ramp up in defined sequence. When all the power supplies have reached their operating voltages, POR_B will be de-asserted, and the CPU may begin booting from reset.

CPU_PORn

PMIC can assert this active-low signal. Other internal IC, such as ethernet PHY or boot memory devices, could be connected to this signal. This guarantees it is in a known state when reset signal is released.

CPU_ONOFF

CPU_ONOFF is internally pulled-up with a 100kΩ to NVCC_VSNVS. This input signal is connected directly to the ONOFF input of the CPU.

BOARD_PGOOD

BOARD_PGOOD is directly related to the internal NVCC_3V3 rail (I/O pins supply) presence and must be used as power enable for all the electronics on MITO 8M carrier board.

When the I/O pins power rail on MITO 8M is not ready (BOARD_PGOOD low) all the integrated circuits connected to the CPU must be powered off in order to avoid back-powering or other issue related to a wrong power-up sequence.

BOOT_MODE_SEL

BOOT_MODE_SEL is internally pulled-up with a 100kΩ to NVCC_3V3.

When connected to GND, select the external microSD as the boot device.

Handling CPU-initiated software reset

By default, MX8 processor does not assert any external signal when it initiates a software reset sequence. Also default software reset implementation does not guarantee that all processor registers are reset properly.

For these reasons it is strongly recommended to use a different approach that, in combination with the use of a processor's watchdog timer (WDT), provides a full hardware reset in case a software reset is issued.

This technique is implemented in DESK-MX8M-L. At the software level, U-Boot and Linux kernel software reset routines make use of the processor's WDT to assert the WDOG_B signal. This signal in turn is routed to the GPIO1_IO02 pad. At the hardware level, this signal is AC-coupled to the master reset pin of the internal supervisor IC. It acts as a complete hardware reset by the assertion of its RESETn output (on the same way of EXT_RESET pin).

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System boot

The boot process begins at Power On Reset (POR) where the hardware reset logic forces the ARM core to begin execution starting from the on-chip boot ROM. The boot ROM:

• determines whether the boot is secure or non-secure
• performs some initialization of the system and clean-ups
• reads the mode pins to determine the primary boot device
• once it is satisfied, it executes the boot code

Boot options

Two options are available related to system boot. They are identified by the Boot field of the ordering code as follows:

• 0: eMMC / SD option (SOM code: DMIxxx0xxxxR)
• 1: NAND / SD option (SOM code: DMIxxx1xxxxR)

For both options the selection of primary boot device is determined by the BOOT_MODE_SEL signal as described in the following sections. BOOT_MODE_SEL is latched when processor reset is released.

In any case, boot process is managed by on-chip boot ROM code that is described in detail in processor's Reference Manual.

eMMC / SD option

Selection of primary boot device is determined by the BOOT_MODE_SEL signal as follows:

• BOOT_MODE_SEL = 0
  • primary boot device is SD2 (USDHC2)
• boot ROM will try to boot a valid image from the SD card. In case no valid image is found, boot ROM shall enable USB serial download mode automatically
• BOOT_MODE_SEL = 1 or floating
  • primary boot device is eMMC connected to USDHC1
  • in case no valid image is found on eMMC, boot ROM shall enable USB serial download mode automatically

NAND / SD option

Selection of primary boot device is determined by the BOOT_MODE_SEL signal as follows:

• BOOT_MODE_SEL = 0
  • primary boot device is SD2 (USDHC2)
  • in case no valid image is found in SD card, boot ROM shall enable USB serial download mode automatically
• BOOT_MODE_SEL = 1 or floating
  • primary boot device is NAND flash
  • in case no valid image is found in NAND flash, boot ROM shall enable USB serial download mode automatically

Important note for manufacture mode management

When the internal boot and recover boot (if enabled) failed, the boot goes to the SD/MMC manufacture mode before the serial download mode.

By default, the SD/MMC manufacture mode is enabled. DAVE Embedded Systems do not blow the fuse of the DISABLE_SDMMC_MFG in order to disable it.

Boot ROM detect SD/MMC card on USDHC2 port. If a card is inserted, ROM will try to boot from it. SD2_CD_B is used as card detect signal during bootrom's manufacture mode. This signal need to be kept high during bootstrap stage in order to prevent the intervention of bootrom's manufacture mode, if it's not desidered.

Bootstrap stage has to be intended as the time elapsing between the release of hardware reset (CPU_PORn) and the execution of the first instruction of user code (typically this is the reset vector of U-Boot boot loader).

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On board JTAG connector

JTAG signals are routed to a dedicated connector on the MITO 8M PCB.

The connector is placed on the top side of the PCB, on the right side (please see the picture below).

JD5 - Connector's pinout

On the JF5 footprint can be hand soldered a header pinstrip 10x1x1.27mm connector. The following table reports the connector's pinout:

Pin#	Pin name	Function	Notes
1	DGND	-
2	EEPROM_WP	-
3	NC	-
4	JTAG_TCK	-	internal pull-up 10k to NVCC_3V3
5	JTAG_TMS	-
6	JTAG_TDO	-
7	JTAG_TDI	-
8	JTAG_nTRST	-
9	CPU_PORn	-	internal pull-up 100k to NVCC_SNVS
10	NVCC_3V3	-	reference voltage for JTAG signals

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Peripherals

Peripheral Audio

The Audio interface available on MITO 8M is based on iMX8M SoC which provides the following audio subsystems:

• Synchronous Audio Interface (SAI)
  • 6x I2S/SAI (20+ channels, each 32-bits @384 kHz)
  • Highest levels of pro audio fidelity with more than 20 audio channels each @384KHz
• Sony/Philips Digital Interface (SPDIF)
  • S/PDIF Tx/Rx

Description

The I2S (or I2S) module provides a synchronous audio interface (SAI) that supports full- duplex serial interfaces with frame synchronization such as I2S, AC97, TDM, and codec/DSP interfaces. It supports the following standards and features:

• Transmitter and receiver with independent bit clock and frame sync supporting 8 data lines
• Each data line can support a maximum Frame size of 32 words
• Asynchronous 128 x 32-bit FIFO for each transmit and receive data line
• Supports packing of 8-bit and 16-bit data into each 32-bit FIFO word
• Supports combining multiple data line FIFOs into single data line FIFO

The Sony/Philips Digital Interface (SPDIF) audio block is a stereo transceiver that allows the processor to receive and transmit digital audio.

Pin mapping

The Pin mapping is described in the Pinout table section

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Peripheral Ethernet

Description

The 10/100/1000-Mbit/s Ethernet interface available on MITO 8M is based on iMX8M SoC.

The SOC is directly interfaced with an ETH PHY chip (MICROCHIP KSZ9031RNX) that has the following features:

• Auto-Negotiation to Automatically Select the Highest Link-Up Speed (10/100/1000 Mbps) and Duplex (Half/Full)
• On-Chip Termination Resistors for the Differential Pairs
• Energy Detect Power-Down Mode for Reduced Power Consumption When the Cable is Not Attached

Important note for the external magnetic connection

The Ethernet peripheral requires an external insulator magnetic on the carrier board.

The four transformer center tap pins on the PHY side should not be connected to any power supply source on the board; rather, the center tap pins should be separated from one another and connected through separate 0.1 µF common-mode capacitors to ground. Separation is required because the common-mode voltage could be different between the four differential pairs, depending on the connected speed mode.

See KSZ9031RNX datasheet for more details.

Pin mapping

The Pin mapping is described in the Pinout table section

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Peripheral HDMI

HDMI (High-Definition Multimedia Interface) is a compact audio/video interface for transmitting uncompressed digital video data and uncompressed/compressed digital audio data.

HDMI connects digital audio/video sources-such as set-top boxes, Blu-ray Disc players, personal computers (PCs), video game consoles, and AV receivers to compatible digital audio devices, computer monitors, and digital televisions.

Description

The HDMI interface available on MITO 8M is based on iMX8M SoC.

The HDMI port supports the following standards and features:

• High-Definition Multimedia Interface Specification, Version up to 2.0a
• Compliant with HDCP2.2 (and back compatible with HDCP1.3/HDCP1.4)
• Variety of video resolutions and formats
  • Supports up to 4k2k at 60Hz resolution
  • Supports 8, 10, 12, and 16bpp
  • Supports RGB, YCbCr422 formats
• Variety of audio formats – PCM and compressed, over I2S interface
  • I2S PCM samples are converted to comply with IEC60958 sub-frames
  • Supporting I2S-TDM

Pin mapping

The Pin mapping is described in the Pinout table section

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Peripheral LVDS

The LVDS interface available on MITO 8M is based on a MIPI® DSI To FLATLINK™ LVDS bridge IC.

It is directly connected to the MIPI® DSI output port of iMX8M SOC.

This support covers all aspects of these activities:

• Connectivity to relevant devices - Displays with LVDS receivers
• Arranging the data as required by the external display receiver and by LVDS display standards
• Synchronization and control capabilities

Description

The LVDS port supports the following standards and features:

• Suitable for 60-fps WUXGA 1920 × 1200 Resolution at 18-bpp and 24-bpp Color, 60 fps 1366 × 768 at 18 bpp and 24 bpp
• Output Configurable for Single-Link or Dual-Link LVDS
• LVDS Output Clock Range of 25 MHz to 154 MHz in Dual-Link or Single-Link Modes

Pin mapping

The Pin mapping is described in the Pinout table section

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Peripheral MIPI

The MIPI interfaces available on iMX8M SoC are following described:

• The Camera Serial Interface (CSI) is a specification of the Mobile Industry Processor Interface (MIPI) Alliance. It defines an interface between a camera and a host processor.
• The Display Serial Interface (DSI) is a specification by the Mobile Industry Processor Interface (MIPI) Alliance aimed at reducing the cost of display controllers in a mobile device. It is commonly targeted at LCD and similar display technologies.

The two CSI interface on MITO 8M SOM:

• CSI1 is avaiable on SODIMM connector pinout
• CSI2 is avaiable on ONE PIECE expansion connector J5

The DSI interface is internally used on MITO 8M SOM to generate an LVDS output interface. More details on LVDS section.

Description

The MIPI CSI port supports the following standards and features:

• Configurable interface logic to support most commonly available CMOS sensors.
• Scalable data lane support, 1 to 4 Data Lanes
• Support for CCIR656 video interface as well as traditional sensor interface.
• 8-bit / 16-bit / 24-bit data port for YCbCr, YUV, or RGB data input.
• 8-bit / 10-bit / 16-bit data port for Bayer data input.
• Implements all three CSI-2 MIPI layers (Pixel to byte packing, low level protocol, Lane management)

Pin mapping

The Pin mapping is described in the Pinout table section

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Peripheral SDIOs

The Ultra Secured Digital Host Controller (uSDHC) provides the interface between the host system and the SD/SDIO/MMC cards or devices.

MITO 8M SOM provides up to two SDIO interface available for an external memory device connection.

The availability of this interface is related to the SOM mounting option:

• on NAND on board version, the NAND interface is internally connected, and the SD1 interface is routed externally the SOM
• on eMMC on board version, the SD1 interface is internally connected, and the NAND interface is routed externally the SOM

See Pin mapping tables for connection details.

Description

The SDIOs interface available on MITO 8M is based on iMX8M SoC.

The SDIOs port supports the following standards and features:

• Conforms to the SD Host Controller Standard Specification version 2.0/3.0
• Compatible with the MMC System Specification version 4.2/4.3/4.4/4.41/5.0/5.1
• Compatible with the SD Memory Card Specification version 3.0 and supports the Extended Capacity SD Memory Card
• Compatible with the SDIO Card Specification version 2.0/3.0
• Supports 1-bit/4-bit SD and SDIO modes, and 1-bit/4-bit/8-bit MMC modes
• Card bus clock frequency up to 208 MHz

Pin mapping

The Pin mapping is described in the Pinout table section

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Peripheral UARTs

Description

The Universal Asynchronous Receiver/Transmitter (UART) interface available on MITO 8M is based on iMX8M SoC.

UARTs provides serial communication capability with external devices and support NRZ encoding format, RS485 compatible 9 bit data format and IrDA-compatible infrared slow data rate (SIR) format.

The UART port supports the following standards and features:

• High-speed TIA/EIA-232-F compatible, up to Mbit/s
• Serial IR interface low-speed, IrDA-compatible (up to 115.2 Kbit/s)
• 9-bit or Multidrop mode (RS-485) support (automatic slave address detection)
• 7 or 8 data bits for RS-232 characters, or 9 bit RS-485 format
• 1 or 2 stop bits
• Programmable parity (even, odd, and no parity)
• Hardware flow control support for request to send (RTS_B) and clear to send (CTS_B) signals
• Two independent, 32-entry FIFOs for transmit and receive

Pin mapping

The Pin mapping is described in the Pinout table section

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Peripheral USB

Universal Serial Bus (USB) is an industry standard that establishes specifications for cables and connectors and protocols for connection, communication and power supply (interfacing) between computers, peripherals and other computers.

Description

The two USB interface available on MITO 8M are based on iMX8M SoC.

Each USB 3.0-compliant serial interface port supports the following standards and features:

• USB dual-role operation and can be configured as host or device
• Super-speed (5 Gbit/s), high-speed (480 Mbit/s), full-speed (12 Mbit/s), and low-speed (1.5 Mbit/s) operations.
• OTG (on-the-go) 2.0 compliant, which includes both device and host capability. Super-speed operation is not supported when OTG is enabled.

Pin mapping

The Pin mapping is described in the Pinout table section

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Peripheral PCI Express

PCI Express (Peripheral Component Interconnect Express) is a high-speed serial computer expansion bus standard, designed to replace the older PCI, PCI-X and AGP bus standards.

The two PCI Express interface on MITO 8M SOM:

• PCIe1 is avaiable on SODIMM connector pinout
• PCIe2 is avaiable on ONE PIECE expansion connector J5

Description

The PCI Express interfaces available on MITO 8M is based on iMX8M SoC.

The PCI Express interfaces supports the following standards and features:

• two PCIe PHY ports (1-lines each)
• up to 6.0 Gbps data rate
• complies to PCI Express base specification 2.1.
• 8B/10B Encoding / Decoding
• Supports Spread Spectrum Clocking in Transmitter and Receiver

Pin mapping

The Pin mapping is described in the Pinout table section

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Peripheral GPIOs

The GPIO general-purpose input/output peripheral provides dedicated general-purpose pins that can be configured as either inputs or outputs.

Description

When configured as an output, it is possible to write to an internal register to control the state driven on the output pin. When configured as an input, it is possible to detect the state of the input by reading the state of an internal register. In addition, the GPIO peripheral can produce CORE interrupts.

Pin mapping

The Pin mapping is described in the Pinout table section

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Real Time Clock

This chapter describes the technical specifications and features for the RTC component on the MITO 8M module.

The Real Time Clock available on MITO 8M is based on iMX8M SoC.

Features

The MITO 8M module uses a 32.768kHz dedicated crystal in order to obtain an accurate time base for the RTC.

Important note for RTC during power-off

On the MITO 8M module the SNVS voltage rails are obtained by the main supply of the SOM.

For this reason, there is no possibility to keep operative the CPU RTC when the SOM is not connected to the 3.3VIN power rail.

Use an external RTC with battery backup functionality if required.

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Peripheral Watchdog

The Watchdog Timer (WDOG) protects against system failures by providing a method by which to escape from unexpected events or programming errors.

Description

By default, the Watchdog Timer of iMX8M SOC is internally used on MITO 8M for the CPU-initiated software reset function.

For more details see the reset scheme and control signals section.

Pin mapping

The Pin mapping is described in the Pinout table section

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Electrical, Thermal and Mechanical Features

Operational characteristics

Maximum ratings

Parameter	Min	Typ	Max	Unit
Main power supply voltage	0	3.3	3.6	V

Recommended ratings

Parameter	Min	Typ	Max	Unit
Main power supply voltage	3.135	3.3	3.465	V

Power consumption

Providing theoretical maximum power consumption value would be useless for the majority of system designers building their application upon MITO 8M module. Practically speaking, these figures would be of no help when it comes to size power supply unit or to perform thermal design of real systems.

Instead, several configurations have been tested in order to provide figures that are measured on real-world use cases.

Please note that MITO 8M platform is so flexible that it is virtually impossible to test for all possible configurations and applications on the market. The use cases here presented should cover most of real-world scenarios. However actual customer's application might require more power than values reported here or customer's use case may be differ significantly with respect to the ones here considered.

Therefore, application-specific requirements have always to be taken into consideration in order to size power supply unit and to implement thermal management properly.

Use cases results

Measurements have been performed on the MITO 8M SOM under test is equipped with:

Section not completed yet

Checkpoint	Power (mW)
U-boot prompt	xxxx
Linux prompt	xxxx
Stress App test (*)	xxxx

(*) Stressful Application Test: https://github.com/stressapptest/stressapptest

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Thermal management

The MITO 8M SOM is designed to support the maximum available temperature range declared by the manufacturer.

The customer shall define and conduct a reasonable number of tests and verification in order to qualify the DUT capabilities to manage the heat dissipation.

Any heatsink, fan etc shall be defined case by case.

DAVE Embedded Systems' team is available for any additional information, please contact sales@dave.eu.

Heatsink suggestion

The MITO 8M SOM is designed with two holes that allow to mount a heatsink directly on the CPU IC.

Suggested part are ATS Push Pin Heat Sinks CPX0250250xx or FPX0250250xx part numbers.

See ATS website for more details [1].

Software thermal protection

In DESK-MX8-L, two software thermal protection mechanisms are implemented. Both are based on the processor's temperature sensor. It is worth remembering that maximum junction temperature (also denoted as Tj in the rest of the document) is:

• 95°C for Consumer parts
• 105°C for Industrial parts

Section not completed yet

U-Boot

At U-Boot level, automatic boot procedure is halted until Tj is smaller than (following temperatures might seem excessively low but they take into account the intrinsic poor precision of the temperature sensor to provide a reasonable safe margin):

• TBD for Consumer parts
• 95°C for Industrial parts

Linux kernel

At Linux level, a more sophisticated protection mechanism is implemented. Please refer to the following sections for more details.

The default temperature thresholds depend on the silicon grade, as follows:

• for Consumer parts
  • passive threshold: TBD
  • critical threshold: TBD
• for Industrial parts
  • passive threshold: 85°C
  • critical threshold: 95°C

Practically speaking, for DESK-MX8-L this mechanism makes use of two different thresholds, denoted as trip_point0 (also known as passive threshold) and trip_point1 (also known as critical threshold).

When Tj reaches trip_point0, Linux kernel scales down processor frequency.

If Tj reaches trip_point1, a complete shutdown is triggered:

thermal thermal_zone0: critical temperature reached(95 C),shutting down

By default, temperature thresholds are set up as follows:

• trip_point0: 85°C
• trip_point1: 95°C.

Trip point thresholds can be accessed via sysfs interface from user space. The following example shows how to read the values of the trip points:

root@mito:~# cat /sys/devices/virtual/thermal/thermal_zone0/trip_point_0_temp
85000
root@mito:~# cat /sys/devices/virtual/thermal/thermal_zone0/trip_point_1_temp
950000

This example shows how to set trip points 0 and 1 to 95°C and 100°C respectively:

echo 95000 > /sys/class/thermal/thermal_zone0/trip_point_0_temp
echo 100000 > /sys/class/thermal/thermal_zone0/trip_point_1_temp

Please note that:

• it is possible to set up trip points greater than the maximum junction temperature indicated by manufacturer datasheet;
• exceeding maximum junction temperature indicated by manufacturer datasheet may cause permanent damage.

To read current processor temperature please issue this command (reported temperature is 36.676°C in the example):

root@mito:~# cat /sys/class/thermal/thermal_zone0/temp
36676

For more details about this functionality, please refer to Documentation/thermal/sysfs-api.txt in the kernel sources.

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Mechanical specifications

This chapter describes the mechanical characteristics of the MITO 8M module.

Board Layout

The following figure shows the physical dimensions of the MITO 8M module:

MITO8M TOP view

MITO8M side view

MITO8M heat sink holes detail view

Connectors

The following figure shows the MITO 8M connector layout:

MITO8M connectors TOP view

MITO8M connectors BOTTOM view

CAD drawings

• DXF (2D): CS031518.dxf
• STEP (3D): CS031518

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