a000298_approval, dave_user
299
edits
Changes
→BOOT_MODE_SEL
=== EXT_RESET ===
EXT_RESET is internally pulled-up with a 90kΩ to NVCC_VSNVS. Connect EXT_RESET signal to DGND GND (for example with a button or an open-collector circuit) causes the internal supervisor IC to assert its RESETn output.
This will power down the VDD_SOC_0V9 and make PMIC_ON pulled low by PG (Power Good) of VDD_SOC_0V9 regulator.
PMIC can assert this active-low signal. Other internal IC, such as ethernet PHY or boot memory devices, could be connected to this signal. This guarantees it is in a known state when reset signal is released.
=== CPU_ONOFF ===
CPU_ONOFF is internally pulled-up with a 100kΩ to NVCC_VSNVS. This input signal is connected directly to the ONOFF input of the CPU.
=== BOARD_PGOOD ===
BOARD_PGOOD is directly related to the internal NVCC_3V3 rail (I/O pins supply) presence and must be used as power enable for all the electronics on MITO 8M carrier board.
When the I/O pins power rail on MITO 8M is not ready (BOARD_PGOOD low) all the integrated circuits connected to the CPU must be powered off in order to avoid back-powering or other issue related to a wrong power-up sequence.
=== BOOT_MODE_SEL ===
BOOT_MODE_SEL is internally pulled-up with a 100kΩ to NVCC_3V3.
When connected to GND, select the external microSD as the boot device.
=== Handling CPU-initiated software reset ===