[[File:MITO 8M-reset-scheme.png | 800px]]
''TBD: qui di seguito vanno inserite le sezioni che includano la descrizione dei segnali coinvolti nella fase di Reset, ad esempio:''
* MRST
* POR
* SNVS
* SYSRST
* ...
'''TBD: indicare le connessioni del segnale di reset verso altri device interni (come per esempio la NOR SPI'''
''TBD: di seguito la pagina di AXEL Lite da rivedere nel caso di altri SOM''
=== NVCC_VSNVS ===
=== CPU_PORn ===
The following devices PMIC can assert this active-low signal:. Other internal IC, such as ethernet PHY or boot memory devices, could be connected to this signal. This guarantees it is in a known state when reset signal is released.* PMIC=== CPU_ONOFF ===* multipleCPU_ONOFF is internally pulled-voltage monitor: this device monitors critical power voltages and triggers a reset pulse in case any of these exhibits up with a brownout condition 100kΩ to NVCC_VSNVS.
Since SPI NOR flash can be used as boot device, CPU_PORn is connected to this device too. This guarantees it is in a known state when reset signal is released.=== BOARD_PGOOD ===
=== CPU_ONOFF BOOT_MODE_SEL ===CPU_ONOFF is internally pulled-up with a 100kΩ to NVCC_VSNVS.
=== Handling CPU-initiated software reset ===