For these reasons we it is strongly recommended to use a different approach that, in combination with the use of a processor's watchdog timer (WDT), provides a full hardware reset in case a software reset is issued.

This technique is implemented in [[DESK-MX8|DESK-MX8]]. At the software level, U-Boot and Linux kernel software reset routines make use of the processor's WDT to assert the WDOG_B signal. This signal in turn is routed to the GPIO1_IO02 pad. At the hardware level, this signal is AC-coupled to the master reset pin of the SOM voltage monitorinternal supervisor IC. It's act acts as a complete harware hardware reset by the assertion of its RESETn output (on the same way of EXT_RESETpin) by powering down the VDD_SOC_0V9 regulator.