=== PMIC_VSNVS NVCC_VSNVS ===Some signals that are related to reset circuitry are pulled-up to PMIC_VSNVS. This voltage is generated by PMIC PF0100's VSNVS LDO/Switch and its actual value depends on:* voltage applied to PMICS's VIN pin** in case of AxelLite this pin is connected to NVCC_VSNVS (aka 3.3VIN power rail* voltage applied to PMICS's LICELL pin** in case of AxelLite this pin is connected to pin 14 of SODIMM connector (PMIC_LICELL).* PMIC's VSNVSCTL register configuration.

For more details please refer === EXT_RESET ===EXT_RESET is internally pulled-up with a 90kΩ to section ''VSNVS LDO/Switch'' NVCC_VSNVS. Connect EXT_RESET signal to DGND (for example with a button or an open-collector circuit) causes the internal supervisor IC to assert its RESETn output. This will power down the VDD_SOC_0V9 and make PMIC_ON pulled low by PG (Power Good) of ''MMPF0100 Advance Information'' documentVDD_SOC_0V9 regulator.  Since PMIC_ON serves as the enable signal of PMIC and other discrete power supply chips, all the power supplies except for the SNVS domain will be OFF. The RESETn will keep asserted for 270 ms after EXT_RESET is released, thus providing enough time for the power supplies to be completely powered down. During this time, the POR_B driven by the PMIC will also keep asserted (low). After RESETn is released, the power supplies will start to ramp up in defined sequence. When all the power supplies have reached their operating voltages, POR_B will be de-asserted, and the CPU may begin booting from reset.

'''By default, MX6 MX8 processor does not assert any external signal when it initiates a software reset sequence. Also default software reset implementation does not guarantee that all processor registers are reset properly'''.

For these reasons, it is strongly recommended to we use a different approach that, in combination with the use of a processor's watchdog timer (WDT), provides a full hardware reset in case a software reset is issued.

This technique is implemented in [[DESK-MX8|DESK-MX8-L]]. At software level, U-Boot and Linux kernel software reset routines make use of processor's WDT #2 to assert the WDOG2_B reset WDOG_B signal. This signal in turn is routed to GPIO_1 GPIO1_IO02 pad (MUX mode = 1). At hardware level, this signal is AC-coupled to the master reset pin of the SOM voltage monitor. It's act a 3-state output buffer complete harware reset (please refer to U22 chip on same way of [[AxelEVB-Lite]] carrier boardEXT_RESET), driving PMIC_PWRONby powering down the VDD_SOC_0V9 regulator.