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EXT_RESET is internally pulled-up with a 90kΩ to NVCC_VSNVS. Connect EXT_RESET signal to DGND GND (for example with a button or an open-collector circuit) causes the internal supervisor IC to assert its RESETn output.

The following devices PMIC can assert this active-low signal:. Other internal IC, such as ethernet PHY or boot memory devices, could be connected to this signal. This guarantees it is in a known state when reset signal is released.* PMIC=== CPU_ONOFF ===* multipleCPU_ONOFF is internally pulled-voltage monitor: this device monitors critical up with a 100kΩ to NVCC_VSNVS. This input signal is connected directly to the ONOFF input of the CPU. === BOARD_PGOOD ===BOARD_PGOOD is directly related to the internal NVCC_3V3 rail (I/O pins supply) presence and must be used as power enable for all the electronics on MITO 8M carrier board. When the I/O pins power voltages and triggers a reset pulse rail on MITO 8M is not ready (BOARD_PGOOD low) all the integrated circuits connected to the CPU must be powered off in case any of these exhibits order to avoid back-powering or other issue related to a brownout condition wrong power-up sequence.

Since SPI NOR flash can be used as boot device, CPU_PORn === BOOT_MODE_SEL ===BOOT_MODE_SEL is connected internally pulled-up with a 100kΩ to this device too. This guarantees it is in a known state when reset signal is releasedNVCC_3V3.

=== CPU_ONOFF ===CPU_ONOFF is internally pulled-up with a 100kΩ When connected to NVCC_VSNVSGND, select the external microSD as the boot device.

This technique is implemented in [[MITO_8M_SOM/DESK-MX8MX8M-L|DESK-MX8MX8M-L]]. At the software level, U-Boot and Linux kernel software reset routines make use of the processor's WDT to assert the WDOG_B signal. This signal in turn is routed to the GPIO1_IO02 pad. At the hardware level, this signal is AC-coupled to the master reset pin of the internal supervisor IC. It acts as a complete hardware reset by the assertion of its RESETn output (on the same way of EXT_RESET pin).