a000298_approval, dave_user
299
edits
Changes
no edit summary
<section begin=History/>
{| style="border-collapse:collapse; "
!colspan="4" style="width:100%; text-align:left"; border-bottom:solid 2px #ededed"|History
|-
!style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Version!style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Issue Date!style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Notes
|-
|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|X1.Y0.Z0|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|Month YearSep 2020|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|TBDFirst release
|-
|-
|}
== Power Supply Unit (PSU) and recommended power-up sequence ==
Implementing correct power-up sequence for ''TBD: SOC 'iMX8M'' processors is not a trivial task because several power rails are involved.
MITO 8M SOM simplifies this task by embedding all the needed circuitry. The following picture shows a simplified block diagram of PSU/voltage monitoring circuitry:
* generates the proper power-up sequence required by the SOC processor and surrounding memories and peripherals
* synchronizes the powering up of carrier board in order to prevent back power
=== Power-up sequence===
The typical power-up sequence is the following:''TBD: descrizione dei segnali che intervengono nella PS''# 3.3VIN main power supply rail is powered# SNVS domain signals are pulled-up (unless carrier board circuitry keeps this signal low for any reason)# CPU_PORn (active-low) is driven low by PMIC# RTC_RESET_B are internally released after 200ms# VDD_SOC regulator starts and enables the VDD_ARM and PMIC regulators# PMIC initiates power-up sequence needed by iMX8M processor# BOARD_PGOOD goes up when NVCC_3V3 (CPU I/O power rail) is ready# CPU_PORn is deasserted after the last regulator to bring the processor out of reset
==== Note on BOARD_PGOOD usage ====
BOARD_PGOOD is generally used on carrier board to drive loads such as DC/DC enable inputs or switch on/off control signals.
Depending on the kind of such loads, BOARD_PGOOD might not be able to drive them properly. In these cases because it has a simple 2-input AND port can be used to address this issue. The following picture depicts a principle schematic showing this solution20mA output current absolute maximum rating.
[[File:MITO 8M-power-good.png]]