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MITO 8M SOM/MITO 8M Hardware/Pinout Table

327 bytes removed, 17:49, 28 December 2023
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<section begin="History" />
{| style="border-collapse:collapse; "
! colspan="4" style="width:100%; text-align:left" ; border-bottom:solid 2px #ededed" |History
|-
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Version
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Issue Date
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Notes
|-
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |1.0.0{{oldid| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" 10368|Sep 2020/09/29}}
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |First release
|-
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#ededed; padding:5px; color:#000000" |2021/02/02
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#ededed; padding:5px; color:#000000" |Add pull-up/down information
|-
|}
<section end="History" /><section begin="Body" />==IntroductionConnectors and Pinout Table description==
This chapter contains === Connectors description ===In the following table are described all available connectors integrated on MITO 8M SOM:{| class="wikitable"|-!Connector name!Connector Type!Notes!Carrier board counterpart|-|J1|SODIMM edge connector 204 pin|partially compatible with [[AXEL Lite SOM]]|TE Connectivity 2-2013289-1|-|J4|ONE PIECE connector single row 25pins||SAMTEC FSI-125-03-G-S-AD-TR|-|J5|ONE PIECE connector single row 25pins||SAMTEC FSI-125-03-G-S-AD-TR|}The dedicated carrier board must mount the mating connector and pinout description of connect the desired peripheral interfaces according to MITO 8M modulepinout specifications.See the images below for reference:
All interface signals that MITO 8M provides are routed through the following connectors:* 1 x 204 pins SO-DIMM edge connector with interfaces signals (named J1)** partially compatible with [[AXEL Lite SOM]]* 2 x 25 pins One Piece mating board layout Expansion (named J4 and J5)The dedicated carrier board must mount the mating connector and connect the desired peripheral interfaces according to MITO 8M pinout specifications. [[File:MITO 8M-conn-TOP.png|500px|thumb|center|MITO 8M TOP view|none]][[File:MITO 8M-conn-BOTTOM.png|500px|thumb|center|MITO 8M BOTTOM view|none]]
Below a detailed description of the pinout, grouped in the following tables:
* a dedicated tables for J5 one-piece connector
=== Pinout Table description ===
Each row in the pinout tables contains the following information:
{| class="wikitable"
|-
|'''Pin Name'''
| Pin (signal) name on the AxelLite MITO 8M connectors
|-
|'''Internal<br>connections'''
| Connections to the Axel Ultra components
* CPU.<x> : pin connected to CPU pad named <x>
* PMIC.<x> : pin connected to the Power Manager IC(NXP PF4210)* LAN.<x> : pin connected to the LAN PHY(MICROCHIP KSZ9031RNX)* BRIDGE.<x> : pin connected to the MIPI-to-LVDS bridge* SV.<x>: pin connected to voltage supervisor(TI SN65DSI84)
|-
|'''Ball/pin #'''
|-
|}
 
==SODIMM J1 ODD pins declaration ==
{| class="wikitable"
|
|-
|} ==Pinout Table ODD pins declaration == {| class="wikitable"! latexfontsize="scriptsize" | Pin ! latexfontsize="scriptsize" | Pin Name! latexfontsize="scriptsize" | Internal Connections ! latexfontsize="scriptsize" | Ball/pin # ! latexfontsize="scriptsize" |Voltage domain! latexfontsize="scriptsize" | Type ! latexfontsize="scriptsize" | Notes! colspan="2" latexfontsize="scriptsize" | Alternative Functions|-|J1.1|DGND|DGND| -| -|G||||-|J1.35
|3.3VIN
|INPUT VOLTAGE
|
|-
|J1.57
|3.3VIN
|INPUT VOLTAGE
|
|-
|J1.79
|3.3VIN
|INPUT VOLTAGE
|
|-
|J1.9|3.3VIN|INPUT VOLTAGE| -|3.3VIN|S||||-|J1.11
|DGND
|DGND
|I/O
|Must be level translated if used @ 3V3
Internally pulled-up to 1.8V during bootstrap
|
|
|I/O
|Must be level translated if used @ 3V3
Internally pulled-up to 1.8V during bootstrap
|
|
| rowspan="3" |I/O
| rowspan="3" |Internally used for MIPI-to-LVDS interrupt, do not connect
Pulled-up to NVCC_3V3
|ALT0
|GPIO1_IO05
|}
==Pinout Table SODIMM J1 EVEN pins declaration ==
{| class="wikitable"
| rowspan="4" |CPU.SAI5_MCLK
| rowspan="4" |K4
| rowspan="4" |NVCC_3V3| rowspan="4" |I/O
| rowspan="4" |
|ALT0
|SAI5_MCLK
|-
|
|
|ALT1
|SAI1_TX_BCLK
|-
|
|
|ALT2
|SAI4_MCLK
|-
|
|
|ALT5
|GPIO3_IO25
|VDDA_1V8
|D
|Internally used for PCIe CLK, do not connect
|
|
|VDDA_1V8
|D
|Internally used for PCIe CLK, do not connect
|
|
| -
|S
|Absolute maximum ratings 5.25V
|
|
| -
|S
|Absolute maximum ratings 5.25V
|
|
|}
==Pinout Table ONE PIECE J4 pins declaration ==
{| class="wikitable"
! latexfontsize="scriptsize" | Pin
| rowspan="7" |NVCC_3V3
| rowspan="7" |I/O
| rowspan="7" |internally Internally used for BOOT configCould be pulled-up or down during bootstrap.
|ALT0
|SAI1_RX_DATA7
| rowspan="6" |NVCC_3V3
| rowspan="6" |I/O
| rowspan="6" |internally Internally used for BOOT configCould be pulled-up or down during bootstrap.
|ALT0
|SAI1_RX_DATA6
| rowspan="7" |NVCC_3V3
| rowspan="7" |I/O
| rowspan="7" |internally Internally used for BOOT configCould be pulled-up or down during bootstrap.
|ALT0
|SAI1_RX_DATA5
| rowspan="6" |NVCC_3V3
| rowspan="6" |I/O
| rowspan="6" |internally Internally used for BOOT configCould be pulled-up or down during bootstrap.
|ALT0
|SAI1_RX_DATA4
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |internally Internally used for BOOT configCould be pulled-up or down during bootstrap.
|ALT0
|SAI1_RX_DATA3
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |internally Internally used for BOOT configCould be pulled-up or down during bootstrap.
|ALT0
|SAI1_RX_DATA2
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |internally Internally used for BOOT configCould be pulled-up or down during bootstrap.
|ALT0
|SAI1_RX_DATA1
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |internally Internally used for BOOT configCould be pulled-up or down during bootstrap.
|ALT0
|SAI1_RX_DATA0
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |internally Internally used for BOOT configCould be pulled-up or down during bootstrap.
|ALT0
|SAI1_TX_DATA0
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |internally Internally used for BOOT configCould be pulled-up or down during bootstrap.
|ALT0
|SAI1_TX_DATA1
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |internally Internally used for BOOT configCould be pulled-up or down during bootstrap.
|ALT0
|SAI1_TX_DATA2
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |internally Internally used for BOOT configCould be pulled-up or down during bootstrap.
|ALT0
|SAI1_TX_DATA3
| rowspan="6" |NVCC_3V3
| rowspan="6" |I/O
| rowspan="6" |internally Internally used for BOOT configCould be pulled-up or down during bootstrap.
|ALT0
|SAI1_TX_DATA4
| rowspan="6" |NVCC_3V3
| rowspan="6" |I/O
| rowspan="6" |internally Internally used for BOOT configCould be pulled-up or down during bootstrap.
|ALT0
|SAI1_TX_DATA5
| rowspan="6" |NVCC_3V3
| rowspan="6" |I/O
| rowspan="6" |internally Internally used for BOOT configCould be pulled-up or down during bootstrap.
|ALT0
|SAI1_TX_DATA6
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |internally Internally used for BOOT configCould be pulled-up or down during bootstrap.
|ALT0
|SAI1_TX_DATA7
|}
==Pinout Table ONE PIECE J5 pins declaration ==
{| class="wikitable"
! latexfontsize="scriptsize" | Pin
|ALT5
|GPIO5_IO21
|}
 
==Pinout Table JD5 pins declaration ==
{| class="wikitable"
! latexfontsize="scriptsize" | Pin
! latexfontsize="scriptsize" | Pin Name
! latexfontsize="scriptsize" | Internal Connections
! latexfontsize="scriptsize" | Ball/pin #
! latexfontsize="scriptsize" | Voltage domain
! latexfontsize="scriptsize" | Type
! latexfontsize="scriptsize" | Notes
! colspan="2" latexfontsize="scriptsize" | Alternative Functions
|-
|JD5.1
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
|JD5.2
|EEPROM_WP
|Internal EEPROM Write Protect
| -
|NVCC_3V3
|I
|
|
|
|-
|JD5.3
|NC
|Not Connected
| -
| -
|Z
|
|
|
|-
|JD5.4
|JTAG_TCK
|CPU.JTAG_TCK
|T5
|NVCC_3V3
|I
|internal pull-up 10k to NVCC_3V3
|
|
|-
|JD5.5
|JTAG_TMS
|CPU.JTAG_TMS
|V5
|NVCC_3V3
|I
|
|
|
|-
|JD5.6
|JTAG_TDO
|CPU.JTAG_TDO
|U5
|NVCC_3V3
|O
|
|
|
|-
|JD5.7
|JTAG_TDI
|CPU.JTAG_TDI
|W5
|NVCC_3V3
|I
|
|
|
|-
|JD5.8
|JTAG_nTRST
|CPU.JTAG_TRST_B
|U6
|NVCC_3V3
|I
|
|
|
|-
|JD5.9
|CPU_PORn
|CPU.POR_B
PMIC.RESETMCU
|W20
3
|NVCC_SNVS
|I/O
|internal pull-up 100k to NVCC_SNVS
|
|
|-
|JD5.10
|NVCC_3V3
|NVCC_3V3
| -
|<nowiki>-</nowiki>
|S
|
|
|
|}
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