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MITO 8M SOM/MITO 8M Hardware/Pinout Table

13,617 bytes added, 17:49, 28 December 2023
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<section begin="History" />
{| style="border-collapse:collapse; "
! colspan="4" style="width:100%; text-align:left" ; border-bottom:solid 2px #ededed" |History
|-
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Version
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Issue Date
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Notes
|-
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |1.0.0{{oldid| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" 10368|Sep 2020/09/29}}
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |First release
|-
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#ededed; padding:5px; color:#000000" |2021/02/02
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#ededed; padding:5px; color:#000000" |Add pull-up/down information
|-
|}
<section end="History" /><section begin="Body" />==Connectors and Pinout Table=====Introduction=description==
This chapter contains === Connectors description ===In the following table are described all available connectors integrated on MITO 8M SOM:{| class="wikitable"|-!Connector name!Connector Type!Notes!Carrier board counterpart|-|J1|SODIMM edge connector 204 pin|partially compatible with [[AXEL Lite SOM]]|TE Connectivity 2-2013289-1|-|J4|ONE PIECE connector single row 25pins||SAMTEC FSI-125-03-G-S-AD-TR|-|J5|ONE PIECE connector single row 25pins||SAMTEC FSI-125-03-G-S-AD-TR|}The dedicated carrier board must mount the mating connector and connect the desired peripheral interfaces according to MITO 8M pinout specifications. See the images below for reference: [[File:MITO 8M-conn-TOP.png|500px|thumb|MITO 8M TOP view|none]][[File:MITO 8M-conn-BOTTOM.png|500px|thumb|MITO 8M BOTTOM view|none]] Below a detailed description of the MITO 8M modulepinout, grouped in the following tables:* two tables (odd ODD and even EVEN pins) that report the pin mapping of the 204-pin SO-DIMM MITO 8M edge* a dedicated tables for J4 one-piece connector* a dedicated tables for J5 one-piece connector.
=== Pinout Table description ===
Each row in the pinout tables contains the following information:
 {|class="wikitable" style="width:50%;"
|-
|'''Pin'''
|-
|'''Pin Name'''
| Pin (signal) name on the AxelLite MITO 8M connectors
|-
|'''Internal<br>connections'''
| Connections to the Axel Ultra components
* CPU.<x> : pin connected to CPU pad named <x>
* CAN.<x> : pin connected to the CAN transceiver* PMIC.<x> : pin connected to the Power Manager IC(NXP PF4210)* LAN.<x> : pin connected to the LAN PHY(MICROCHIP KSZ9031RNX)* NORBRIDGE.<x> : pin connected to the flash NOR* SV.<x>: pin connected to voltage supervisor* MTR: pin connected MIPI-to voltage monitors-LVDS bridge (TI SN65DSI84)
|-
|'''Ball/pin #'''
|}
===Pinout Table SODIMM J1 ODD pins declaration ===
{| class="wikitable" ! latexfontsize="scriptsize" | A! latexfontsize="scriptsize" | B! latexfontsize="scriptsize" | C! latexfontsize="scriptsize" | D! latexfontsize="scriptsize" | E! latexfontsize="scriptsize" | F! latexfontsize="scriptsize" | G! colspan="2" latexfontsize="scriptsize" | H|-|A|A|A|A|A|A|A|A|A|-|} ===Pinout Table EVEN pins declaration === {| class="wikitable"
! latexfontsize="scriptsize" | Pin
! latexfontsize="scriptsize" | Pin Name
! latexfontsize="scriptsize" | Internal Connections
! latexfontsize="scriptsize" | Ball/pin #
! latexfontsize="scriptsize" |<nowiki>Voltage|domain</nowiki>
! latexfontsize="scriptsize" | Type
! latexfontsize="scriptsize" | Notes
! colspan="2" latexfontsize="scriptsize" | Alternative Functions
|-
|J1.21
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|-
|J1.43|3.3VIN
|INPUT VOLTAGE
| -
|
|-
|J1.65|3.3VIN
|INPUT VOLTAGE
| -
|
|-
|J1.87|3.3VIN
|INPUT VOLTAGE
| -
|
|-
|J1.109|3.3VIN
|INPUT VOLTAGE
| -
|
|-
|J1.1211
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|-
|J1.1413|PMIC_LICELL ETH0_LED1|PMICLAN.LICELLLED1/PME_N1|3017| -NVCC_1V8|SI/O|Must be level translated if used @ 3V3Internally pulled-up to 1.8V during bootstrap
|
|
|-
|J1.1615|CPU_ONOFFETH0_LED2|CPULAN.ONOFFLED2|W2115|NVCC_SNVSNVCC_1V8|I/O|internal pullMust be level translated if used @ 3V3Internally pulled-up 100k to NVCC_SNVS1.8V during bootstrap
|
|
|-
|J1.1817|BOARD_PGOODDGND|DGND
| -
| -
|NVCC_3V3|OG
|
|
|
|-
|J1.2019|BOOT_MODE_SELETH0_TXRX0_P|BOOT MODE SELECTIONLAN.TXRXP_A|2
| -
|NVCC_3V3D|I|internal pull-up to NVCC_3V3
|
|
|-
|J1.2221|CPU_PORnETH0_TXRX0_M|CPULAN.POR_BPMIC.RESETMCUTXRXM_A|W203|NVCC_SNVS-|I/OD|internal pull-up 100k to NVCC_SNVS
|
|
|-
|J1.2423|EXT_RESETETH0_TXRX1_P|MASTER RESETLAN.TXRXP_B|5
| -
|D
|
|
|
|-
|J1.25
|ETH0_TXRX1_M
|LAN.TXRXM_B
|6
| -
|ID|internal pull-up to NVCC_SNVS
|
|
|-
| rowspan="4" |J1.2627| rowspan="4" |SAI3_RXCETH0_TXRX2_P| rowspan="4" |CPULAN.SAI3_RXCTXRXP_C| rowspan="4" |F47| rowspan="4" |NVCC_3V3-| rowspan="4" |I/OD| rowspan="4" ||ALT0|SAI3_RX_BCLK
|-
|ALT1J1.29|ETH0_TXRX2_M|LAN.TXRXM_C|8| -|D||||-|J1.31|ETH0_TXRX3_P|LAN.TXRXP_D|10| -|D|||GPT1_CAPTURE2
|-
|ALT2J1.33|ETH0_TXRX3_M|LAN.TXRXM_D|11| -|D|||SAI5_RX_BCLK
|-
|ALT5J1.35|DGND|DGND| -| -|G|||GPIO4_IO29
|-
| rowspan="4" |J1.2837| rowspan="4" |GPIO1_IO02GPIO1_IO00| rowspan="4" |CPU.GPIO1_IO02GPIO1_IO00| rowspan="4" |R4T6
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |Internally used for SW reset, do not connect
|ALT0
|GPIO1_IO02GPIO1_IO00
|-
|ALT1
|WDOG1_WDOG_BCCM_ENET_PHY_REF_CLK_ROOT
|-
|ALT5
|WDOG1_WDOG_ANYANAMIX_REF_CLK_32K
|-
|ALT7|SJC_DE_B|-|J1.30|DGND|DGND| -|<nowiki>-</nowiki>|G||ALT6|CCM_EXT_CLK1
|-
| rowspan="4" |J1.3239| rowspan="4" |SAI3_RXDGPIO1_IO01| rowspan="4" |CPU.SAI3_RXDGPIO1_IO01| rowspan="4" |F3T7
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |Internally used for ETH PHY reset, do not connect
|ALT0
|SAI3_RX_DATA0GPIO1_IO01
|-
|ALT1
|GPT1_COMPARE1PWM1_OUT
|-
|ALT2ALT5|SAI5_RX_DATA0ANAMIX_REF_CLK_25M
|-
|ALT5ALT6|GPIO4_IO30CCM_EXT_CLK2
|-
| rowspan="3" |J1.3441| rowspan="3" |SAI2_MCLKSPDIF_EXT_CLK| rowspan="3" |CPU.SAI2_MCLKSPDIF_EXT_CLK| rowspan="3" |H5E6
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|SAI2_MCLKSPDIF1_EXT_CLK
|-
|ALT1
|SAI5_MCLKPWM1_OUT
|-
|ALT5
|GPIO4_IO27GPIO5_IO05
|-
| rowspan="43" |J1.3643| rowspan="43" |SAI3_RXFSGPIO1_IO13| rowspan="43" |CPU.SAI3_RXFSGPIO1_IO13| rowspan="43" |G4K6| rowspan="43" |NVCC_3V3| rowspan="43" |I/O| rowspan="43" |Internally used, do not connect
|ALT0
|SAI3_RX_SYNCGPIO1_IO13
|-
|ALT1
|GPT1_CAPTURE1USB1_OTG_OC
|-
|ALT2ALT5|SAI5_RX_SYNCPWM2_OUT
|-
|ALT5J1.45|VDD_PHY_1V8|||||||GPIO4_IO28
|-
| rowspan="43" |J1.3847| rowspan="43" |I2C3_SCLECSPI2_SCLK| rowspan="43" |CPU.I2C3_SCLECSPI2_SCLK| rowspan="43" |G8C5| rowspan="43" |NVCC_3V3| rowspan="43" |I/O| rowspan="43" |
|ALT0
|I2C3_SCLECSPI2_SCLK
|-
|ALT1
|PWM4_OUTUART4_RX
|-
|ALT2ALT5|GPT2_CLKGPIO5_IO10
|-
|ALT5|GPIO5_IO18|-| rowspan="43" |J1.4049| rowspan="43" |SAI3_TXFSECSPI2_MOSI| rowspan="43" |CPU.SAI3_TXFSECSPI2_MOSI| rowspan="43" |G3E5| rowspan="43" |NVCC_3V3| rowspan="43" |I/O| rowspan="43" |
|ALT0
|SAI3_TX_SYNCECSPI2_MOSI
|-
|ALT1
|GPT1_CLK|-|ALT2|SAI5_RX_DATA1UART4_TX
|-
|ALT5
|GPIO4_IO31GPIO5_IO11
|-
| rowspan="3" |J1.4251| rowspan="3" |SPDIF_RXGPIO1_IO08| rowspan="3" |CPU.SPDIF_RXGPIO1_IO08| rowspan="3" |G6N7
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|SPDIF1_INGPIO1_IO08
|-
|ALT1
|PWM2_OUTENET1_1588_EVENT0_IN
|-
|ALT5
|GPIO5_IO04USDHC2_RESET_B
|-
| rowspan="3" |J1.4453| rowspan="3" |SPDIF_TXGPIO1_IO09| rowspan="3" |CPU.SPDIF_TXGPIO1_IO09| rowspan="3" |F6M7
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|SPDIF1_OUTGPIO1_IO09
|-
|ALT1
|PWM3_OUTENET1_1588_EVENT0_OUT
|-
|ALT5
|GPIO5_IO03SDMA2_EXT_EVENT0
|-
| rowspan="43" |J1.4655| rowspan="43" |SAI3_MCLKECSPI2_MISO| rowspan="43" |CPU.SAI3_MCLKECSPI2_MISO| rowspan="43" |D3B5| rowspan="43" |NVCC_3V3| rowspan="43" |I/O| rowspan="43" |
|ALT0
|SAI3_MCLKECSPI2_MISO
|-
|ALT1
|PWM4_OUTUART4_CTS_B
|-
|ALT2ALT5|SAI5_MCLKGPIO5_IO12
|-
|ALT5J1.57|DGND |DGND| -| -|G|||GPIO5_IO02
|-
| rowspan="43" |J1.4859| rowspan="43" |I2C3_SDAECSPI2_SS0| rowspan="43" |CPU.I2C3_SDAECSPI2_SS0| rowspan="43" |E9A5| rowspan="43" |NVCC_3V3| rowspan="43" |I/O| rowspan="43" |
|ALT0
|I2C3_SDAECSPI2_SS0
|-
|ALT1
|PWM3_OUTUART4_RTS_B
|-
|ALT2ALT5|GPT3_CLKGPIO5_IO13|-| rowspan="3" |J1.61| rowspan="3" |GPIO1_IO05| rowspan="3" |CPU.GPIO1_IO05| rowspan="3" |P7| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" |Internally used for MIPI-to-LVDS interrupt, do not connectPulled-up to NVCC_3V3|ALT0|GPIO1_IO05|-|ALT1|M4_NMI
|-
|ALT5
|GPIO5_IO19CCM_PMIC_READY
|-
| rowspan="43" |J1.5063| rowspan="43" |SAI3_TXCI2C2_SCL| rowspan="43" |CPU.SAI3_TXCI2C2_SCL| rowspan="43" |C4G7| rowspan="43" |NVCC_3V3| rowspan="43" |I/O| rowspan="43" |
|ALT0
|SAI3_TX_BCLKI2C2_SCL
|-
|ALT1
|GPT1_COMPARE2|-|ALT2|SAI5_RX_DATA2ENET1_1588_EVENT1_IN
|-
|ALT5
|GPIO5_IO00GPIO5_IO16
|-
| rowspan="43" |J1.5265| rowspan="43" |SAI3_TXDI2C2_SDA| rowspan="43" |CPU.SAI3_TXDI2C2_SDA| rowspan="43" |C3F7| rowspan="43" |NVCC_3V3| rowspan="43" |I/O| rowspan="43" |
|ALT0
|SAI3_TX_DATA0I2C2_SDA
|-
|ALT1
|GPT1_COMPARE3|-|ALT2|SAI5_RX_DATA3ENET1_1588_EVENT1_OUT
|-
|ALT5
|GPIO5_IO01GPIO5_IO17
|-
| rowspan="24" |J1.5467| rowspan="24" |GPIO1_IO10GPIO1_IO06| rowspan="24" |CPU.GPIO1_IO10GPIO1_IO06| rowspan="24" |M7N5| rowspan="24" |NVCC_3V3| rowspan="24" |I/O| rowspan="24" |Internally used for ETH PHY interruptMIPI-to-LVDS enable, do not connect
|ALT0
|GPIO1_IO10GPIO1_IO06
|-
|ALT1
|USB1_OTG_IDENET1_MDC
|-
|J1.56|DGND|DGND| -|<nowiki>-</nowiki>|G||ALT5|USDHC1_CD_B
|-
| rowspan="4" |J1.58| rowspan="4" |SAI5_MCLK| rowspan="4" |CPU.SAI5_MCLK| rowspan="4" |K4| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0ALT6|SAI5_MCLKCCM_EXT_CLK3
|-
|ALT1|SAI1_TX_BCLK|-|ALT2|SAI4_MCLK|-|ALT5|GPIO3_IO25|-| rowspan="43" |J1.6069| rowspan="43" |GPIO1_IO15SAI2_RXC| rowspan="43" |CPU.GPIO1_IO15SAI2_RXC| rowspan="43" |J6H3| rowspan="43" |NVCC_3V3| rowspan="43" |I/O| rowspan="43" |
|ALT0
|GPIO1_IO15SAI2_RX_BCLK
|-
|ALT1
|USB2_OTG_OCSAI5_TX_BCLK
|-
|ALT5
|PWM4_OUTGPIO4_IO22
|-
|ALT6|CCM_CLKO2|-| rowspan="3" |J1.6271| rowspan="3" |SAI5_RXFSSAI2_RXFS| rowspan="3" |CPU.SAI5_RXFSSAI2_RXFS| rowspan="3" |N4J4
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|SAI5_RX_SYNCSAI2_RX_SYNC
|-
|ALT1
|SAI1_TX_DATA0SAI5_TX_SYNC
|-
|ALT5
|GPIO3_IO19GPIO4_IO21
|-
|J1.73|DGND |DGND| -| -|G||||-| rowspan="32" |J1.6475| rowspan="32" |SAI5_RXCSD2_DATA0| rowspan="32" |CPU.SAI5_RXCSD2_DATA0| rowspan="32" |L5N22| rowspan="32" |NVCC_3V3| rowspan="32" |I/O| rowspan="32" |
|ALT0
|SAI5_RX_BCLK|-|ALT1|SAI1_TX_DATA1USDHC2_DATA0
|-
|ALT5
|GPIO3_IO20GPIO2_IO15
|-
| rowspan="32" |J1.6677| rowspan="32" |SAI2_TXCSD2_DATA1| rowspan="32" |CPU.SAI2_TXCSD2_DATA1| rowspan="32" |J5N21| rowspan="32" |NVCC_3V3| rowspan="32" |I/O| rowspan="32" |
|ALT0
|SAI2_TX_BCLK|-|ALT1|SAI5_TX_DATA2USDHC2_DATA1
|-
|ALT5
|GPIO4_IO25GPIO2_IO16
|-
| rowspan="32" |J1.6879| rowspan="32" |SAI2_TXD0SD2_DATA2| rowspan="32" |CPU.SAI2_TXD0SD2_DATA2| rowspan="32" |G5P22| rowspan="32" |NVCC_3V3| rowspan="32" |I/O| rowspan="32" |
|ALT0
|SAI2_TX_DATA0USDHC2_DATA2|-|ALT5|GPIO2_IO17
|-
|ALT1rowspan="2" |J1.81| rowspan="2" |SD2_DATA3| rowspan="2" |CPU.SD2_DATA03| rowspan="2" |P21| rowspan="2" |NVCC_3V3| rowspan="2" |I/O| rowspan="2" ||ALT0|SAI5_TX_DATA3USDHC2_DATA3
|-
|ALT5
|GPIO4_IO26GPIO2_IO18
|-
| rowspan="32" |J1.7083| rowspan="32" |SAI2_TXFSSD2_CMD| rowspan="32" |CPU.SAI2_TXFSSD2_CMD| rowspan="32" |H4M22| rowspan="32" |NVCC_3V3| rowspan="32" |I/O| rowspan="32" |
|ALT0
|SAI2_TX_SYNC|-|ALT1|SAI5_TX_DATA1USDHC2_CMD
|-
|ALT5
|GPIO4_IO24GPIO2_IO14
|-
| rowspan="2" |J1.85| rowspan="2" |SD2_CLK| rowspan="2" |CPU.SD2_CLK| rowspan="2" |L22| rowspan="2" |NVCC_3V3| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC2_CLK|-|ALT5|GPIO2_IO13|-|J1.87|DGND |DGND| -| -|G||||-| rowspan="3" |J1.7289| rowspan="3" |SAI2_RXD0UART3_TXD| rowspan="3" |CPU.SAI2_RXD0UART3_TXD| rowspan="3" |H6B7
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|SAI2_RX_DATA0UART3_TX
|-
|ALT1
|SAI5_TX_DATA0UART1_RTS_B
|-
|ALT5
|GPIO4_IO23GPIO5_IO27
|-
| rowspan="3" |J1.7491| rowspan="3" |SAI5_RXD0UART3_RXD| rowspan="3" |CPU.SAI5_RXD0UART3_RXD| rowspan="3" |M5A6
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|SAI5_RX_DATA0 UART3_RX
|-
|ALT1
|SAI1_TX_DATA2UART1_CTS_B
|-
|ALT5
|GPIO3_IO21GPIO5_IO26|-| rowspan="54" |J1.7693| rowspan="54" |SAI5_RXD1UART4_TXD| rowspan="54" |CPU.SAI5_RXD1UART4_TXD| rowspan="54" |L4D7| rowspan="54" |NVCC_3V3| rowspan="54" |I/O| rowspan="54" ||ALT0|SAI5_RX_DATA1UART4_TX
|-
|ALT1
|SAI1_TX_DATA3UART2_RTS_B
|-
|ALT2
|SAI1_TX_SYNC|-|ALT3|SAI5_TX_SYNCPCIE2_CLKREQ_B
|-
|ALT5
|GPIO3_IO212GPIO5_IO29
|-
| rowspan="54" |J1.7895| rowspan="54" |SAI5_RXD2UART4_RXD| rowspan="54" |CPU.SAI5_RXD2UART4_RXD| rowspan="54" |M4C6| rowspan="54" |NVCC_3V3| rowspan="54" |I/O| rowspan="54" |
|ALT0
|SAI5_RX_DATA2UART4_RX
|-
|ALT1
|SAI1_TX_DATA4UART2_CTS_B
|-
|ALT2
|SAI1_TX_SYNCPCIE1_CLKREQ_B|-|ALT5|GPIO5_IO28
|-
|ALT3rowspan="2" |J1.97| rowspan="2" |SD2_WP| rowspan="2" |CPU.SD2_WP| rowspan="2" |M21| rowspan="2" |NVCC_3V3| rowspan="2" |I/O| rowspan="2" ||ALT0|SAI5_TX_BCLKUSDHC2_WP
|-
|ALT5
|GPIO3_IO23GPIO2_IO20
|-
| rowspan="52" |J1.8099| rowspan="52" |SAI5_RXD3SD2_RST_B| rowspan="52" |CPU.SAI5_RXD3SD2_RESET_B| rowspan="52" |K5R22| rowspan="52" |NVCC_3V3| rowspan="52" |I/O| rowspan="52" |
|ALT0
|SAI5_RX_DATA3|-|ALT1|SAI1_TX_DATA5|-|ALT2|SAI1_TX_SYNC|-|ALT3|SAI5_TX_DATA0USDHC2_RESET_B
|-
|ALT5
|GPIO3_IO24GPIO2_IO19
|-
|J1.82101|DGNDHDMI_DDC_SCL|DGNDCPU.HDMI_DDC_SCL| -R3|<nowiki>-</nowiki>VDD_PHY_1V8|GI/O
|
|
|
|-
|J1.84103|CLK2_NHDMI_DDC_SDA|CPU.CLK2_NHDMI_DDC_SDA|T22P3|VDDA_1V8VDD_PHY_1V8|DI/O
|
|
|
|-
|J1.86105|CLK2_PHDMI_AUX_N|CPU.CLK2_PHDMI_AUX_N|U22V2|VDDA_1V8-
|D
|connected with capacitor in series
|
|
|-
|J1.88107|PCIE1_REF_CLKNHDMI_AUX_P|CPU.PCIE1_REF_PAD_CLK_NHDMI_AUX_P|K24V1|VDD_PHY_3V3-
|D
|connected with capacitor in series
|
|
|-
|J1.90109|PCIE1_REF_CLKPDGND |CPU.PCIE1_REF_PAD_CLK_PDGND|K25-|VDD_PHY_3V3-|DG
|
|
|
|-
|J1.92111|PCIE1_RXNHDMI_TX_M_LN_3|CPU.PCIE1_RXN_NHDMI_TX_M_LN_3|H24M2|VDD_PHY_3V3-
|D
|connected with capacitor in series
|
|
|-
|J1.94113|PCIE1_RXPHDMI_TX_P_LN_3|CPU.PCIE1_RXN_PHDMI_TX_P_LN_3|H25M1|VDD_PHY_3V3-
|D
|connected with capacitor in series
|
|
|-
|J1.96115|PCIE1_TXNHDMI_TX_M_LN_0|CPU.PCIE1_TXN_NHDMI_TX_M_LN_0|J24T2|VDD_PHY_3V3-
|D
|connected with capacitor in series
|
|
|-
|J1.98117|PCIE1_TXPHDMI_TX_P_LN_0|CPU.PCIE1_TXN_PHDMI_TX_P_LN_0|J25T1|VDD_PHY_3V3-
|D
|connected with capacitor in series
|
|
|-
|J1.100119|DGNDHDMI_TX_M_LN_1|DGNDCPU.HDMI_TX_M_LN_1|U1
| -
|<nowiki>-</nowiki>|GD|connected with capacitor in series
|
|
|-
|J1.102121|CSI1_CLK_NHDMI_TX_P_LN_1|CPU.MIPI_CSI1_CLK_NHDMI_TX_P_LN_1|A22U2
| -
|D
|connected with capacitor in series
|
|
|-
|J1.104123|CSI1_CLK_PHDMI_TX_M_LN_2|CPU.MIPI_CSI1_CLK_PHDMI_TX_M_LN_2|B22N1
| -
|D
|connected with capacitor in series
|
|
|-
|J1.106125|CSI1_D0_NHDMI_TX_P_LN_2|CPU.MIPI_CSI1_D0_NHDMI_TX_P_LN_2|A23N2
| -
|D
|connected with capacitor in series
|
|
|-
|J1.127
|HDMI_CEC
|CPU.HDMI_CEC
|W3
|VDD_PHY_1V8
|I/O
|
|
|
|-
|J1.108129|CSI1_D0_PHDMI_HPD|CPU.MIPI_CSI1_D0_PHDMI_HPD|B23W2| -VDD_PHY_1V8|DI/O
|
|
|
|-
|J1.110131|CSI1_D1_NDGND |CPU.MIPI_CSI1_D1_NDGND|C22-
| -
|DG
|
|
|
|-
|J1.112133|CSI1_D1_PLVDS0_CLK_N|CPUBRIDGE.MIPI_CSI1_D1_PA_CLKN|D22F9
| -
|D
|
|-
|J1.114135|CSI1_D2_NLVDS0_CLK_P|CPUBRIDGE.MIPI_CSI1_D2_NA_CLKP|B24F8
| -
|D
|
|-
|J1.116137|CSI1_D2_PLVDS0_TX0_N|CPUBRIDGE.MIPI_CSI1_D2_PA_Y0N|C23C9
| -
|D
|
|-
|J1.118139|CSI1_D3_NLVDS0_TX0_P|CPUBRIDGE.MIPI_CSI1_D3_NA_Y0P|C21C8
| -
|D
|
|-
|J1.120141|CSI1_D3_PLVDS0_TX1_N|CPUBRIDGE.MIPI_CSI1_D3_PA_Y1N|D21D9| -|D||||-|J1.143|LVDS0_TX1_P|BRIDGE.A_Y1P|D8
| -
|D
|
|-
|J1.122145|DGNDLVDS0_TX2_N|DGNDBRIDGE.A_Y2N|E9
| -
|<nowiki>-</nowiki>|GD
|
|
|
|-
|J1.124(NAND on board)147|NAND_DQSLVDS0_TX2_P|CPUBRIDGE.NAND_DQSA_Y2P|M20E8|NVCC_3V3-|I/OD|Internally used for NAND, do not connect
|
|
|-
| rowspan="3" |J1.124(eMMC on board)149| rowspan="3" |NAND_DQSLVDS0_TX3_N| rowspan="3" |CPUBRIDGE.NAND_DQSA_Y3N| rowspan="3" |M20G9| rowspan="3" |NVCC_3V3-| rowspan="3" |I/OD| rowspan="3" ||ALT0|RAWNAND_DQS
|-
|ALT1J1.151|LVDS0_TX3_P|BRIDGE.A_Y3P|G8| -|D|||QSPI_A_DQS
|-
|ALT5J1.153|DGND |DGND| -| -|G|||GPIO3_IO14
|-
|J1.126(NAND on board)155|NAND_ALELVDS1_CLK_N|CPUBRIDGE.NAND_ALEB_CLKN|G19A6|NVCC_3V3-|I/OD|Internally used for NAND, do not connect
|
|
|-
| rowspan="3" |J1.126(eMMC on board)157| rowspan="3" |NAND_ALELVDS1_CLK_P| rowspan="3" |CPUBRIDGE.NAND_ALEB_CLKP| rowspan="3" |G19B6| rowspan="3" |NVCC_3V3-| rowspan="3" |I/OD| rowspan="3" ||ALT0|RAWNAND_ALE
|-
|ALT1J1.159|LVDS1_TX0_N|BRIDGE.B_Y0N|A3| -|D|||QSPI_A_SCLK
|-
|ALT5J1.161|LVDS1_TX0_P|BRIDGE.B_Y0P|B3| -|D|||GPIO3_IO00
|-
| rowspan="2" |J1.128(NAND on board)163| rowspan="2" |SD1_CLKLVDS1_TX1_N| rowspan="2" |CPUBRIDGE.SD1_CLKB_Y1N| rowspan="2" |L25A4| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)-| rowspan="2" |I/OD| rowspan="2" ||ALT0|USDHC1_CLK
|-
|ALT5J1.165|LVDS1_TX1_P|BRIDGE.B_Y1P|B4| -|D|||GPIO2_IO00
|-
| rowspan="3" |J1.128(eMMC on board)167| rowspan="3" |NAND_CE0_BLVDS1_TX2_N| rowspan="3" |CPUBRIDGE.NAND_CE0_BB_Y2N| rowspan="3" |H19A5| rowspan="3" |NVCC_3V3-| rowspan="3" |I/OD| rowspan="3" ||ALT0|RAWNAND_CE0_B
|-
|ALT1J1.169|LVDS1_TX2_P|BRIDGE.B_Y2P|B5| -|D|||QSPI_A_SS0_B
|-
|ALT5J1.171|LVDS1_TX3_N|BRIDGE.B_Y3N|A7| -|D||||-|J1.173|LVDS1_TX3_P|BRIDGE.B_Y3P|B7| -|D||||-|J1.175|DGND |DGND| -| -|G|||GPIO3_IO01
|-
| rowspan="2" |J1.130(NAND on board)177| rowspan="2" |SD1_CMDSD2_CD_B| rowspan="2" |CPU.SD1_CMDSD2_CD_B| rowspan="2" |L24L21
| rowspan="2" |NVCC_3V3
(NVCC_1V8 on request)
| rowspan="2" |I/O
| rowspan="2" |
|ALT0
|USDHC1_CMDUSDHC2_CD_B
|-
|ALT5
|GPIO2_IO01GPIO2_IO12
|-
| rowspan="3" |J1.130(eMMC on board)179| rowspan="3" |NAND_CE1_BECSPI1_SS0| rowspan="3" |CPU.NAND_CE1_BECSPI1_SS0| rowspan="3" |G21D4
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|RAWNAND_CE1_BECSPI1_SS0
|-
|ALT1
|QSPI_A_SS1_BUART3_RTS_B
|-
|ALT5
|GPIO3_IO02GPIO5_IO09
|-
| rowspan="23" |J1.132(NAND on board)181| rowspan="23" |SD1_RST_BECSPI1_SCLK| rowspan="23" |CPU.SD1_RST_BECSPI1_SCLK| rowspan="23" |R24D5| rowspan="23" |NVCC_3V3(NVCC_1V8 on request)| rowspan="23" |I/O| rowspan="23" |
|ALT0
|USDHC1_RESET_BECSPI1_SCLK|-|ALT1|UART3_RX
|-
|ALT5
|GPIO2_IO10GPIO5_IO06
|-
| rowspan="3" |J1.132(eMMC on board)183| rowspan="3" |NAND_CE2_BECSPI1_MISO| rowspan="3" |CPU.NAND_CE2_BECSPI1_MISO| rowspan="3" |F21B4
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|RAWNAND_CE2_BECSPI1_MISO
|-
|ALT1
|QSPI_B_SS0_BUART3_CTS_B
|-
|ALT5
|GPIO3_IO03GPIO5_IO08|-| rowspan="3" |J1.185| rowspan="3" |GPIO1_IO03| rowspan="3" |CPU.GPIO1_IO03| rowspan="3" |P4| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|GPIO1_IO03
|-
| rowspan="2" |J1.134(NAND on board)| rowspan="2" |SD1_STROBE| rowspan="2" |CPU.SD1_STROBE| rowspan="2" |T24| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" ||ALT0ALT1|USDHC1_STROBEUSDHC1_VSELECT
|-
|ALT5
|GPIO2_IO11SDMA1_EXT_EVENT0
|-
| rowspan="3" |J1.134(eMMC on board)187| rowspan="3" |NAND_CE3_BUART2_TXD| rowspan="3" |CPU.NAND_CE3_BUART2_TXD| rowspan="3" |H20D6
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |used as default Linux console
|ALT0
|RAWNAND_CE3_BUART2_TX
|-
|ALT1
|QSPI_B_SS1_BECSPI3_SS0
|-
|ALT5
|GPIO3_IO034|-|J1.136(NAND on board)|NAND_CLE|CPU.NAND_CLE|H21|NVCC_3V3|I/O|Internally used for NAND, do not connect||GPIO5_IO25
|-
| rowspan="3" |J1.136(eMMC on board)189| rowspan="3" |NAND_CLEUART2_RXD| rowspan="3" |CPU.NAND_CLEUART2_RXD| rowspan="3" |H21B6
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |used as default Linux console
|ALT0
|RAWNAND_CLEUART2_RXD
|-
|ALT1
|QSPI_B_SCLKECSPI3_MISO
|-
|ALT5
|GPIO3_IO05GPIO5_IO24
|-
| rowspan="23" |J1.138(NAND on board)191| rowspan="23" |SD1_DATA0UART1_TXD| rowspan="23" |CPU.SD1_DATA0UART1_TXD| rowspan="23" |M25A7| rowspan="23" |NVCC_3V3(NVCC_1V8 on request)| rowspan="23" |I/O| rowspan="23" |
|ALT0
|USDHC1_DATA0UART1_TX|-|ALT1|ECSPI3_MOSI
|-
|ALT5
|GPIO2_IO02GPIO5_IO23
|-
| rowspan="3" |J1.138(eMMC on board)193| rowspan="3" |NAND_DATA00UART1_RXD| rowspan="3" |CPU.NAND_DATA00UART1_RXD| rowspan="3" |G20C7
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|RAWNAND_DATA00UART1_RXD
|-
|ALT1
|QSPI_A_DATA0ECSPI3_SCLK
|-
|ALT5
|GPIO3_IO06GPIO5_IO22
|-
| rowspan="23" |J1.140(NAND on board)195| rowspan="23" |SD1_DATA1ECSPI1_MOSI| rowspan="23" |CPU.SD1_DATA1ECSPI1_MOSI| rowspan="23" |M24A4| rowspan="23" |NVCC_3V3(NVCC_1V8 on request)| rowspan="23" |I/O| rowspan="23" |
|ALT0
|USDHC1_DATA1ECSPI1_MOSI|-|ALT1|UART3_TX|-|ALT5|GPIO5_IO07|-| rowspan="4" |J1.197| rowspan="4" |GPIO1_IO14| rowspan="4" |CPU.GPIO1_IO14| rowspan="4" |K7| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|GPIO1_IO14|-|ALT1|USB2_OTG_PWR
|-
|ALT5
|GPIO2_IO0PWM3_OUT|-|ALT6|CCM_CLKO1
|-
| rowspan="3" |J1.140(eMMC on board)199| rowspan="3" |NAND_DATA01GPIO1_IO04| rowspan="3" |CPU.NAND_DATA01GPIO1_IO04| rowspan="3" |J20P5
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|RAWNAND_DATA01GPIO1_IO04
|-
|ALT1
|QSPI_A_DATA1USDHC2_VSELECT
|-
|ALT5
|GPIO3_IO07SDMA1_EXT_EVENT1
|-
| rowspan="23" |J1.142(NAND on board)201| rowspan="23" |SD1_DATA2GPIO1_IO12| rowspan="23" |CPU.SD1_DATA2GPIO1_IO12| rowspan="23" |N25L7| rowspan="23" |NVCC_3V3(NVCC_1V8 on request)| rowspan="23" |I/O| rowspan="23" |
|ALT0
|USDHC1_DATA2|-|ALT5|GPIO2_IO04|-| rowspan="3" |J1.142(eMMC on board)| rowspan="3" |NAND_DATA02| rowspan="3" |CPU.NAND_DATA02| rowspan="3" |H22| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_DATA02GPIO1_IO12
|-
|ALT1
|QSPI_A_DATA2USB1_OTG_PWR
|-
|ALT5
|GPIO3_IO08SDMA2_EXT_EVENT1
|-
| rowspan="2" |J1.144(NAND on board)203| rowspan="2" |SD1_DATA3DGND | rowspan="2" |CPU.SD1_DATA3DGND| rowspan="2" |P25-| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)-| rowspan="2" |I/OG| rowspan="2" ||ALT0|USDHC1_DATA3
|-
|ALT5} ==SODIMM J1 EVEN pins declaration == {| class="wikitable" ! latexfontsize="scriptsize" | Pin ! latexfontsize="scriptsize" | Pin Name! latexfontsize="scriptsize" | Internal Connections ! latexfontsize="scriptsize" | Ball/pin # ! latexfontsize="scriptsize" | Voltage domain ! latexfontsize="scriptsize" | Type ! latexfontsize="scriptsize" | Notes! colspan="2" latexfontsize="scriptsize" |GPIO2_IO05Alternative Functions
|-
| rowspan="3" |J1.144(eMMC on board)| rowspan="3" |NAND_DATA03| rowspan="3" |CPU.NAND_DATA03| rowspan="3" |J21| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_DATA03|-|ALT1|QSPI_A_DATA3|-|ALT5|GPIO3_IO09|-|J1.1462
|DGND
|DGND
|
|-
| rowspan="2" |J1.148(NAND on board)4| rowspan="2" |SD1_DATA43.3VIN | rowspan="2" |CPU.SD1_DATA4INPUT VOLTAGE| rowspan="2" |N24-| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)3.3VIN| rowspan="2" |I/OS| rowspan="2" ||ALT0|USDHC1_DATA4
|-
|ALT5J1.6|3.3VIN |INPUT VOLTAGE| -|3.3VIN|S|||GPIO2_IO06
|-
| rowspan="3" |J1.148(eMMC on board)8| rowspan="3" |NAND_DATA04.3VIN | rowspan="3" |CPU.NAND_DATA04INPUT VOLTAGE| rowspan="3" |L20-| rowspan="3" |NVCC_3V3.3VIN| rowspan="3" |I/OS| rowspan="3" ||ALT0|RAWNAND_DATA04
|-
|ALT1J1.10|3.3VIN |INPUT VOLTAGE| -|3.3VIN|S|||QSPI_B_DATA0
|-
|ALT5J1.12|DGND|DGND| -|<nowiki>-</nowiki>|G|||GPIO3_IO10
|-
| rowspan="2" |J1.150(NAND on board)14| rowspan="2" |SD1_DATA5PMIC_LICELL | rowspan="2" |CPUPMIC.SD1_DATA5LICELL| rowspan="2" |P2430| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)-| rowspan="2" |I/OS| rowspan="2" ||ALT0|USDHC1_DATA5
|-
|ALT5J1.16|CPU_ONOFF|CPU.ONOFF|W21|NVCC_SNVS|I|internal pull-up 100k to NVCC_SNVS||GPIO2_IO07
|-
| rowspan="3" |J1.150(eMMC on board)18| rowspan="3" |NAND_DATA05BOARD_PGOOD| rowspan="3" |CPU.NAND_DATA05-| rowspan="3" |J22-| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_DATA05
|-
|ALT1J1.20|BOOT_MODE_SEL|BOOT MODE SELECTION| -|NVCC_3V3|I|internal pull-up to NVCC_3V3||QSPI_B_DATA1
|-
|ALT5J1.22|CPU_PORn|CPU.POR_BPMIC.RESETMCU|W203|NVCC_SNVS|I/O|internal pull-up 100k to NVCC_SNVS||GPIO3_IO11
|-
|J1.24|EXT_RESET|MASTER RESET| -| -|I|internal pull-up to NVCC_SNVS|||-| rowspan="24" |J1.152(NAND on board)26| rowspan="24" |SD1_DATA6SAI3_RXC| rowspan="24" |CPU.SD1_DATA6SAI3_RXC| rowspan="24" |R25F4| rowspan="24" |NVCC_3V3(NVCC_1V8 on request)| rowspan="24" |I/O| rowspan="24" |
|ALT0
|USDHC1_DATA6SAI3_RX_BCLK|-|ALT1|GPT1_CAPTURE2|-|ALT2|SAI5_RX_BCLK
|-
|ALT5
|GPIO2_IO08GPIO4_IO29
|-
| rowspan="34" |J1.152(eMMC on board)28| rowspan="34" |NAND_DATA06GPIO1_IO02| rowspan="34" |CPU.NAND_DATA06GPIO1_IO02| rowspan="34" |L19R4| rowspan="34" |NVCC_3V3| rowspan="34" |I/O| rowspan="34" |Internally used for SW reset, do not connect
|ALT0
|RAWNAND_DATA06GPIO1_IO02
|-
|ALT1
|QSPI_B_DATA2WDOG1_WDOG_B
|-
|ALT5
|GPIO3_IO12WDOG1_WDOG_ANY
|-
| rowspan="2" |J1.154(NAND on board)| rowspan="2" |SD1_DATA7| rowspan="2" |CPU.SD1_DATA7| rowspan="2" |T25| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" ||ALT0ALT7|USDHC1_DATA7SJC_DE_B
|-
|ALT5J1.30|DGND|DGND| -|<nowiki>-</nowiki>|G|||GPIO2_IO09
|-
| rowspan="34" |J1.154(eMMC on board)32| rowspan="34" |NAND_DATA07SAI3_RXD| rowspan="34" |CPU.NAND_DATA07SAI3_RXD| rowspan="34" |M19F3| rowspan="34" |NVCC_3V3| rowspan="34" |I/O| rowspan="34" |
|ALT0
|RAWNAND_DATA07SAI3_RX_DATA0
|-
|ALT1
|QSPI_B_DATA3GPT1_COMPARE1|-|ALT2|SAI5_RX_DATA0
|-
|ALT5
|GPIO3_IO13GPIO4_IO30
|-
|J1.156(NAND on board)|NAND_RE_B|CPU.NAND_RE_B|K19|NVCC_3V3|I/O|Internally used for NAND, do not connect|||-| rowspan="3" |J1.156(eMMC on board)34| rowspan="3" |NAND_RE_BSAI2_MCLK| rowspan="3" |CPU.NAND_RE_BSAI2_MCLK| rowspan="3" |K19H5
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|RAWNAND_RE_BSAI2_MCLK
|-
|ALT1
|QSPI_B_DQSSAI5_MCLK
|-
|ALT5
|GPIO3_IO15GPIO4_IO27
|-
| rowspan="4" |J1.15836(NAND on board)| rowspan="4" |SAI3_RXFS|NAND_READY_Browspan="4" |CPU.NAND_READY_BSAI3_RXFS|K20rowspan="4" |G4| rowspan="4" |NVCC_3V3| rowspan="4" |I/O|Internally used for NAND, do not connectrowspan="4" ||ALT0|SAI3_RX_SYNC|-|ALT1|GPT1_CAPTURE1
|-
| rowspan="2" |J1.158(eMMC on board)| rowspan="2" |NAND_READY_B| rowspan="2" |CPU.NAND_READY_B| rowspan="2" |K20| rowspan="2" |NVCC_3V3| rowspan="2" |I/O| rowspan="2" ||ALT0ALT2|RAWNAND_READY_BSAI5_RX_SYNC
|-
|ALT5
|GPIO3_IO16GPIO4_IO28
|-
| rowspan="4" |J1.16038(NAND on board)| rowspan="4" |I2C3_SCL|NAND_WE_Browspan="4" |CPU.NAND_WE_BI2C3_SCL|K22rowspan="4" |G8| rowspan="4" |NVCC_3V3| rowspan="4" |I/O|Internally used for NAND, do not connectrowspan="4" ||ALT0|I2C3_SCL|-|ALT1|PWM4_OUT
|-
| rowspan="2" |J1.160(eMMC on board)| rowspan="2" |NAND_WE_B| rowspan="2" |CPU.NAND_WE_B| rowspan="2" |K22| rowspan="2" |NVCC_3V3| rowspan="2" |I/O| rowspan="2" ||ALT0ALT2|RAWNAND_WE_BGPT2_CLK
|-
|ALT5
|GPIO3_IO17GPIO5_IO18
|-
| rowspan="4" |J1.16240(NAND on board)| rowspan="4" |SAI3_TXFS|NAND_WP_Browspan="4" |CPU.NAND_WP_BSAI3_TXFS|K21rowspan="4" |G3| rowspan="4" |NVCC_3V3| rowspan="4" |I/O|Internally used for NAND, do not connectrowspan="4" ||ALT0|SAI3_TX_SYNC|-|ALT1|GPT1_CLK|-|ALT2|SAI5_RX_DATA1|-|ALT5|GPIO4_IO31
|-
| rowspan="23" |J1.162(eMMC on board)42| rowspan="23" |NAND_WP_BSPDIF_RX| rowspan="23" |CPU.NAND_WP_BSPDIF_RX| rowspan="23" |K21G6| rowspan="23" |NVCC_3V3| rowspan="23" |I/O| rowspan="23" |
|ALT0
|RAWNAND_WP_BSPDIF1_IN|-|ALT1|PWM2_OUT
|-
|ALT5
|GPIO3_IO18GPIO5_IO04
|-
| rowspan="3" |J1.16444|DGNDrowspan="3" |SPDIF_TX|DGNDrowspan="3" |CPU.SPDIF_TX| -rowspan="3" |F6| rowspan="3" |NVCC_3V3|<nowiki>-<rowspan="3" |I/nowiki>O| rowspan="3" ||ALT0|GSPDIF1_OUT|-|ALT1|PWM3_OUT
|-
|J1.166|CLK1_N|CPU.CLK1_N|T23||D||ALT5|GPIO5_IO03
|-
| rowspan="4" |J1.16846|CLK1_Prowspan="4" |SAI3_MCLK| rowspan="4" |CPU.CLK1_PSAI3_MCLK|R23rowspan="4" |D3|rowspan="4" |NVCC_3V3|Drowspan="4" |I/O| rowspan="4" ||ALT0|SAI3_MCLK
|-
|J1.170|USB2_RXN|CPU.USB2_RX_N|B8||D||ALT1|PWM4_OUT
|-
|J1.172|USB2_RXP|CPU.USB2_RX_P|A8||D||ALT2|SAI5_MCLK
|-
|ALT5|GPIO5_IO02|-| rowspan="4" |J1.17448|USB2_TXNrowspan="4" |I2C3_SDA| rowspan="4" |CPU.USB2_TX_NI2C3_SDA|B9rowspan="4" |E9|rowspan="4" |NVCC_3V3|Drowspan="4" |I/O| rowspan="4" ||ALT0|I2C3_SDA
|-
|J1.176|USB2_TXP|CPU.USB2_TX_P|A9||D||ALT1|PWM3_OUT
|-
|J1.178|USB1_RXN|CPU.USB1_RX_N|B12||D||ALT2|GPT3_CLK
|-
|J1.180|USB1_RXP|CPU.USB1_RX_P|A12||D||ALT5|GPIO5_IO19
|-
| rowspan="4" |J1.18250|USB1_TXNrowspan="4" |SAI3_TXC| rowspan="4" |CPU.USB1_TX_NSAI3_TXC|B13rowspan="4" |C4|rowspan="4" |NVCC_3V3|Drowspan="4" |I/O| rowspan="4" ||ALT0|SAI3_TX_BCLK
|-
|J1.184|USB1_TXP|CPU.USB1_TX_P|A13||D||ALT1|GPT1_COMPARE2
|-
|J1.186|USB1_VBUS|CPU.USB1_VBUS|D14| -|S||ALT2|SAI5_RX_DATA2
|-
|J1.188|USB2_VBUS|CPU.USB2_VBUS|D9| -|S||ALT5|GPIO5_IO00
|-
| rowspan="4" |J1.19052| rowspan="4" |SAI3_TXD| rowspan="4" |CPU.SAI3_TXD| rowspan="4" |C3| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|SAI3_TX_DATA0|-|ALT1|GPT1_COMPARE3|-|ALT2|SAI5_RX_DATA3|-|ALT5|GPIO5_IO01|-| rowspan="2" |J1.54| rowspan="2" |GPIO1_IO10| rowspan="2" |CPU.GPIO1_IO10| rowspan="2" |M7| rowspan="2" |NVCC_3V3| rowspan="2" |I/O| rowspan="2" |Internally used for ETH PHY interrupt, do not connect|ALT0|GPIO1_IO10|-|ALT1|USB1_OTG_ID|-|J1.56|DGND
|DGND
| -
|
|-
| rowspan="4" |J1.19258|USB1_IDrowspan="4" |SAI5_MCLK| rowspan="4" |CPU.USB1_IDSAI5_MCLK|C14rowspan="4" |K4|VDD_PHY_3V3rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|SAI5_MCLK
|-
|J1.194|USB2_ID|CPU.USB2_ID|C9|VDD_PHY_3V3|I||ALT1|SAI1_TX_BCLK
|-
|J1.196|USB1_DN|CPU.USB1_DN|B14| -|D||ALT2|SAI4_MCLK
|-
|ALT5|GPIO3_IO25|-| rowspan="4" |J1.19860|USB1_DProwspan="4" |GPIO1_IO15| rowspan="4" |CPU.USB1_DPGPIO1_IO15|A14rowspan="4" |J6| -rowspan="4" |NVCC_3V3|Drowspan="4" |I/O| rowspan="4" ||ALT0|GPIO1_IO15
|-
|J1.200|USB2_DP|CPU.USB2_DP|A10| -|D||ALT1|USB2_OTG_OC
|-
|J1.202|USB2_DN|CPU.USB2_DN|B10| -|D||ALT5|PWM4_OUT
|-
|J1.204|DGND|DGND| -|<nowiki>-</nowiki>|G||ALT6|CCM_CLKO2
|-
|} ===Pinout Table J4 pins declaration ==={| classrowspan="wikitable3" |J1.62! latexfontsize| rowspan="scriptsize3" | Pin SAI5_RXFS! latexfontsize| rowspan="scriptsize3" | Pin NameCPU.SAI5_RXFS! latexfontsize| rowspan="scriptsize3" | Internal Connections N4! latexfontsize| rowspan="scriptsize3" | Ball/pin # NVCC_3V3! latexfontsize| rowspan="scriptsize3" |<nowiki>Voltage|domain<I/nowiki>O! latexfontsize| rowspan="scriptsize3" | Type ! latexfontsize="scriptsize" | NotesALT0! colspan="2" |Alternative FunctionsSAI5_RX_SYNC
|-
|J4.1ALT1|DGND|DGNDSAI1_TX_DATA0| -|<nowiki>-</nowiki>|G||ALT5|GPIO3_IO19
|-
| rowspan="73" |J4J1.264| rowspan="73" |SAI1_RXD7SAI5_RXC| rowspan="73" |CPU.SAI1_RXD7SAI5_RXC| rowspan="73" |G1L5| rowspan="73" |NVCC_3V3| rowspan="73" |I/O| rowspan="73" |internally used for BOOT config
|ALT0
|SAI1_RX_DATA7SAI5_RX_BCLK
|-
|ALT1
|SAI6_MCLKSAI1_TX_DATA1
|-
|ALT2ALT5|SAI1_TX_SYNCGPIO3_IO20
|-
|ALT3rowspan="3" |J1.66| rowspan="3" |SAI2_TXC| rowspan="3" |CPU.SAI2_TXC| rowspan="3" |J5| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|SAI1_TX_DATA4SAI2_TX_BCLK
|-
|ALT4ALT1|CORESIGHT_TRACE7SAI5_TX_DATA2
|-
|ALT5
|GPIO4_IO09GPIO4_IO25
|-
|ALT6|SRC_BOOT_CFG7|-| rowspan="63" |J4J1.368| rowspan="63" |SAI1_RXD6SAI2_TXD0| rowspan="63" |CPU.SAI1_RXD6SAI2_TXD0| rowspan="63" |G2G5| rowspan="63" |NVCC_3V3| rowspan="63" |I/O| rowspan="63" |internally used for BOOT config
|ALT0
|SAI1_RX_DATA6SAI2_TX_DATA0
|-
|ALT1
|SAI6_TX_SYNC|-|ALT2|SAI6_RX_SYNC|-|ALT4|CORESIGHT_TRACE6SAI5_TX_DATA3
|-
|ALT5
|GPIO4_IO08GPIO4_IO26
|-
|ALT6|SRC_BOOT_CFG6|-| rowspan="73" |J4J1.470| rowspan="73" |SAI1_RXD5SAI2_TXFS| rowspan="73" |CPU.SAI1_RXD5SAI2_TXFS| rowspan="73" |F1H4| rowspan="73" |NVCC_3V3| rowspan="73" |I/O| rowspan="73" |internally used for BOOT config
|ALT0
|SAI1_RX_DATA5SAI2_TX_SYNC
|-
|ALT1
|SAI6_TX_DATA0SAI5_TX_DATA1
|-
|ALT2ALT5|SAI6_RX_DATA0GPIO4_IO24
|-
|ALT3rowspan="3" |J1.72| rowspan="3" |SAI2_RXD0| rowspan="3" |CPU.SAI2_RXD0| rowspan="3" |H6| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|SAI1_RX_SYNCSAI2_RX_DATA0
|-
|ALT4ALT1|CORESIGHT_TRACE5SAI5_TX_DATA0
|-
|ALT5
|GPIO4_IO07GPIO4_IO23
|-
|ALT6|SRC_BOOT_CFG5|-| rowspan="63" |J4J1.574| rowspan="63" |SAI1_RXD4SAI5_RXD0| rowspan="63" |CPU.SAI1_RXD4SAI5_RXD0| rowspan="63" |J1M5| rowspan="63" |NVCC_3V3| rowspan="63" |I/O| rowspan="63" |internally used for BOOT config
|ALT0
|SAI1_RX_DATA4SAI5_RX_DATA0
|-
|ALT1
|SAI6_TX_BCLKSAI1_TX_DATA2
|-
|ALT2ALT5|SAI6_RX_BCLKGPIO3_IO21
|-
|ALT4|CORESIGHT_TRACE4|-|ALT5|GPIO4_IO06|-|ALT6|SRC_BOOT_CFG4|-| rowspan="5" |J4J1.676| rowspan="5" |SAI1_RXD3SAI5_RXD1| rowspan="5" |CPU.SAI1_RXD3SAI5_RXD1| rowspan="5" |J2L4
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |internally used for BOOT config
|ALT0
|SAI1_RX_DATA3SAI5_RX_DATA1
|-
|ALT1
|SAI5_RX_DATA3SAI1_TX_DATA3|-|ALT2|SAI1_TX_SYNC
|-
|ALT4ALT3|CORESIGHT_TRACE3SAI5_TX_SYNC
|-
|ALT5
|GPIO4_IO05GPIO3_IO212
|-
|ALT6|SRC_BOOT_CFG3|-| rowspan="5" |J4J1.778| rowspan="5" |SAI1_RXD2SAI5_RXD2| rowspan="5" |CPU.SAI1_RXD2SAI5_RXD2| rowspan="5" |H2M4
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |internally used for BOOT config
|ALT0
|SAI1_RX_DATA2SAI5_RX_DATA2
|-
|ALT1
|SAI5_RX_DATA2SAI1_TX_DATA4|-|ALT2|SAI1_TX_SYNC
|-
|ALT4ALT3|CORESIGHT_TRACE2SAI5_TX_BCLK
|-
|ALT5
|GPIO4_IO04GPIO3_IO23
|-
|ALT6|SRC_BOOT_CFG2|-| rowspan="5" |J4J1.880| rowspan="5" |SAI1_RXD1SAI5_RXD3| rowspan="5" |CPU.SAI1_RXD1SAI5_RXD3| rowspan="5" |L2K5
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |internally used for BOOT config
|ALT0
|SAI1_RX_DATA1SAI5_RX_DATA3
|-
|ALT1
|SAI5_RX_DATA1SAI1_TX_DATA5|-|ALT2|SAI1_TX_SYNC
|-
|ALT4ALT3|CORESIGHT_TRACE1SAI5_TX_DATA0
|-
|ALT5
|GPIO4_IO03GPIO3_IO24
|-
|ALT6J1.82|DGND|DGND| -|<nowiki>-</nowiki>|G|||SRC_BOOT_CFG1
|-
| rowspan="5" |J4J1.984| rowspan="5" |SAI1_RXD0CLK2_N| rowspan="5" |CPU.SAI1_RXD0CLK2_N| rowspan="5" |K2T22| rowspan="5" |NVCC_3V3VDDA_1V8| rowspan="5" |I/OD| rowspan="5" |internally Internally used for BOOT config|ALT0|SAI1_RX_DATA0|-PCIe CLK, do not connect|ALT1|SAI5_RX_DATA0
|-
|ALT4J1.86|CLK2_P|CPU.CLK2_P|U22|VDDA_1V8|D|Internally used for PCIe CLK, do not connect||CORESIGHT_TRACE0
|-
|ALT5J1.88|PCIE1_REF_CLKN|CPU.PCIE1_REF_PAD_CLK_N|K24|VDD_PHY_3V3|D|||GPIO4_IO02
|-
|ALT6J1.90|PCIE1_REF_CLKP|CPU.PCIE1_REF_PAD_CLK_P|K25|VDD_PHY_3V3|D|||SRC_BOOT_CFG0
|-
| rowspan="4" |J4J1.1092| rowspan="4" |SAI1_RXCPCIE1_RXN| rowspan="4" |CPU.SAI1_RXCPCIE1_RXN_N| rowspan="4" |K1H24| rowspan="4" |NVCC_3V3VDD_PHY_3V3| rowspan="4" |I/OD| rowspan="4" ||ALT0|SAI1_RX_BCLK
|-
|ALT1J1.94|PCIE1_RXP|CPU.PCIE1_RXN_P|H25|VDD_PHY_3V3|D|||SAI5_RX_BCLK
|-
|ALT4J1.96|CORESIGHT_TRACE_CTLPCIE1_TXN|CPU.PCIE1_TXN_N|J24|VDD_PHY_3V3|D|-|ALT5|GPIO4_IO01
|-
| rowspan="4" |J4J1.1198| rowspan="4" |SAI1_RXFSPCIE1_TXP| rowspan="4" |CPU.SAI1_RXFSPCIE1_TXN_P| rowspan="4" |L1J25| rowspan="4" |NVCC_3V3VDD_PHY_3V3| rowspan="4" |I/OD| rowspan="4" ||ALT0|SAI1_RX_SYNC
|-
|ALT1|SAI5_RX_SYNC|-|ALT4|CORESIGHT_TRACE_CLK|-|ALT5|GPIO4_IO00|-|J4J1.12100
|DGND
|DGND
|
|-
| rowspan="4" |J4J1.13102| rowspan="4" |SAI1_MCLKCSI1_CLK_N| rowspan="4" |CPU.SAI1_MCLK| rowspan="4" || rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|SAI1_MCLK|-|ALT1|SAI5_MCLK |-|ALT2|SAI1_TX_BCLK|-|ALT5|GPIO4_IO20|-|J4.14|DGNDMIPI_CSI1_CLK_N|DGNDA22
| -
|<nowiki>-</nowiki>|GD
|
|
|
|-
| rowspan="4" |J4J1.15104| rowspan="4" |SAI1_TXFSCSI1_CLK_P| rowspan="4" |CPU.SAI1_TXFSMIPI_CSI1_CLK_P| rowspan="4" |H4B22| rowspan="4" |NVCC_3V3-| rowspan="4" |I/OD| rowspan="4" ||ALT0|SAI1_TX_SYNC
|-
|ALT1J1.106|CSI1_D0_N|CPU.MIPI_CSI1_D0_N|A23| -|D|||SAI5_TX_SYNC
|-
|ALT4J1.108|CSI1_D0_P|CPU.MIPI_CSI1_D0_P|B23| -|D|||CORESIGHT_EVENTO
|-
|ALT5J1.110|CSI1_D1_N|CPU.MIPI_CSI1_D1_N|C22| -|D|||GPIO4_IO10
|-
| rowspan="4" |J4J1.16112| rowspan="4" |SAI1_TXCCSI1_D1_P| rowspan="4" |CPU.SAI1_TXCMIPI_CSI1_D1_P| rowspan="4" |J5D22| rowspan="4" |NVCC_3V3-| rowspan="4" |I/OD| rowspan="4" ||ALT0|SAI1_TX_BCLK
|-
|ALT1J1.114|SAI5_TX_BCLKCSI1_D2_N|CPU.MIPI_CSI1_D2_N|B24|-|ALT4D|||CORESIGHT_EVENTI
|-
|ALT5J1.116|CSI1_D2_P|CPU.MIPI_CSI1_D2_P|C23| -|D|||GPIO4_IO11
|-
| rowspan="5" |J4J1.17118| rowspan="5" |SAI1_TXD0CSI1_D3_N| rowspan="5" |CPU.SAI1_TXD0MIPI_CSI1_D3_N| rowspan="5" |F2C21| rowspan="5" |NVCC_3V3-| rowspan="5" |I/OD| rowspan="5" |internally used for BOOT config|ALT0|SAI1_TX_DATA0
|-
|ALT1J1.120|CSI1_D3_P|CPU.MIPI_CSI1_D3_P|D21| -|D|||SAI5_TX_DATA0
|-
|ALT4J1.122|DGND|DGND| -|<nowiki>-</nowiki>|G|||CORESIGHT_TRACE8
|-
|ALT5J1.124(NAND on board)|NAND_DQS|CPU.NAND_DQS|M20|NVCC_3V3|I/O|Internally used for NAND, do not connect||GPIO4_IO12
|-
|ALT6|SRC_BOOT_CFG8|-| rowspan="53" |J4J1.18124(eMMC on board)| rowspan="53" |SAI1_TXD1NAND_DQS| rowspan="53" |CPU.SAI1_TXD1NAND_DQS| rowspan="53" |E2M20| rowspan="53" |NVCC_3V3| rowspan="53" |I/O| rowspan="53" |internally used for BOOT config
|ALT0
|SAI1_TX_DATA1RAWNAND_DQS
|-
|ALT1
|SAI5_TX_DATA1|-|ALT4|CORESIGHT_TRACE9QSPI_A_DQS
|-
|ALT5
|GPIO4_IO13GPIO3_IO14
|-
|ALT6J1.126(NAND on board)|NAND_ALE|CPU.NAND_ALE|G19|NVCC_3V3|I/O|Internally used for NAND, do not connect||SRC_BOOT_CFG9
|-
| rowspan="53" |J4J1.19126(eMMC on board)| rowspan="53" |SAI1_TXD2NAND_ALE| rowspan="53" |CPU.SAI1_TXD2NAND_ALE| rowspan="53" |B2G19| rowspan="53" |NVCC_3V3| rowspan="53" |I/O| rowspan="53" |internally used for BOOT config
|ALT0
|SAI1_TX_DATA2RAWNAND_ALE
|-
|ALT1
|SAI5_TX_DATA2QSPI_A_SCLK|-|ALT5|GPIO3_IO00
|-
|ALT4rowspan="2" |J1.128(NAND on board)| rowspan="2" |SD1_CLK| rowspan="2" |CPU.SD1_CLK| rowspan="2" |L25| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" ||ALT0|CORESIGHT_TRACE10USDHC1_CLK
|-
|ALT5
|GPIO4_IO14GPIO2_IO00
|-
|ALT6|SRC_BOOT_CFG10|-| rowspan="53" |J4J1.20128(eMMC on board)| rowspan="53" |SAI1_TXD3NAND_CE0_B| rowspan="53" |CPU.SAI1_TXD3NAND_CE0_B| rowspan="53" |D1H19| rowspan="53" |NVCC_3V3| rowspan="53" |I/O| rowspan="53" |internally used for BOOT config
|ALT0
|SAI1_TX_DATA3RAWNAND_CE0_B
|-
|ALT1
|SAI5_TX_DATA3QSPI_A_SS0_B|-|ALT5|GPIO3_IO01
|-
|ALT4rowspan="2" |J1.130(NAND on board)| rowspan="2" |SD1_CMD| rowspan="2" |CPU.SD1_CMD| rowspan="2" |L24| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" ||ALT0|CORESIGHT_TRACE11USDHC1_CMD
|-
|ALT5
|GPIO4_IO15GPIO2_IO01
|-
|ALT6|SRC_BOOT_CFG11|-| rowspan="63" |J4J1.21130(eMMC on board)| rowspan="63" |SAI1_TXD4NAND_CE1_B| rowspan="63" |CPU.SAI1_TXD4NAND_CE1_B| rowspan="63" |D2G21| rowspan="63" |NVCC_3V3| rowspan="63" |I/O| rowspan="63" |internally used for BOOT config
|ALT0
|SAI1_TX_DATA4RAWNAND_CE1_B
|-
|ALT1
|SAI6_RX_BCLK|-|ALT2|SAI6_TX_BCLK|-|ALT4|CORESIGHT_TRACE12QSPI_A_SS1_B
|-
|ALT5
|GPIO4_IO16GPIO3_IO02
|-
|ALT6|SRC_BOOT_CFG12|-| rowspan="62" |J4J1.22132(NAND on board)| rowspan="62" |SAI1_TXD5SD1_RST_B| rowspan="62" |CPU.SAI1_TXD5SD1_RST_B| rowspan="62" |C2R24| rowspan="62" |NVCC_3V3(NVCC_1V8 on request)| rowspan="62" |I/O| rowspan="62" |internally used for BOOT config
|ALT0
|SAI1_TX_DATA5USDHC1_RESET_B
|-
|ALT1ALT5|SAI6_RX_DATA0GPIO2_IO10
|-
|ALT2rowspan="3" |J1.132(eMMC on board)| rowspan="3" |NAND_CE2_B| rowspan="3" |CPU.NAND_CE2_B| rowspan="3" |F21| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|SAI6_TX_DATA0RAWNAND_CE2_B
|-
|ALT4ALT1|CORESIGHT_TRACE13QSPI_B_SS0_B
|-
|ALT5
|GPIO4_IO17GPIO3_IO03
|-
|ALT6rowspan="2" |J1.134(NAND on board)| rowspan="2" |SD1_STROBE| rowspan="2" |CPU.SD1_STROBE| rowspan="2" |T24| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_STROBE|-|ALT5|SRC_BOOT_CFG13GPIO2_IO11
|-
| rowspan="63" |J4J1.23134(eMMC on board)| rowspan="63" |SAI1_TXD6NAND_CE3_B| rowspan="63" |CPU.SAI1_TXD6NAND_CE3_B| rowspan="63" |B3H20| rowspan="63" |NVCC_3V3| rowspan="63" |I/O| rowspan="63" |internally used for BOOT config
|ALT0
|SAI1_TX_DATA6RAWNAND_CE3_B
|-
|ALT1
|SAI6_RX_SYNCQSPI_B_SS1_B
|-
|ALT2ALT5|SAI6_TX_SYNCGPIO3_IO034
|-
|ALT4J1.136(NAND on board)|NAND_CLE|CPU.NAND_CLE|H21|NVCC_3V3|I/O|Internally used for NAND, do not connect||CORESIGHT_TRACE14
|-
|ALT5|GPIO4_IO18|-|ALT6|SRC_BOOT_CFG14|-| rowspan="53" |J4J1.24136(eMMC on board)| rowspan="53" |SAI1_TXD7NAND_CLE| rowspan="53" |CPU.SAI1_TXD7NAND_CLE| rowspan="53" |C1H21| rowspan="53" |NVCC_3V3| rowspan="53" |I/O| rowspan="53" |internally used for BOOT config
|ALT0
|SAI1_TX_DATA7RAWNAND_CLE
|-
|ALT1
|SAI6_MCLKQSPI_B_SCLK
|-
|ALT4ALT5|CORESIGHT_TRACE15GPIO3_IO05|-| rowspan="2" |J1.138(NAND on board)| rowspan="2" |SD1_DATA0| rowspan="2" |CPU.SD1_DATA0| rowspan="2" |M25| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_DATA0
|-
|ALT5
|GPIO4_IO19GPIO2_IO02|-| rowspan="3" |J1.138(eMMC on board)| rowspan="3" |NAND_DATA00| rowspan="3" |CPU.NAND_DATA00| rowspan="3" |G20| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_DATA00
|-
|ALT6ALT1|SRC_BOOT_CFG15QSPI_A_DATA0
|-
|J4.25ALT5|DGND|DGND| -|<nowiki>-</nowiki>|G||||}===Pinout Table J5 pins declaration ==={| class="wikitable" ! latexfontsize="scriptsize" | Pin ! latexfontsize="scriptsize" | Pin Name! latexfontsize="scriptsize" | Internal Connections ! latexfontsize="scriptsize" | Ball/pin # ! latexfontsize="scriptsize" |<nowiki>Voltage|domain</nowiki>! latexfontsize="scriptsize" | Type ! latexfontsize="scriptsize" | Notes! colspan="2" |Alternative FunctionsGPIO3_IO06
|-
|J5rowspan="2" |J1.1140(NAND on board)| rowspan="2" |SD1_DATA1|DGNDrowspan="2" |CPU.SD1_DATA1|DGNDrowspan="2" |M24| -rowspan="2" |NVCC_3V3(NVCC_1V8 on request)|<nowiki>-<rowspan="2" |I/nowiki>O|Growspan="2" ||ALT0|USDHC1_DATA1
|-
|J5ALT5|GPIO2_IO0|-| rowspan="3" |J1.2140(eMMC on board)|PCIE2_RXNrowspan="3" |NAND_DATA01| rowspan="3" |CPU.PCIE2_RXN_NNAND_DATA01|D24rowspan="3" |J20| -rowspan="3" |NVCC_3V3|Drowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_DATA01
|-
|J5.3|PCIE2_RXP|CPU.PCIE2_RXN_P|D25| -|D||ALT1|QSPI_A_DATA1
|-
|J5ALT5|GPIO3_IO07|-| rowspan="2" |J1.4142(NAND on board)|DGNDrowspan="2" |SD1_DATA2|DGNDrowspan="2" |CPU.SD1_DATA2| -rowspan="2" |N25| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)|<nowiki>-<rowspan="2" |I/nowiki>O|Growspan="2" ||ALT0|USDHC1_DATA2
|-
|J5.5|PCIE2_TXN|CPU.PCIE2_TXN_N|E24| -|D||ALT5|GPIO2_IO04
|-
|J5rowspan="3" |J1.6142(eMMC on board)|PCIE2_TXProwspan="3" |NAND_DATA02| rowspan="3" |CPU.PCIE2_TXN_PNAND_DATA02| rowspan="3" |H22| rowspan="3" |NVCC_3V3| rowspan="3" |I/O|E25rowspan="3" || -ALT0|DRAWNAND_DATA02|-|ALT1|QSPI_A_DATA2
|-
|J5.7|DGND|DGND| -|<nowiki>-</nowiki>|G||ALT5|GPIO3_IO08
|-
|J5rowspan="2" |J1.8144(NAND on board)|PCIE2_REF_CLKNrowspan="2" |SD1_DATA3| rowspan="2" |CPU.PCIE2_REF_PAD_CLK_NSD1_DATA3|F24rowspan="2" |P25| -rowspan="2" |NVCC_3V3(NVCC_1V8 on request)|Drowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_DATA3
|-
|J5.9|PCIE2_REF_CLKP|CPU.PCIE2_REF_PAD_CLK_P|F25| -|D||ALT5|GPIO2_IO05
|-
|J5rowspan="3" |J1.10144(eMMC on board)| rowspan="3" |DGNDNAND_DATA03|DGNDrowspan="3" |CPU.NAND_DATA03| -rowspan="3" |J21|<nowiki>-<rowspan="3" |NVCC_3V3| rowspan="3" |I/nowiki>O|Growspan="3" ||ALT0|RAWNAND_DATA03
|-
|J5.11|CSI_P2_CKN|CPU.MIPI_CSI2_CLK_N|A19| -|D||ALT1|QSPI_A_DATA3
|-
|J5.12|CSI_P2_CKP|CPU.MIPI_CSI2_CLK_P|B19| -|D||ALT5|GPIO3_IO09
|-
|J5J1.13146
|DGND
|DGND
|
|-
|J5rowspan="2" |J1.14148(NAND on board)|CSI_P2_DN0rowspan="2" |SD1_DATA4| rowspan="2" |CPU.MIPI_CSI2_D0_NSD1_DATA4|C20rowspan="2" |N24| -rowspan="2" |NVCC_3V3(NVCC_1V8 on request)|Drowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_DATA4
|-
|J5.15|CSI_P2_DP0|CPU.MIPI_CSI2_D0_P|D10| -|D||ALT5|GPIO2_IO06
|-
|J5rowspan="3" |J1.16148(eMMC on board)|CSI_P2_DN1rowspan="3" |NAND_DATA04| rowspan="3" |CPU.MIPI_CSI2_D1_NNAND_DATA04|A20rowspan="3" |L20| -rowspan="3" |NVCC_3V3|Drowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_DATA04
|-
|J5.17|CSI_P2_DP1|CPU.MIPI_CSI2_D1_P|B20| -|D||ALT1|QSPI_B_DATA0
|-
|J5.18|DGND|DGND| -|<nowiki>-</nowiki>|G||ALT5|GPIO3_IO10
|-
|J5rowspan="2" |J1.19150(NAND on board)|CSI_P2_DN2rowspan="2" |SD1_DATA5| rowspan="2" |CPU.MIPI_CSI2_D2_NSD1_DATA5|A21rowspan="2" |P24| -rowspan="2" |NVCC_3V3(NVCC_1V8 on request)|Drowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_DATA5
|-
|J5.20|CSI_P2_DP2|CPU.MIPI_CSI2_D2_P|B21| -|D||ALT5|GPIO2_IO07
|-
|J5rowspan="3" |J1.21150(eMMC on board)|CSI_P2_DN3rowspan="3" |NAND_DATA05| rowspan="3" |CPU.MIPI_CSI2_D3_NNAND_DATA05|C19rowspan="3" |J22| -rowspan="3" |NVCC_3V3|Drowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_DATA05
|-
|J5.22|CSI_P2_DP3|CPU.MIPI_CSI2_D3_P|D19| -|D||ALT1|QSPI_B_DATA1
|-
|J5.23|DGND|DGND| -|<nowiki>-</nowiki>|G||ALT5|GPIO3_IO11
|-
| rowspan="42" |J5J1.24152(NAND on board)| rowspan="2" |SD1_DATA6| rowspan="2" |CPU.SD1_DATA6| rowspan="2" |R25| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_DATA6|-|ALT5|GPIO2_IO08|-| rowspan="3" |J1.152(eMMC on board)| rowspan="43" |I2C4_SCLNAND_DATA06| rowspan="43" |CPU.I2C4_SCLNAND_DATA06| rowspan="43" |F8L19| rowspan="43" |NVCC_3V3| rowspan="43" |I/O| rowspan="43" |
|ALT0
|I2C4_SCLRAWNAND_DATA06
|-
|ALT1
|PWM2_OUT|-|ALT2|PCIE1_CLKREQ_BQSPI_B_DATA2
|-
|ALT5
|GPIO5_IO20GPIO3_IO12
|-
| rowspan="42" |J5J1.25154(NAND on board)| rowspan="2" |SD1_DATA7| rowspan="2" |CPU.SD1_DATA7| rowspan="2" |T25| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_DATA7|-|ALT5|GPIO2_IO09|-| rowspan="3" |J1.154(eMMC on board)| rowspan="43" |I2C4_SDANAND_DATA07| rowspan="43" |CPU.I2C4_SDANAND_DATA07| rowspan="43" |F9M19| rowspan="43" |NVCC_3V3| rowspan="43" |I/O| rowspan="43" |
|ALT0
|I2C4_SDARAWNAND_DATA07
|-
|ALT1
|PWM1_OUT|-|ALT2|PCIE2_CLKREQ_BQSPI_B_DATA3
|-
|ALT5
|GPIO5_IO21|} ===Pinout Table JD5 pins declaration ==={| class="wikitable" ! latexfontsize="scriptsize" | Pin ! latexfontsize="scriptsize" | Pin Name! latexfontsize="scriptsize" | Internal Connections ! latexfontsize="scriptsize" | Ball/pin # ! latexfontsize="scriptsize" |<nowiki> Voltage|domain</nowiki>! latexfontsize="scriptsize" | Type ! latexfontsize="scriptsize" | Notes! colspan="2" latexfontsize="scriptsize" | Alternative FunctionsGPIO3_IO13
|-
|JD5J1.1156|DGND|DGND| -|<nowiki>-</nowiki>(NAND on board)|GNAND_RE_B||||-|JD5CPU.2|EEPROM_WP|Internal EEPROM Write ProtectNAND_RE_B| -K19
|NVCC_3V3
|I/O|Internally used for NAND, do not connect
|
|
|-
|JD5rowspan="3" |J1.156(eMMC on board)| rowspan="3" |NAND_RE_B|NCrowspan="3" |CPU.NAND_RE_B|Not Connectedrowspan="3" |K19| -rowspan="3" |NVCC_3V3| -rowspan="3" |I/O|Zrowspan="3" ||ALT0|RAWNAND_RE_B
|-
|JD5.4|JTAG_TCK|CPU.JTAG_TCK|T5|NVCC_3V3|I|internal pull-up 10k to NVCC_3V3|ALT1|QSPI_B_DQS
|-
|JD5.5|JTAG_TMS|CPU.JTAG_TMS|V5|NVCC_3V3|I||ALT5|GPIO3_IO15
|-
|JD5J1.6158(NAND on board)|JTAG_TDONAND_READY_B|CPU.JTAG_TDONAND_READY_B|U5K20
|NVCC_3V3
|I/O|Internally used for NAND, do not connect
|
|
|-
|JD5rowspan="2" |J1.7158(eMMC on board)|JTAG_TDIrowspan="2" |NAND_READY_B| rowspan="2" |CPU.JTAG_TDINAND_READY_B|W5rowspan="2" |K20| rowspan="2" |NVCC_3V3| rowspan="2" |I/O| rowspan="2" ||ALT0|RAWNAND_READY_B|-|ALT5|GPIO3_IO16
|-
|JD5J1.8160(NAND on board)|JTAG_nTRSTNAND_WE_B|CPU.JTAG_TRST_BNAND_WE_B|U6K22
|NVCC_3V3
|I
|
|
|
|-
|JD5.9
|CPU_PORn
|CPU.POR_B
PMIC.RESETMCU
|W20
3
|NVCC_SNVS
|I/O
|internal pull-up 100k to NVCC_SNVSInternally used for NAND, do not connect
|
|
|-
|JD5rowspan="2" |J1.10160(eMMC on board)| rowspan="2" |NAND_WE_B| rowspan="2" |CPU.NAND_WE_B| rowspan="2" |K22| rowspan="2" |NVCC_3V3|NVCC_3V3rowspan="2" |I/O| rowspan="2" ||ALT0|RAWNAND_WE_B| -|<nowiki>ALT5|GPIO3_IO17|-<|J1.162(NAND on board)|NAND_WP_B|CPU.NAND_WP_B|K21|NVCC_3V3|I/nowiki>O|SInternally used for NAND, do not connect
|
|
|-
| rowspan="2" |J1.162
(eMMC on board)
| rowspan="2" |NAND_WP_B
| rowspan="2" |CPU.NAND_WP_B
| rowspan="2" |K21
| rowspan="2" |NVCC_3V3
| rowspan="2" |I/O
| rowspan="2" |
|ALT0
|RAWNAND_WP_B
|-
|ALT5
|GPIO3_IO18
|-
|J1.164
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
|J1.166
|CLK1_N
|CPU.CLK1_N
|T23
|
|D
|
|
|
|-
|J1.168
|CLK1_P
|CPU.CLK1_P
|R23
|
|D
|
|
|
|-
|J1.170
|USB2_RXN
|CPU.USB2_RX_N
|B8
|
|D
|
|
|
|-
|J1.172
|USB2_RXP
|CPU.USB2_RX_P
|A8
|
|D
|
|
|
|-
|J1.174
|USB2_TXN
|CPU.USB2_TX_N
|B9
|
|D
|
|
|
|-
|J1.176
|USB2_TXP
|CPU.USB2_TX_P
|A9
|
|D
|
|
|
|-
|J1.178
|USB1_RXN
|CPU.USB1_RX_N
|B12
|
|D
|
|
|
|-
|J1.180
|USB1_RXP
|CPU.USB1_RX_P
|A12
|
|D
|
|
|
|-
|J1.182
|USB1_TXN
|CPU.USB1_TX_N
|B13
|
|D
|
|
|
|-
|J1.184
|USB1_TXP
|CPU.USB1_TX_P
|A13
|
|D
|
|
|
|-
|J1.186
|USB1_VBUS
|CPU.USB1_VBUS
|D14
| -
|S
|Absolute maximum ratings 5.25V
|
|
|-
|J1.188
|USB2_VBUS
|CPU.USB2_VBUS
|D9
| -
|S
|Absolute maximum ratings 5.25V
|
|
|-
|J1.190
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
|J1.192
|USB1_ID
|CPU.USB1_ID
|C14
|VDD_PHY_3V3
|I
|
|
|
|-
|J1.194
|USB2_ID
|CPU.USB2_ID
|C9
|VDD_PHY_3V3
|I
|
|
|
|-
|J1.196
|USB1_DN
|CPU.USB1_DN
|B14
| -
|D
|
|
|
|-
|J1.198
|USB1_DP
|CPU.USB1_DP
|A14
| -
|D
|
|
|
|-
|J1.200
|USB2_DP
|CPU.USB2_DP
|A10
| -
|D
|
|
|
|-
|J1.202
|USB2_DN
|CPU.USB2_DN
|B10
| -
|D
|
|
|
|-
|J1.204
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
|}
 
==ONE PIECE J4 pins declaration ==
{| class="wikitable"
! latexfontsize="scriptsize" | Pin
! latexfontsize="scriptsize" | Pin Name
! latexfontsize="scriptsize" | Internal Connections
! latexfontsize="scriptsize" | Ball/pin #
! latexfontsize="scriptsize" | Voltage domain
! latexfontsize="scriptsize" | Type
! latexfontsize="scriptsize" | Notes
! colspan="2" |Alternative Functions
|-
|J4.1
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
| rowspan="7" |J4.2
| rowspan="7" |SAI1_RXD7
| rowspan="7" |CPU.SAI1_RXD7
| rowspan="7" |G1
| rowspan="7" |NVCC_3V3
| rowspan="7" |I/O
| rowspan="7" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_RX_DATA7
|-
|ALT1
|SAI6_MCLK
|-
|ALT2
|SAI1_TX_SYNC
|-
|ALT3
|SAI1_TX_DATA4
|-
|ALT4
|CORESIGHT_TRACE7
|-
|ALT5
|GPIO4_IO09
|-
|ALT6
|SRC_BOOT_CFG7
|-
| rowspan="6" |J4.3
| rowspan="6" |SAI1_RXD6
| rowspan="6" |CPU.SAI1_RXD6
| rowspan="6" |G2
| rowspan="6" |NVCC_3V3
| rowspan="6" |I/O
| rowspan="6" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_RX_DATA6
|-
|ALT1
|SAI6_TX_SYNC
|-
|ALT2
|SAI6_RX_SYNC
|-
|ALT4
|CORESIGHT_TRACE6
|-
|ALT5
|GPIO4_IO08
|-
|ALT6
|SRC_BOOT_CFG6
|-
| rowspan="7" |J4.4
| rowspan="7" |SAI1_RXD5
| rowspan="7" |CPU.SAI1_RXD5
| rowspan="7" |F1
| rowspan="7" |NVCC_3V3
| rowspan="7" |I/O
| rowspan="7" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_RX_DATA5
|-
|ALT1
|SAI6_TX_DATA0
|-
|ALT2
|SAI6_RX_DATA0
|-
|ALT3
|SAI1_RX_SYNC
|-
|ALT4
|CORESIGHT_TRACE5
|-
|ALT5
|GPIO4_IO07
|-
|ALT6
|SRC_BOOT_CFG5
|-
| rowspan="6" |J4.5
| rowspan="6" |SAI1_RXD4
| rowspan="6" |CPU.SAI1_RXD4
| rowspan="6" |J1
| rowspan="6" |NVCC_3V3
| rowspan="6" |I/O
| rowspan="6" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_RX_DATA4
|-
|ALT1
|SAI6_TX_BCLK
|-
|ALT2
|SAI6_RX_BCLK
|-
|ALT4
|CORESIGHT_TRACE4
|-
|ALT5
|GPIO4_IO06
|-
|ALT6
|SRC_BOOT_CFG4
|-
| rowspan="5" |J4.6
| rowspan="5" |SAI1_RXD3
| rowspan="5" |CPU.SAI1_RXD3
| rowspan="5" |J2
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_RX_DATA3
|-
|ALT1
|SAI5_RX_DATA3
|-
|ALT4
|CORESIGHT_TRACE3
|-
|ALT5
|GPIO4_IO05
|-
|ALT6
|SRC_BOOT_CFG3
|-
| rowspan="5" |J4.7
| rowspan="5" |SAI1_RXD2
| rowspan="5" |CPU.SAI1_RXD2
| rowspan="5" |H2
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_RX_DATA2
|-
|ALT1
|SAI5_RX_DATA2
|-
|ALT4
|CORESIGHT_TRACE2
|-
|ALT5
|GPIO4_IO04
|-
|ALT6
|SRC_BOOT_CFG2
|-
| rowspan="5" |J4.8
| rowspan="5" |SAI1_RXD1
| rowspan="5" |CPU.SAI1_RXD1
| rowspan="5" |L2
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_RX_DATA1
|-
|ALT1
|SAI5_RX_DATA1
|-
|ALT4
|CORESIGHT_TRACE1
|-
|ALT5
|GPIO4_IO03
|-
|ALT6
|SRC_BOOT_CFG1
|-
| rowspan="5" |J4.9
| rowspan="5" |SAI1_RXD0
| rowspan="5" |CPU.SAI1_RXD0
| rowspan="5" |K2
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_RX_DATA0
|-
|ALT1
|SAI5_RX_DATA0
|-
|ALT4
|CORESIGHT_TRACE0
|-
|ALT5
|GPIO4_IO02
|-
|ALT6
|SRC_BOOT_CFG0
|-
| rowspan="4" |J4.10
| rowspan="4" |SAI1_RXC
| rowspan="4" |CPU.SAI1_RXC
| rowspan="4" |K1
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |
|ALT0
|SAI1_RX_BCLK
|-
|ALT1
|SAI5_RX_BCLK
|-
|ALT4
|CORESIGHT_TRACE_CTL
|-
|ALT5
|GPIO4_IO01
|-
| rowspan="4" |J4.11
| rowspan="4" |SAI1_RXFS
| rowspan="4" |CPU.SAI1_RXFS
| rowspan="4" |L1
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |
|ALT0
|SAI1_RX_SYNC
|-
|ALT1
|SAI5_RX_SYNC
|-
|ALT4
|CORESIGHT_TRACE_CLK
|-
|ALT5
|GPIO4_IO00
|-
|J4.12
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
| rowspan="4" |J4.13
| rowspan="4" |SAI1_MCLK
| rowspan="4" |CPU.SAI1_MCLK
| rowspan="4" |
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |
|ALT0
|SAI1_MCLK
|-
|ALT1
|SAI5_MCLK
|-
|ALT2
|SAI1_TX_BCLK
|-
|ALT5
|GPIO4_IO20
|-
|J4.14
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
| rowspan="4" |J4.15
| rowspan="4" |SAI1_TXFS
| rowspan="4" |CPU.SAI1_TXFS
| rowspan="4" |H4
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |
|ALT0
|SAI1_TX_SYNC
|-
|ALT1
|SAI5_TX_SYNC
|-
|ALT4
|CORESIGHT_EVENTO
|-
|ALT5
|GPIO4_IO10
|-
| rowspan="4" |J4.16
| rowspan="4" |SAI1_TXC
| rowspan="4" |CPU.SAI1_TXC
| rowspan="4" |J5
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |
|ALT0
|SAI1_TX_BCLK
|-
|ALT1
|SAI5_TX_BCLK
|-
|ALT4
|CORESIGHT_EVENTI
|-
|ALT5
|GPIO4_IO11
|-
| rowspan="5" |J4.17
| rowspan="5" |SAI1_TXD0
| rowspan="5" |CPU.SAI1_TXD0
| rowspan="5" |F2
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_TX_DATA0
|-
|ALT1
|SAI5_TX_DATA0
|-
|ALT4
|CORESIGHT_TRACE8
|-
|ALT5
|GPIO4_IO12
|-
|ALT6
|SRC_BOOT_CFG8
|-
| rowspan="5" |J4.18
| rowspan="5" |SAI1_TXD1
| rowspan="5" |CPU.SAI1_TXD1
| rowspan="5" |E2
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_TX_DATA1
|-
|ALT1
|SAI5_TX_DATA1
|-
|ALT4
|CORESIGHT_TRACE9
|-
|ALT5
|GPIO4_IO13
|-
|ALT6
|SRC_BOOT_CFG9
|-
| rowspan="5" |J4.19
| rowspan="5" |SAI1_TXD2
| rowspan="5" |CPU.SAI1_TXD2
| rowspan="5" |B2
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_TX_DATA2
|-
|ALT1
|SAI5_TX_DATA2
|-
|ALT4
|CORESIGHT_TRACE10
|-
|ALT5
|GPIO4_IO14
|-
|ALT6
|SRC_BOOT_CFG10
|-
| rowspan="5" |J4.20
| rowspan="5" |SAI1_TXD3
| rowspan="5" |CPU.SAI1_TXD3
| rowspan="5" |D1
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_TX_DATA3
|-
|ALT1
|SAI5_TX_DATA3
|-
|ALT4
|CORESIGHT_TRACE11
|-
|ALT5
|GPIO4_IO15
|-
|ALT6
|SRC_BOOT_CFG11
|-
| rowspan="6" |J4.21
| rowspan="6" |SAI1_TXD4
| rowspan="6" |CPU.SAI1_TXD4
| rowspan="6" |D2
| rowspan="6" |NVCC_3V3
| rowspan="6" |I/O
| rowspan="6" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_TX_DATA4
|-
|ALT1
|SAI6_RX_BCLK
|-
|ALT2
|SAI6_TX_BCLK
|-
|ALT4
|CORESIGHT_TRACE12
|-
|ALT5
|GPIO4_IO16
|-
|ALT6
|SRC_BOOT_CFG12
|-
| rowspan="6" |J4.22
| rowspan="6" |SAI1_TXD5
| rowspan="6" |CPU.SAI1_TXD5
| rowspan="6" |C2
| rowspan="6" |NVCC_3V3
| rowspan="6" |I/O
| rowspan="6" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_TX_DATA5
|-
|ALT1
|SAI6_RX_DATA0
|-
|ALT2
|SAI6_TX_DATA0
|-
|ALT4
|CORESIGHT_TRACE13
|-
|ALT5
|GPIO4_IO17
|-
|ALT6
|SRC_BOOT_CFG13
|-
| rowspan="6" |J4.23
| rowspan="6" |SAI1_TXD6
| rowspan="6" |CPU.SAI1_TXD6
| rowspan="6" |B3
| rowspan="6" |NVCC_3V3
| rowspan="6" |I/O
| rowspan="6" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_TX_DATA6
|-
|ALT1
|SAI6_RX_SYNC
|-
|ALT2
|SAI6_TX_SYNC
|-
|ALT4
|CORESIGHT_TRACE14
|-
|ALT5
|GPIO4_IO18
|-
|ALT6
|SRC_BOOT_CFG14
|-
| rowspan="5" |J4.24
| rowspan="5" |SAI1_TXD7
| rowspan="5" |CPU.SAI1_TXD7
| rowspan="5" |C1
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_TX_DATA7
|-
|ALT1
|SAI6_MCLK
|-
|ALT4
|CORESIGHT_TRACE15
|-
|ALT5
|GPIO4_IO19
|-
|ALT6
|SRC_BOOT_CFG15
|-
|J4.25
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|}
 
==ONE PIECE J5 pins declaration ==
{| class="wikitable"
! latexfontsize="scriptsize" | Pin
! latexfontsize="scriptsize" | Pin Name
! latexfontsize="scriptsize" | Internal Connections
! latexfontsize="scriptsize" | Ball/pin #
! latexfontsize="scriptsize" | Voltage domain
! latexfontsize="scriptsize" | Type
! latexfontsize="scriptsize" | Notes
! colspan="2" |Alternative Functions
|-
|J5.1
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
|J5.2
|PCIE2_RXN
|CPU.PCIE2_RXN_N
|D24
| -
|D
|
|
|
|-
|J5.3
|PCIE2_RXP
|CPU.PCIE2_RXN_P
|D25
| -
|D
|
|
|
|-
|J5.4
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
|J5.5
|PCIE2_TXN
|CPU.PCIE2_TXN_N
|E24
| -
|D
|
|
|
|-
|J5.6
|PCIE2_TXP
|CPU.PCIE2_TXN_P
|E25
| -
|D
|
|
|
|-
|J5.7
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
|J5.8
|PCIE2_REF_CLKN
|CPU.PCIE2_REF_PAD_CLK_N
|F24
| -
|D
|
|
|
|-
|J5.9
|PCIE2_REF_CLKP
|CPU.PCIE2_REF_PAD_CLK_P
|F25
| -
|D
|
|
|
|-
|J5.10
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
|J5.11
|CSI_P2_CKN
|CPU.MIPI_CSI2_CLK_N
|A19
| -
|D
|
|
|
|-
|J5.12
|CSI_P2_CKP
|CPU.MIPI_CSI2_CLK_P
|B19
| -
|D
|
|
|
|-
|J5.13
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
|J5.14
|CSI_P2_DN0
|CPU.MIPI_CSI2_D0_N
|C20
| -
|D
|
|
|
|-
|J5.15
|CSI_P2_DP0
|CPU.MIPI_CSI2_D0_P
|D10
| -
|D
|
|
|
|-
|J5.16
|CSI_P2_DN1
|CPU.MIPI_CSI2_D1_N
|A20
| -
|D
|
|
|
|-
|J5.17
|CSI_P2_DP1
|CPU.MIPI_CSI2_D1_P
|B20
| -
|D
|
|
|
|-
|J5.18
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
|J5.19
|CSI_P2_DN2
|CPU.MIPI_CSI2_D2_N
|A21
| -
|D
|
|
|
|-
|J5.20
|CSI_P2_DP2
|CPU.MIPI_CSI2_D2_P
|B21
| -
|D
|
|
|
|-
|J5.21
|CSI_P2_DN3
|CPU.MIPI_CSI2_D3_N
|C19
| -
|D
|
|
|
|-
|J5.22
|CSI_P2_DP3
|CPU.MIPI_CSI2_D3_P
|D19
| -
|D
|
|
|
|-
|J5.23
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
| rowspan="4" |J5.24
| rowspan="4" |I2C4_SCL
| rowspan="4" |CPU.I2C4_SCL
| rowspan="4" |F8
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |
|ALT0
|I2C4_SCL
|-
|ALT1
|PWM2_OUT
|-
|ALT2
|PCIE1_CLKREQ_B
|-
|ALT5
|GPIO5_IO20
|-
| rowspan="4" |J5.25
| rowspan="4" |I2C4_SDA
| rowspan="4" |CPU.I2C4_SDA
| rowspan="4" |F9
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |
|ALT0
|I2C4_SDA
|-
|ALT1
|PWM1_OUT
|-
|ALT2
|PCIE2_CLKREQ_B
|-
|ALT5
|GPIO5_IO21
|}
U0007
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