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MITO 8M SOM/MITO 8M Hardware/Pinout Table

14,648 bytes added, 17:49, 28 December 2023
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<section begin="History" />
{| style="border-collapse:collapse; "
! colspan="4" style="width:100%; text-align:left" ; border-bottom:solid 2px #ededed" |History
|-
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Version
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Issue Date
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Notes
|-
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |1.0.0{{oldid| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" 10368|Sep 2020/09/29}}
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |First release
|-
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#ededed; padding:5px; color:#000000" |2021/02/02
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#ededed; padding:5px; color:#000000" |Add pull-up/down information
|-
|}
<section end="History" /><section begin="Body" />==Connectors and Pinout Table=====Introduction=description==
This chapter contains the pinout === Connectors description of ===In the following table are described all available connectors integrated on MITO 8M module, grouped in two tables (odd and even pins) that report the SOM:{| class="wikitable"|-!Connector name!Connector Type!Notes!Carrier board counterpart|-|J1|SODIMM edge connector 204 pin mapping of the 204|partially compatible with [[AXEL Lite SOM]]|TE Connectivity 2-2013289-1|-|J4|ONE PIECE connector single row 25pins||SAMTEC FSI-125-03-G-S-AD-TR|-|J5|ONE PIECE connector single row 25pins||SAMTEC FSI-125-03-G-S-pin SOAD-DIMM TR|}The dedicated carrier board must mount the mating connector and connect the desired peripheral interfaces according to MITO 8M connectorpinout specifications.See the images below for reference:
Each row in the pinout tables contains the following information[[File:MITO 8M-conn-TOP.png|500px|thumb|MITO 8M TOP view|none]][[File:MITO 8M-conn-BOTTOM.png|500px|thumb|MITO 8M BOTTOM view|none]]
===Pinout Table Below a detailed description of the pinout, grouped in the following tables:* two tables (ODD and EVEN pins declaration ===) that report the pin mapping of the 204-pin SO-DIMM edge* a dedicated tables for J4 one-piece connector* a dedicated tables for J5 one-piece connector
=== Pinout Table description ===Each row in the pinout tables contains the following information:{| class="wikitable" ! latexfontsize="scriptsize" | A-|'''Pin'''| Reference to the connector pin|-|'''Pin Name''' | Pin (signal) name on the MITO 8M connectors|-|'''Internal<br>connections''' | Connections to the components* CPU.<x> : pin connected to CPU pad named <x>* PMIC.<x> : pin connected to the Power Manager IC (NXP PF4210)* LAN.<x> : pin connected to the LAN PHY (MICROCHIP KSZ9031RNX)* BRIDGE.<x> : pin connected to the MIPI-to-LVDS bridge (TI SN65DSI84)|-|'''Ball/pin #''' | Component ball/pin number connected to signal|-|'''Voltage''' || I/O voltage levels |-|'''Type''' ! latexfontsize="scriptsize" | BPin type:! latexfontsize* I ="scriptsize" | CInput! latexfontsize* O ="scriptsize" | Output* D= Differential* Z = High impedance! latexfontsize* S ="scriptsize" | EPower supply voltage* G = Ground! latexfontsize* A ="scriptsize" Analog signal| F-! latexfontsize="scriptsize" | G'''Notes'''! colspan="2" latexfontsize="scriptsize" | HRemarks on special pin characteristics
|-
|A'''Pin MUX alternative functions'''|AMuxes:|A* Pin ALT-0* Pin ALT-1* Pin ALT-2|A* Pin ALT-3|A* Pin ALT-4|A* Pin ALT-5|A* Pin ALT-6|A* Pin ALT-7|A* Pin ALT-8
|-
|}
===Pinout Table EVEN SODIMM J1 ODD pins declaration ===
{| class="wikitable"
! latexfontsize="scriptsize" | Pin
! latexfontsize="scriptsize" | Pin Name
! latexfontsize="scriptsize" | Internal Connections
! latexfontsize="scriptsize" | Ball/pin #
! latexfontsize="scriptsize" |<nowiki>Voltage|domain</nowiki>
! latexfontsize="scriptsize" | Type
! latexfontsize="scriptsize" | Notes
! colspan="2" latexfontsize="scriptsize" | Alternative Functions
|-
|J1.21
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|-
|J1.43|3.3VIN
|INPUT VOLTAGE
| -
|
|-
|J1.65|3.3VIN
|INPUT VOLTAGE
| -
|
|-
|J1.87|3.3VIN
|INPUT VOLTAGE
| -
|
|-
|J1.109|3.3VIN
|INPUT VOLTAGE
| -
|
|-
|J1.1211
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|-
|J1.1413|PMIC_LICELL ETH0_LED1|PMICLAN.LICELLLED1/PME_N1|3017| -NVCC_1V8|SI/O|Must be level translated if used @ 3V3Internally pulled-up to 1.8V during bootstrap
|
|
|-
|J1.1615|CPU_ONOFFETH0_LED2|CPULAN.ONOFFLED2|W2115|NVCC_SNVSNVCC_1V8|I/O|internal pullMust be level translated if used @ 3V3Internally pulled-up 100k to NVCC_SNVS1.8V during bootstrap
|
|
|-
|J1.1817|BOARD_PGOODDGND|DGND
| -
| -
|NVCC_3V3|OG
|
|
|
|-
|J1.2019|BOOT_MODE_SELETH0_TXRX0_P|BOOT MODE SELECTIONLAN.TXRXP_A|2
| -
|NVCC_3V3D|I|internal pull-up to NVCC_3V3
|
|
|-
|J1.2221|CPU_PORnETH0_TXRX0_M|CPULAN.POR_BPMIC.RESETMCUTXRXM_A|W203|NVCC_SNVS-|I/OD|internal pull-up 100k to NVCC_SNVS
|
|
|-
|J1.2423|EXT_RESETETH0_TXRX1_P|MASTER RESETLAN.TXRXP_B|5
| -
|D
|
|
|
|-
|J1.25
|ETH0_TXRX1_M
|LAN.TXRXM_B
|6
| -
|ID|internal pull-up to NVCC_SNVS
|
|
|-
| rowspan="4" |J1.2627| rowspan="4" |SAI3_RXCETH0_TXRX2_P| rowspan="4" |CPULAN.SAI3_RXCTXRXP_C| rowspan="4" |F47| rowspan="4" |NVCC_3V3-| rowspan="4" |I/OD| rowspan="4" ||ALT0|SAI3_RX_BCLK
|-
|ALT1J1.29|ETH0_TXRX2_M|LAN.TXRXM_C|8| -|D||||-|J1.31|ETH0_TXRX3_P|LAN.TXRXP_D|10| -|D|||GPT1_CAPTURE2
|-
|ALT2J1.33|ETH0_TXRX3_M|LAN.TXRXM_D|11| -|D|||SAI5_RX_BCLK
|-
|ALT5J1.35|DGND|DGND| -| -|G|||GPIO4_IO29
|-
| rowspan="4" |J1.2837| rowspan="4" |GPIO1_IO02GPIO1_IO00| rowspan="4" |CPU.GPIO1_IO02GPIO1_IO00| rowspan="4" |R4T6
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |Internally used for SW reset, do not connect
|ALT0
|GPIO1_IO02GPIO1_IO00
|-
|ALT1
|WDOG1_WDOG_BCCM_ENET_PHY_REF_CLK_ROOT
|-
|ALT5
|WDOG1_WDOG_ANYANAMIX_REF_CLK_32K
|-
|ALT7|SJC_DE_B|-|J1.30|DGND|DGND| -|<nowiki>-</nowiki>|G||ALT6|CCM_EXT_CLK1
|-
| rowspan="4" |J1.3239| rowspan="4" |SAI3_RXDGPIO1_IO01| rowspan="4" |CPU.SAI3_RXDGPIO1_IO01| rowspan="4" |F3T7
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |Internally used for ETH PHY reset, do not connect
|ALT0
|SAI3_RX_DATA0GPIO1_IO01
|-
|ALT1
|GPT1_COMPARE1PWM1_OUT
|-
|ALT2ALT5|SAI5_RX_DATA0ANAMIX_REF_CLK_25M
|-
|ALT5ALT6|GPIO4_IO30CCM_EXT_CLK2
|-
| rowspan="3" |J1.3441| rowspan="3" |SAI2_MCLKSPDIF_EXT_CLK| rowspan="3" |CPU.SAI2_MCLKSPDIF_EXT_CLK| rowspan="3" |H5E6
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|SAI2_MCLKSPDIF1_EXT_CLK
|-
|ALT1
|SAI5_MCLKPWM1_OUT
|-
|ALT5
|GPIO4_IO27GPIO5_IO05
|-
| rowspan="43" |J1.3643| rowspan="43" |SAI3_RXFSGPIO1_IO13| rowspan="43" |CPU.SAI3_RXFSGPIO1_IO13| rowspan="43" |G4K6| rowspan="43" |NVCC_3V3| rowspan="43" |I/O| rowspan="43" |Internally used, do not connect
|ALT0
|SAI3_RX_SYNCGPIO1_IO13
|-
|ALT1
|GPT1_CAPTURE1USB1_OTG_OC|-|ALT5|PWM2_OUT|-|J1.45|VDD_PHY_1V8||||||||-| rowspan="3" |J1.47| rowspan="3" |ECSPI2_SCLK| rowspan="3" |CPU.ECSPI2_SCLK| rowspan="3" |C5| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|ECSPI2_SCLK
|-
|ALT2ALT1|SAI5_RX_SYNCUART4_RX
|-
|ALT5
|GPIO4_IO28GPIO5_IO10
|-
| rowspan="43" |J1.3849| rowspan="43" |I2C3_SCLECSPI2_MOSI| rowspan="43" |CPU.I2C3_SCLECSPI2_MOSI| rowspan="43" |G8E5| rowspan="43" |NVCC_3V3| rowspan="43" |I/O| rowspan="43" |
|ALT0
|I2C3_SCLECSPI2_MOSI
|-
|ALT1
|PWM4_OUT|-|ALT2|GPT2_CLKUART4_TX
|-
|ALT5
|GPIO5_IO18GPIO5_IO11
|-
| rowspan="43" |J1.4051| rowspan="43" |SAI3_TXFSGPIO1_IO08| rowspan="43" |CPU.SAI3_TXFSGPIO1_IO08| rowspan="43" |G3N7| rowspan="43" |NVCC_3V3| rowspan="43" |I/O| rowspan="43" |
|ALT0
|SAI3_TX_SYNCGPIO1_IO08
|-
|ALT1
|GPT1_CLK|-|ALT2|SAI5_RX_DATA1ENET1_1588_EVENT0_IN
|-
|ALT5
|GPIO4_IO31USDHC2_RESET_B
|-
| rowspan="3" |J1.4253| rowspan="3" |SPDIF_RXGPIO1_IO09| rowspan="3" |CPU.SPDIF_RXGPIO1_IO09| rowspan="3" |G6M7| rowspan="3" |NVCC_3V3| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|SPDIF1_INGPIO1_IO09
|-
|ALT1
|PWM2_OUTENET1_1588_EVENT0_OUT
|-
|ALT5
|GPIO5_IO04SDMA2_EXT_EVENT0
|-
| rowspan="3" |J1.4455| rowspan="3" |SPDIF_TXECSPI2_MISO| rowspan="3" |CPU.SPDIF_TXECSPI2_MISO| rowspan="3" |F6B5
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|SPDIF1_OUTECSPI2_MISO
|-
|ALT1
|PWM3_OUTUART4_CTS_B
|-
|ALT5
|GPIO5_IO03GPIO5_IO12|-|J1.57|DGND |DGND| -| -|G|||
|-
| rowspan="43" |J1.4659| rowspan="43" |SAI3_MCLKECSPI2_SS0| rowspan="43" |CPU.SAI3_MCLKECSPI2_SS0| rowspan="43" |D3A5| rowspan="43" |NVCC_3V3| rowspan="43" |I/O| rowspan="43" |
|ALT0
|SAI3_MCLKECSPI2_SS0
|-
|ALT1
|PWM4_OUT|-|ALT2|SAI5_MCLKUART4_RTS_B
|-
|ALT5
|GPIO5_IO02GPIO5_IO13
|-
| rowspan="43" |J1.4861| rowspan="43" |I2C3_SDAGPIO1_IO05| rowspan="43" |CPU.I2C3_SDAGPIO1_IO05| rowspan="43" |E9P7| rowspan="43" |NVCC_3V3| rowspan="43" |I/O| rowspan="43" |Internally used for MIPI-to-LVDS interrupt, do not connectPulled-up to NVCC_3V3
|ALT0
|I2C3_SDAGPIO1_IO05
|-
|ALT1
|PWM3_OUT|-|ALT2|GPT3_CLKM4_NMI
|-
|ALT5
|GPIO5_IO19CCM_PMIC_READY
|-
| rowspan="43" |J1.5063| rowspan="43" |SAI3_TXCI2C2_SCL| rowspan="43" |CPU.SAI3_TXCI2C2_SCL| rowspan="43" |C4G7| rowspan="43" |NVCC_3V3| rowspan="43" |I/O| rowspan="43" |
|ALT0
|SAI3_TX_BCLKI2C2_SCL
|-
|ALT1
|GPT1_COMPARE2|-|ALT2|SAI5_RX_DATA2ENET1_1588_EVENT1_IN
|-
|ALT5
|GPIO5_IO00GPIO5_IO16
|-
| rowspan="3" |J1.65| rowspan="3" |I2C2_SDA| rowspan="3" |CPU.I2C2_SDA| rowspan="3" |F7| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|I2C2_SDA|-|ALT1|ENET1_1588_EVENT1_OUT|-|ALT5|GPIO5_IO17|-| rowspan="4" |J1.5267| rowspan="4" |SAI3_TXDGPIO1_IO06| rowspan="4" |CPU.SAI3_TXDGPIO1_IO06| rowspan="4" |C3N5
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |Internally used for MIPI-to-LVDS enable, do not connect
|ALT0
|SAI3_TX_DATA0GPIO1_IO06
|-
|ALT1
|GPT1_COMPARE3ENET1_MDC
|-
|ALT2ALT5|SAI5_RX_DATA3USDHC1_CD_B
|-
|ALT5ALT6|GPIO5_IO01CCM_EXT_CLK3
|-
| rowspan="23" |J1.5469| rowspan="23" |GPIO1_IO10SAI2_RXC| rowspan="23" |CPU.GPIO1_IO10SAI2_RXC| rowspan="23" |M7H3| rowspan="23" |NVCC_3V3| rowspan="23" |I/O| rowspan="23" |Internally used for ETH PHY interrupt, do not connect
|ALT0
|GPIO1_IO10SAI2_RX_BCLK
|-
|ALT1
|USB1_OTG_IDSAI5_TX_BCLK
|-
|ALT5|GPIO4_IO22|-| rowspan="3" |J1.5671| rowspan="3" |SAI2_RXFS| rowspan="3" |CPU.SAI2_RXFS| rowspan="3" |J4| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|SAI2_RX_SYNC|-|ALT1|SAI5_TX_SYNC|-|ALT5|GPIO4_IO21|-|J1.73|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|-
| rowspan="42" |J1.5875| rowspan="42" |SAI5_MCLKSD2_DATA0| rowspan="42" |CPU.SAI5_MCLKSD2_DATA0| rowspan="42" |K4N22| rowspan="42" |NVCC_3V3| rowspan="42" |I/O| rowspan="42" |
|ALT0
|SAI5_MCLK|-|ALT1|SAI1_TX_BCLK|-|ALT2|SAI4_MCLKUSDHC2_DATA0
|-
|ALT5
|GPIO3_IO25GPIO2_IO15
|-
| rowspan="42" |J1.6077| rowspan="42" |GPIO1_IO15SD2_DATA1| rowspan="42" |CPU.GPIO1_IO15SD2_DATA1| rowspan="42" |J6N21| rowspan="42" |NVCC_3V3| rowspan="42" |I/O| rowspan="42" |
|ALT0
|GPIO1_IO15|-|ALT1|USB2_OTG_OCUSDHC2_DATA1
|-
|ALT5
|PWM4_OUTGPIO2_IO16
|-
|ALT6|CCM_CLKO2|-| rowspan="32" |J1.6279| rowspan="32" |SAI5_RXFSSD2_DATA2| rowspan="32" |CPU.SAI5_RXFSSD2_DATA2| rowspan="32" |N4P22| rowspan="32" |NVCC_3V3| rowspan="32" |I/O| rowspan="32" |
|ALT0
|SAI5_RX_SYNC|-|ALT1|SAI1_TX_DATA0USDHC2_DATA2
|-
|ALT5
|GPIO3_IO19GPIO2_IO17
|-
| rowspan="32" |J1.6481| rowspan="32" |SAI5_RXCSD2_DATA3| rowspan="32" |CPU.SAI5_RXCSD2_DATA03| rowspan="32" |L5P21| rowspan="32" |NVCC_3V3| rowspan="32" |I/O| rowspan="32" |
|ALT0
|SAI5_RX_BCLKUSDHC2_DATA3|-|ALT5|GPIO2_IO18
|-
|ALT1rowspan="2" |J1.83| rowspan="2" |SD2_CMD| rowspan="2" |CPU.SD2_CMD| rowspan="2" |M22| rowspan="2" |NVCC_3V3| rowspan="2" |I/O| rowspan="2" ||ALT0|SAI1_TX_DATA1USDHC2_CMD
|-
|ALT5
|GPIO3_IO20GPIO2_IO14
|-
| rowspan="32" |J1.6685| rowspan="32" |SAI2_TXCSD2_CLK| rowspan="32" |CPU.SAI2_TXCSD2_CLK| rowspan="32" |J5L22| rowspan="32" |NVCC_3V3| rowspan="32" |I/O| rowspan="32" |
|ALT0
|SAI2_TX_BCLK|-|ALT1|SAI5_TX_DATA2USDHC2_CLK
|-
|ALT5
|GPIO4_IO25GPIO2_IO13
|-
|J1.87|DGND |DGND| -| -|G||||-| rowspan="3" |J1.6889| rowspan="3" |SAI2_TXD0UART3_TXD| rowspan="3" |CPU.SAI2_TXD0UART3_TXD| rowspan="3" |G5B7
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|SAI2_TX_DATA0UART3_TX
|-
|ALT1
|SAI5_TX_DATA3UART1_RTS_B
|-
|ALT5
|GPIO4_IO26GPIO5_IO27
|-
| rowspan="3" |J1.7091| rowspan="3" |SAI2_TXFSUART3_RXD| rowspan="3" |CPU.SAI2_TXFSUART3_RXD| rowspan="3" |H4A6
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|SAI2_TX_SYNCUART3_RX
|-
|ALT1
|SAI5_TX_DATA1UART1_CTS_B
|-
|ALT5
|GPIO4_IO24GPIO5_IO26
|-
| rowspan="34" |J1.7293| rowspan="34" |SAI2_RXD0UART4_TXD| rowspan="34" |CPU.SAI2_RXD0UART4_TXD| rowspan="34" |H6D7| rowspan="34" |NVCC_3V3| rowspan="34" |I/O| rowspan="34" |
|ALT0
|SAI2_RX_DATA0UART4_TX
|-
|ALT1
|SAI5_TX_DATA0UART2_RTS_B|-|ALT2|PCIE2_CLKREQ_B
|-
|ALT5
|GPIO4_IO23GPIO5_IO29
|-
| rowspan="34" |J1.7495| rowspan="34" |SAI5_RXD0UART4_RXD| rowspan="34" |CPU.SAI5_RXD0UART4_RXD| rowspan="34" |M5C6| rowspan="34" |NVCC_3V3| rowspan="34" |I/O| rowspan="34" |
|ALT0
|SAI5_RX_DATA0 UART4_RX
|-
|ALT1
|SAI1_TX_DATA2UART2_CTS_B|-|ALT2|PCIE1_CLKREQ_B
|-
|ALT5
|GPIO3_IO21GPIO5_IO28
|-
| rowspan="52" |J1.7697| rowspan="52" |SAI5_RXD1SD2_WP| rowspan="52" |CPU.SAI5_RXD1SD2_WP| rowspan="52" |L4M21| rowspan="52" |NVCC_3V3| rowspan="52" |I/O| rowspan="52" |
|ALT0
|SAI5_RX_DATA1USDHC2_WP
|-
|ALT1ALT5|SAI1_TX_DATA3GPIO2_IO20
|-
|ALT2rowspan="2" |J1.99| rowspan="2" |SD2_RST_B| rowspan="2" |CPU.SD2_RESET_B|SAI1_TX_SYNCrowspan="2" |R22|-rowspan="2" |NVCC_3V3| rowspan="2" |I/O| rowspan="2" ||ALT3ALT0|SAI5_TX_SYNCUSDHC2_RESET_B
|-
|ALT5
|GPIO3_IO212GPIO2_IO19
|-
| rowspan="5" |J1.78101| rowspan="5" |SAI5_RXD2HDMI_DDC_SCL| rowspan="5" |CPU.SAI5_RXD2HDMI_DDC_SCL| rowspan="5" |M4R3| rowspan="5" |NVCC_3V3VDD_PHY_1V8| rowspan="5" |I/O| rowspan="5" ||ALT0|SAI5_RX_DATA2
|-
|ALT1J1.103|HDMI_DDC_SDA|CPU.HDMI_DDC_SDA|P3|VDD_PHY_1V8|I/O|||SAI1_TX_DATA4
|-
|ALT2J1.105|HDMI_AUX_N|CPU.HDMI_AUX_N|V2| -|D|connected with capacitor in series||SAI1_TX_SYNC
|-
|ALT3|SAI5_TX_BCLK|-|ALT5|GPIO3_IO23|-| rowspan="5" |J1.80107| rowspan="5" |SAI5_RXD3HDMI_AUX_P| rowspan="5" |CPU.SAI5_RXD3HDMI_AUX_P| rowspan="5" |K5V1| rowspan="5" |NVCC_3V3-| rowspan="5" |I/OD| rowspan="5" |connected with capacitor in series|ALT0|SAI5_RX_DATA3
|-
|ALT1|SAI1_TX_DATA5|-|ALT2|SAI1_TX_SYNC|-|ALT3|SAI5_TX_DATA0|-|ALT5|GPIO3_IO24|-|J1.82109|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|-
|J1.84111|CLK2_NHDMI_TX_M_LN_3|CPU.CLK2_NHDMI_TX_M_LN_3|T22M2|VDDA_1V8-|D|connected with capacitor in series|||-|J1.113|HDMI_TX_P_LN_3|CPU.HDMI_TX_P_LN_3|M1| -
|D
|connected with capacitor in series
|
|
|-
|J1.86115|CLK2_PHDMI_TX_M_LN_0|CPU.CLK2_PHDMI_TX_M_LN_0|U22T2|VDDA_1V8-
|D
|connected with capacitor in series
|
|
|-
|J1.88117|PCIE1_REF_CLKNHDMI_TX_P_LN_0|CPU.PCIE1_REF_PAD_CLK_NHDMI_TX_P_LN_0|K24T1|VDD_PHY_3V3-
|D
|connected with capacitor in series
|
|
|-
|J1.90119|PCIE1_REF_CLKPHDMI_TX_M_LN_1|CPU.PCIE1_REF_PAD_CLK_PHDMI_TX_M_LN_1|K25U1|VDD_PHY_3V3-
|D
|connected with capacitor in series
|
|
|-
|J1.92121|PCIE1_RXNHDMI_TX_P_LN_1|CPU.PCIE1_RXN_NHDMI_TX_P_LN_1|H24U2|VDD_PHY_3V3-
|D
|connected with capacitor in series
|
|
|-
|J1.94123|PCIE1_RXPHDMI_TX_M_LN_2|CPU.PCIE1_RXN_PHDMI_TX_M_LN_2|H25N1|VDD_PHY_3V3-
|D
|connected with capacitor in series
|
|
|-
|J1.125
|HDMI_TX_P_LN_2
|CPU.HDMI_TX_P_LN_2
|N2
| -
|D
|connected with capacitor in series
|
|
|-
|J1.96127|PCIE1_TXNHDMI_CEC|CPU.PCIE1_TXN_NHDMI_CEC|J24W3|VDD_PHY_3V3VDD_PHY_1V8|DI/O
|
|
|
|-
|J1.98129|PCIE1_TXPHDMI_HPD|CPU.PCIE1_TXN_PHDMI_HPD|J25W2|VDD_PHY_3V3VDD_PHY_1V8|DI/O
|
|
|
|-
|J1.100131|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|-
|J1.102133|CSI1_CLK_NLVDS0_CLK_N|CPUBRIDGE.MIPI_CSI1_CLK_NA_CLKN|A22F9
| -
|D
|
|-
|J1.104135|CSI1_CLK_PLVDS0_CLK_P|CPUBRIDGE.MIPI_CSI1_CLK_PA_CLKP|B22F8| -|D
|
|
|
|-
|J1.106137|CSI1_D0_NLVDS0_TX0_N|CPUBRIDGE.MIPI_CSI1_D0_NA_Y0N|A23C9
| -
|D
|
|-
|J1.108139|CSI1_D0_PLVDS0_TX0_P|CPUBRIDGE.MIPI_CSI1_D0_PA_Y0P|B23C8
| -
|D
|
|-
|J1.110141|CSI1_D1_NLVDS0_TX1_N|CPUBRIDGE.MIPI_CSI1_D1_NA_Y1N|C22D9
| -
|D
|
|-
|J1.112143|CSI1_D1_PLVDS0_TX1_P|CPUBRIDGE.MIPI_CSI1_D1_PA_Y1P|D22D8
| -
|D
|
|-
|J1.114145|CSI1_D2_NLVDS0_TX2_N|CPUBRIDGE.MIPI_CSI1_D2_NA_Y2N|B24E9
| -
|D
|
|-
|J1.116147|CSI1_D2_PLVDS0_TX2_P|CPUBRIDGE.MIPI_CSI1_D2_PA_Y2P|C23E8
| -
|D
|
|-
|J1.118149|CSI1_D3_NLVDS0_TX3_N|CPUBRIDGE.MIPI_CSI1_D3_NA_Y3N|C21G9
| -
|D
|
|-
|J1.120151|CSI1_D3_PLVDS0_TX3_P|CPUBRIDGE.MIPI_CSI1_D3_PA_Y3P|D21G8
| -
|D
|
|-
|J1.122153|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|-
|J1.124(NAND on board)155|NAND_DQSLVDS1_CLK_N|CPUBRIDGE.NAND_DQSB_CLKN|M20A6|NVCC_3V3-|I/OD|Internally used for NAND, do not connect
|
|
|-
| rowspan="3" |J1.124(eMMC on board)157| rowspan="3" |NAND_DQSLVDS1_CLK_P| rowspan="3" |CPUBRIDGE.NAND_DQSB_CLKP| rowspan="3" |M20B6| rowspan="3" |NVCC_3V3-| rowspan="3" |I/OD| rowspan="3" ||ALT0|RAWNAND_DQS
|-
|ALT1J1.159|LVDS1_TX0_N|BRIDGE.B_Y0N|A3| -|D||||-|J1.161|LVDS1_TX0_P|BRIDGE.B_Y0P|B3| -|D|||QSPI_A_DQS
|-
|ALT5J1.163|LVDS1_TX1_N|BRIDGE.B_Y1N|A4| -|D|||GPIO3_IO14
|-
|J1.126(NAND on board)165|NAND_ALELVDS1_TX1_P|CPUBRIDGE.NAND_ALEB_Y1P|G19B4|NVCC_3V3-|I/OD|Internally used for NAND, do not connect
|
|
|-
| rowspan="3" J1.167|LVDS1_TX2_N|J1BRIDGE.126B_Y2N(eMMC on board)|A5| rowspan="3" -|NAND_ALED| rowspan="3" ||CPU.NAND_ALE| rowspan="3" -|G19J1.169| rowspan="3" LVDS1_TX2_P|NVCC_3V3BRIDGE.B_Y2P| rowspan="3" B5|I/O-| rowspan="3" D||ALT0|RAWNAND_ALE
|-
|ALT1J1.171|LVDS1_TX3_N|BRIDGE.B_Y3N|A7| -|D|||QSPI_A_SCLK
|-
|ALT5J1.173|LVDS1_TX3_P|BRIDGE.B_Y3P|B7| -|D|||GPIO3_IO00
|-
|J1.175|DGND |DGND| -| -|G||||-| rowspan="2" |J1.128(NAND on board)177| rowspan="2" |SD1_CLKSD2_CD_B| rowspan="2" |CPU.SD1_CLKSD2_CD_B| rowspan="2" |L25L21
| rowspan="2" |NVCC_3V3
(NVCC_1V8 on request)
| rowspan="2" |I/O
| rowspan="2" |
|ALT0
|USDHC1_CLKUSDHC2_CD_B
|-
|ALT5
|GPIO2_IO00GPIO2_IO12
|-
| rowspan="3" |J1.128(eMMC on board)179| rowspan="3" |NAND_CE0_BECSPI1_SS0| rowspan="3" |CPU.NAND_CE0_BECSPI1_SS0| rowspan="3" |H19D4
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|RAWNAND_CE0_BECSPI1_SS0
|-
|ALT1
|QSPI_A_SS0_BUART3_RTS_B
|-
|ALT5
|GPIO3_IO01GPIO5_IO09
|-
| rowspan="23" |J1.130(NAND on board)181| rowspan="23" |SD1_CMDECSPI1_SCLK| rowspan="23" |CPU.SD1_CMDECSPI1_SCLK| rowspan="23" |L24D5| rowspan="23" |NVCC_3V3(NVCC_1V8 on request)| rowspan="23" |I/O| rowspan="23" |
|ALT0
|USDHC1_CMDECSPI1_SCLK|-|ALT1|UART3_RX
|-
|ALT5
|GPIO2_IO01GPIO5_IO06
|-
| rowspan="3" |J1.130(eMMC on board)183| rowspan="3" |NAND_CE1_BECSPI1_MISO| rowspan="3" |CPU.NAND_CE1_BECSPI1_MISO| rowspan="3" |G21B4
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|RAWNAND_CE1_BECSPI1_MISO
|-
|ALT1
|QSPI_A_SS1_BUART3_CTS_B
|-
|ALT5
|GPIO3_IO02GPIO5_IO08
|-
| rowspan="23" |J1.132(NAND on board)185| rowspan="23" |SD1_RST_BGPIO1_IO03| rowspan="23" |CPU.SD1_RST_BGPIO1_IO03| rowspan="23" |R24P4| rowspan="23" |NVCC_3V3(NVCC_1V8 on request)| rowspan="23" |I/O| rowspan="23" |
|ALT0
|USDHC1_RESET_BGPIO1_IO03|-|ALT1|USDHC1_VSELECT
|-
|ALT5
|GPIO2_IO10SDMA1_EXT_EVENT0
|-
| rowspan="3" |J1.132(eMMC on board)187| rowspan="3" |NAND_CE2_BUART2_TXD| rowspan="3" |CPU.NAND_CE2_BUART2_TXD| rowspan="3" |F21D6
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |used as default Linux console
|ALT0
|RAWNAND_CE2_BUART2_TX
|-
|ALT1
|QSPI_B_SS0_BECSPI3_SS0
|-
|ALT5
|GPIO3_IO03GPIO5_IO25
|-
| rowspan="23" |J1.134(NAND on board)189| rowspan="23" |SD1_STROBEUART2_RXD| rowspan="23" |CPU.SD1_STROBEUART2_RXD| rowspan="23" |T24B6| rowspan="23" |NVCC_3V3(NVCC_1V8 on request)| rowspan="23" |I/O| rowspan="23" |used as default Linux console
|ALT0
|USDHC1_STROBEUART2_RXD|-|ALT1|ECSPI3_MISO
|-
|ALT5
|GPIO2_IO11GPIO5_IO24
|-
| rowspan="3" |J1.134(eMMC on board)191| rowspan="3" |NAND_CE3_BUART1_TXD| rowspan="3" |CPU.NAND_CE3_BUART1_TXD| rowspan="3" |H20A7
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|RAWNAND_CE3_BUART1_TX
|-
|ALT1
|QSPI_B_SS1_BECSPI3_MOSI
|-
|ALT5
|GPIO3_IO034GPIO5_IO23
|-
| rowspan="3" |J1.136193(NAND on board)| rowspan="3" |UART1_RXD|NAND_CLErowspan="3" |CPU.NAND_CLEUART1_RXD|H21rowspan="3" |C7| rowspan="3" |NVCC_3V3| rowspan="3" |I/O|Internally used for NAND, do not connectrowspan="3" ||ALT0|UART1_RXD
|-
|ALT1|ECSPI3_SCLK|-|ALT5|GPIO5_IO22|-| rowspan="3" |J1.136(eMMC on board)195| rowspan="3" |NAND_CLEECSPI1_MOSI| rowspan="3" |CPU.NAND_CLEECSPI1_MOSI| rowspan="3" |H21A4
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|RAWNAND_CLEECSPI1_MOSI
|-
|ALT1
|QSPI_B_SCLKUART3_TX
|-
|ALT5
|GPIO3_IO05GPIO5_IO07
|-
| rowspan="24" |J1.138(NAND on board)197| rowspan="24" |SD1_DATA0GPIO1_IO14| rowspan="24" |CPU.SD1_DATA0GPIO1_IO14| rowspan="24" |M25K7| rowspan="24" |NVCC_3V3(NVCC_1V8 on request)| rowspan="24" |I/O| rowspan="24" |
|ALT0
|USDHC1_DATA0GPIO1_IO14|-|ALT1|USB2_OTG_PWR
|-
|ALT5
|GPIO2_IO02PWM3_OUT|-|ALT6|CCM_CLKO1
|-
| rowspan="3" |J1.138(eMMC on board)199| rowspan="3" |NAND_DATA00GPIO1_IO04| rowspan="3" |CPU.NAND_DATA00GPIO1_IO04| rowspan="3" |G20P5| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|RAWNAND_DATA00GPIO1_IO04
|-
|ALT1
|QSPI_A_DATA0USDHC2_VSELECT
|-
|ALT5
|GPIO3_IO06|-| rowspan="2" |J1.140(NAND on board)| rowspan="2" |SD1_DATA1| rowspan="2" |CPU.SD1_DATA1| rowspan="2" |M24| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_DATA1SDMA1_EXT_EVENT1
|-
|ALT5|GPIO2_IO0|-| rowspan="3" |J1.140(eMMC on board)201| rowspan="3" |NAND_DATA01GPIO1_IO12| rowspan="3" |CPU.NAND_DATA01GPIO1_IO12| rowspan="3" |J20L7
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|RAWNAND_DATA01GPIO1_IO12
|-
|ALT1
|QSPI_A_DATA1USB1_OTG_PWR
|-
|ALT5
|GPIO3_IO07SDMA2_EXT_EVENT1
|-
| rowspan="2" |J1.142(NAND on board)203| rowspan="2" |SD1_DATA2DGND | rowspan="2" |CPU.SD1_DATA2DGND| rowspan="2" |N25-| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)-| rowspan="2" |I/OG| rowspan="2" ||ALT0|USDHC1_DATA2
|-
|ALT5} ==SODIMM J1 EVEN pins declaration == {| class="wikitable" ! latexfontsize="scriptsize" | Pin ! latexfontsize="scriptsize" | Pin Name! latexfontsize="scriptsize" | Internal Connections ! latexfontsize="scriptsize" | Ball/pin # ! latexfontsize="scriptsize" | Voltage domain ! latexfontsize="scriptsize" | Type ! latexfontsize="scriptsize" | Notes! colspan="2" latexfontsize="scriptsize" |GPIO2_IO04Alternative Functions
|-
| rowspan="3" |J1.1422(eMMC on board)| rowspan="3" |NAND_DATA02DGND| rowspan="3" |CPU.NAND_DATA02DGND| rowspan="3" |H22-| rowspan="3" |NVCC_3V3<nowiki>-</nowiki>| rowspan="3" |I/OG| rowspan="3" ||ALT0|RAWNAND_DATA02
|-
|ALT1J1.4|3.3VIN |INPUT VOLTAGE| -|3.3VIN|S|||QSPI_A_DATA2
|-
|ALT5J1.6|3.3VIN |INPUT VOLTAGE| -|3.3VIN|S|||GPIO3_IO08
|-
| rowspan="2" |J1.144(NAND on board)8| rowspan="2" |SD1_DATA33.3VIN | rowspan="2" |CPU.SD1_DATA3INPUT VOLTAGE| rowspan="2" |P25-| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)3.3VIN| rowspan="2" |I/OS| rowspan="2" ||ALT0|USDHC1_DATA3
|-
|ALT5J1.10|3.3VIN |INPUT VOLTAGE| -|3.3VIN|S|||GPIO2_IO05
|-
| rowspan="3" |J1.144(eMMC on board)| rowspan="3" |NAND_DATA03| rowspan="3" |CPU.NAND_DATA03| rowspan="3" |J21| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_DATA03|-|ALT1|QSPI_A_DATA3|-|ALT5|GPIO3_IO09|-|J1.14612|DGND|DGND| -
|<nowiki>-</nowiki>
|G
|
|-
| rowspan="2" |J1.148(NAND on board)14| rowspan="2" |SD1_DATA4PMIC_LICELL | rowspan="2" |CPUPMIC.SD1_DATA4LICELL| rowspan="2" |N2430| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)-| rowspan="2" |I/OS| rowspan="2" ||ALT0|USDHC1_DATA4
|-
|ALT5J1.16|CPU_ONOFF|CPU.ONOFF|W21|NVCC_SNVS|I|internal pull-up 100k to NVCC_SNVS||GPIO2_IO06
|-
| rowspan="3" |J1.148(eMMC on board)18| rowspan="3" |NAND_DATA04BOARD_PGOOD| rowspan="3" |CPU.NAND_DATA04-| rowspan="3" |L20-| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_DATA04
|-
|ALT1J1.20|BOOT_MODE_SEL|BOOT MODE SELECTION| -|NVCC_3V3|I|internal pull-up to NVCC_3V3||QSPI_B_DATA0
|-
|ALT5J1.22|CPU_PORn|CPU.POR_BPMIC.RESETMCU|W203|NVCC_SNVS|I/O|internal pull-up 100k to NVCC_SNVS||GPIO3_IO10
|-
| rowspan="2" |J1.150(NAND on board)24| rowspan="2" |SD1_DATA5EXT_RESET| rowspan="2" |CPU.SD1_DATA5MASTER RESET| rowspan="2" |P24-| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)-| rowspan="2" |I/O| rowspan="2" |internal pull-up to NVCC_SNVS|ALT0|USDHC1_DATA5
|-
|ALT5|GPIO2_IO07|-| rowspan="34" |J1.150(eMMC on board)26| rowspan="34" |NAND_DATA05SAI3_RXC| rowspan="34" |CPU.NAND_DATA05SAI3_RXC| rowspan="34" |J22F4| rowspan="34" |NVCC_3V3| rowspan="34" |I/O| rowspan="34" |
|ALT0
|RAWNAND_DATA05SAI3_RX_BCLK
|-
|ALT1
|QSPI_B_DATA1GPT1_CAPTURE2|-|ALT2|SAI5_RX_BCLK
|-
|ALT5
|GPIO3_IO11GPIO4_IO29
|-
| rowspan="24" |J1.152(NAND on board)28| rowspan="24" |SD1_DATA6GPIO1_IO02| rowspan="24" |CPU.SD1_DATA6GPIO1_IO02| rowspan="24" |R25R4| rowspan="24" |NVCC_3V3(NVCC_1V8 on request)| rowspan="24" |I/O| rowspan="24" |Internally used for SW reset, do not connect
|ALT0
|USDHC1_DATA6|-|ALT5|GPIO2_IO08|-| rowspan="3" |J1.152(eMMC on board)| rowspan="3" |NAND_DATA06| rowspan="3" |CPU.NAND_DATA06| rowspan="3" |L19| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_DATA06GPIO1_IO02
|-
|ALT1
|QSPI_B_DATA2WDOG1_WDOG_B
|-
|ALT5
|GPIO3_IO12WDOG1_WDOG_ANY
|-
|ALT7|SJC_DE_B|-|J1.30|DGND|DGND| -|<nowiki>-</nowiki>|G||||-| rowspan="24" |J1.154(NAND on board)32| rowspan="24" |SD1_DATA7SAI3_RXD| rowspan="24" |CPU.SD1_DATA7SAI3_RXD| rowspan="24" |T25F3| rowspan="24" |NVCC_3V3(NVCC_1V8 on request)| rowspan="24" |I/O| rowspan="24" |
|ALT0
|USDHC1_DATA7SAI3_RX_DATA0
|-
|ALT5ALT1|GPIO2_IO09GPT1_COMPARE1
|-
|ALT2|SAI5_RX_DATA0|-|ALT5|GPIO4_IO30|-| rowspan="3" |J1.154(eMMC on board)34| rowspan="3" |NAND_DATA07SAI2_MCLK| rowspan="3" |CPU.NAND_DATA07SAI2_MCLK| rowspan="3" |M19H5
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|RAWNAND_DATA07SAI2_MCLK
|-
|ALT1
|QSPI_B_DATA3SAI5_MCLK
|-
|ALT5
|GPIO3_IO13GPIO4_IO27
|-
| rowspan="4" |J1.15636(NAND on board)| rowspan="4" |SAI3_RXFS|NAND_RE_Browspan="4" |CPU.NAND_RE_BSAI3_RXFS|K19rowspan="4" |G4| rowspan="4" |NVCC_3V3| rowspan="4" |I/O|Internally used for NAND, do not connectrowspan="4" ||ALT0|SAI3_RX_SYNC|-|ALT1|GPT1_CAPTURE1|-|ALT2|SAI5_RX_SYNC|-|ALT5|GPIO4_IO28
|-
| rowspan="34" |J1.156(eMMC on board)38| rowspan="34" |NAND_RE_BI2C3_SCL| rowspan="34" |CPU.NAND_RE_BI2C3_SCL| rowspan="34" |K19G8| rowspan="34" |NVCC_3V3| rowspan="34" |I/O| rowspan="34" |
|ALT0
|RAWNAND_RE_BI2C3_SCL
|-
|ALT1
|QSPI_B_DQSPWM4_OUT|-|ALT2|GPT2_CLK
|-
|ALT5
|GPIO3_IO15GPIO5_IO18
|-
|J1.158(NAND on board)|NAND_READY_B|CPU.NAND_READY_B|K20|NVCC_3V3|I/O|Internally used for NAND, do not connect|||-| rowspan="24" |J1.158(eMMC on board)40| rowspan="24" |NAND_READY_BSAI3_TXFS| rowspan="24" |CPU.NAND_READY_BSAI3_TXFS| rowspan="24" |K20G3| rowspan="24" |NVCC_3V3| rowspan="24" |I/O| rowspan="24" |
|ALT0
|RAWNAND_READY_BSAI3_TX_SYNC
|-
|ALT5ALT1|GPIO3_IO16GPT1_CLK
|-
|J1.160(NAND on board)|NAND_WE_B|CPU.NAND_WE_B|K22|NVCC_3V3ALT2|I/OSAI5_RX_DATA1|Internally used for NAND, do not connect-|ALT5|GPIO4_IO31
|-
| rowspan="23" |J1.160(eMMC on board)42| rowspan="23" |NAND_WE_BSPDIF_RX| rowspan="23" |CPU.NAND_WE_BSPDIF_RX| rowspan="23" |K22G6| rowspan="23" |NVCC_3V3| rowspan="23" |I/O| rowspan="23" |
|ALT0
|RAWNAND_WE_BSPDIF1_IN|-|ALT1|PWM2_OUT
|-
|ALT5
|GPIO3_IO17GPIO5_IO04
|-
| rowspan="3" |J1.16244(NAND on board)| rowspan="3" |SPDIF_TX|NAND_WP_Browspan="3" |CPU.NAND_WP_BSPDIF_TX|K21rowspan="3" |F6| rowspan="3" |NVCC_3V3| rowspan="3" |I/O|Internally used for NAND, do not connectrowspan="3" ||ALT0|SPDIF1_OUT
|-
| rowspan="2" |J1.162(eMMC on board)| rowspan="2" |NAND_WP_B| rowspan="2" |CPU.NAND_WP_B| rowspan="2" |K21| rowspan="2" |NVCC_3V3| rowspan="2" |I/O| rowspan="2" ||ALT0ALT1|RAWNAND_WP_BPWM3_OUT
|-
|ALT5
|GPIO3_IO18GPIO5_IO03
|-
| rowspan="4" |J1.16446|DGNDrowspan="4" |SAI3_MCLK|DGNDrowspan="4" |CPU.SAI3_MCLK| -rowspan="4" |D3| rowspan="4" |NVCC_3V3|<nowiki>-<rowspan="4" |I/nowiki>O| rowspan="4" ||ALT0|GSAI3_MCLK|-|ALT1|PWM4_OUT
|-
|J1.166|CLK1_N|CPU.CLK1_N|T23||D||ALT2|SAI5_MCLK
|-
|ALT5|GPIO5_IO02|-| rowspan="4" |J1.16848|CLK1_Prowspan="4" |I2C3_SDA| rowspan="4" |CPU.CLK1_PI2C3_SDA|R23rowspan="4" |E9|rowspan="4" |NVCC_3V3|Drowspan="4" |I/O| rowspan="4" ||ALT0|I2C3_SDA
|-
|J1.170|USB2_RXN|CPU.USB2_RX_N|B8||D||ALT1|PWM3_OUT
|-
|J1.172|USB2_RXP|CPU.USB2_RX_P|A8||D||ALT2|GPT3_CLK
|-
|J1.174|USB2_TXN|CPU.USB2_TX_N|B9||D||ALT5|GPIO5_IO19
|-
| rowspan="4" |J1.17650|USB2_TXProwspan="4" |SAI3_TXC| rowspan="4" |CPU.USB2_TX_PSAI3_TXC|A9rowspan="4" |C4|rowspan="4" |NVCC_3V3|Drowspan="4" |I/O| rowspan="4" ||ALT0|SAI3_TX_BCLK
|-
|J1.178|USB1_RXN|CPU.USB1_RX_N|B12||D||ALT1|GPT1_COMPARE2
|-
|J1.180|USB1_RXP|CPU.USB1_RX_P|A12||D||ALT2|SAI5_RX_DATA2
|-
|J1.182|USB1_TXN|CPU.USB1_TX_N|B13||D||ALT5|GPIO5_IO00
|-
| rowspan="4" |J1.18452|USB1_TXProwspan="4" |SAI3_TXD| rowspan="4" |CPU.USB1_TX_PSAI3_TXD|A13rowspan="4" |C3| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|DSAI3_TX_DATA0|-|ALT1|GPT1_COMPARE3
|-
|J1.186|USB1_VBUS|CPU.USB1_VBUS|D14| -|S||ALT2|SAI5_RX_DATA3
|-
|ALT5|GPIO5_IO01|-| rowspan="2" |J1.18854|USB2_VBUSrowspan="2" |GPIO1_IO10| rowspan="2" |CPU.USB2_VBUSGPIO1_IO10| rowspan="2" |M7| rowspan="2" |NVCC_3V3|D9rowspan="2" |I/O| -rowspan="2" |Internally used for ETH PHY interrupt, do not connect|ALT0|SGPIO1_IO10|-|ALT1|USB1_OTG_ID
|-
|J1.19056
|DGND
|DGND
|
|-
| rowspan="4" |J1.19258|USB1_IDrowspan="4" |SAI5_MCLK| rowspan="4" |CPU.USB1_IDSAI5_MCLK|C14rowspan="4" |K4|VDD_PHY_3V3rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|SAI5_MCLK
|-
|J1.194|USB2_ID|CPU.USB2_ID|C9|VDD_PHY_3V3|I||ALT1|SAI1_TX_BCLK
|-
|J1.196|USB1_DN|CPU.USB1_DN|B14| -|D||ALT2|SAI4_MCLK
|-
|J1.198|USB1_DP|CPU.USB1_DP|A14| -|D||ALT5|GPIO3_IO25
|-
| rowspan="4" |J1.20060|USB2_DProwspan="4" |GPIO1_IO15| rowspan="4" |CPU.USB2_DPGPIO1_IO15| rowspan="4" |J6|A10rowspan="4" |NVCC_3V3| -rowspan="4" |I/O| rowspan="4" ||ALT0|DGPIO1_IO15|-|ALT1|USB2_OTG_OC
|-
|J1.202|USB2_DN|CPU.USB2_DN|B10| -|D||ALT5|PWM4_OUT
|-
|ALT6|CCM_CLKO2|-| rowspan="3" |J1.20462|DGNDrowspan="3" |SAI5_RXFS|DGNDrowspan="3" |CPU.SAI5_RXFS| -rowspan="3" |N4| rowspan="3" |NVCC_3V3|<nowiki>-<rowspan="3" |I/nowiki>O|Growspan="3" ||ALT0|SAI5_RX_SYNC
|-
|}ALT1 ===Pinout Table J4 pins declaration ==={| class="wikitable" ! latexfontsize="scriptsize" | Pin ! latexfontsize="scriptsize" | Pin Name! latexfontsize="scriptsize" | Internal Connections ! latexfontsize="scriptsize" | Ball/pin # ! latexfontsize="scriptsize" |<nowiki>Voltage|domain</nowiki>! latexfontsize="scriptsize" | Type ! latexfontsize="scriptsize" | Notes! colspan="2" |Alternative FunctionsSAI1_TX_DATA0
|-
|J4.1|DGND|DGND| -|<nowiki>-</nowiki>|G||ALT5|GPIO3_IO19
|-
| rowspan="73" |J4J1.264| rowspan="73" |SAI1_RXD7SAI5_RXC| rowspan="73" |CPU.SAI1_RXD7SAI5_RXC| rowspan="73" |G1L5| rowspan="73" |NVCC_3V3| rowspan="73" |I/O| rowspan="73" |internally used for BOOT config
|ALT0
|SAI1_RX_DATA7SAI5_RX_BCLK
|-
|ALT1
|SAI6_MCLK|-|ALT2|SAI1_TX_SYNC|-|ALT3|SAI1_TX_DATA4|-|ALT4|CORESIGHT_TRACE7SAI1_TX_DATA1
|-
|ALT5
|GPIO4_IO09GPIO3_IO20
|-
|ALT6|SRC_BOOT_CFG7|-| rowspan="63" |J4J1.366| rowspan="63" |SAI1_RXD6SAI2_TXC| rowspan="63" |CPU.SAI1_RXD6SAI2_TXC| rowspan="63" |G2J5| rowspan="63" |NVCC_3V3| rowspan="63" |I/O| rowspan="63" |internally used for BOOT config
|ALT0
|SAI1_RX_DATA6SAI2_TX_BCLK
|-
|ALT1
|SAI6_TX_SYNC|-|ALT2|SAI6_RX_SYNC|-|ALT4|CORESIGHT_TRACE6SAI5_TX_DATA2
|-
|ALT5
|GPIO4_IO08GPIO4_IO25
|-
|ALT6|SRC_BOOT_CFG6|-| rowspan="73" |J4J1.468| rowspan="73" |SAI1_RXD5SAI2_TXD0| rowspan="73" |CPU.SAI1_RXD5SAI2_TXD0| rowspan="73" |F1G5| rowspan="73" |NVCC_3V3| rowspan="73" |I/O| rowspan="73" |internally used for BOOT config
|ALT0
|SAI1_RX_DATA5SAI2_TX_DATA0
|-
|ALT1
|SAI6_TX_DATA0SAI5_TX_DATA3
|-
|ALT2ALT5|SAI6_RX_DATA0GPIO4_IO26
|-
|ALT3rowspan="3" |J1.70| rowspan="3" |SAI2_TXFS| rowspan="3" |CPU.SAI2_TXFS| rowspan="3" |H4| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|SAI1_RX_SYNCSAI2_TX_SYNC
|-
|ALT4ALT1|CORESIGHT_TRACE5SAI5_TX_DATA1
|-
|ALT5
|GPIO4_IO07GPIO4_IO24
|-
|ALT6|SRC_BOOT_CFG5|-| rowspan="63" |J4J1.572| rowspan="63" |SAI1_RXD4SAI2_RXD0| rowspan="63" |CPU.SAI1_RXD4SAI2_RXD0| rowspan="63" |J1H6| rowspan="63" |NVCC_3V3| rowspan="63" |I/O| rowspan="63" |internally used for BOOT config
|ALT0
|SAI1_RX_DATA4SAI2_RX_DATA0
|-
|ALT1
|SAI6_TX_BCLK|-|ALT2|SAI6_RX_BCLK|-|ALT4|CORESIGHT_TRACE4SAI5_TX_DATA0
|-
|ALT5
|GPIO4_IO06GPIO4_IO23
|-
|ALT6|SRC_BOOT_CFG4|-| rowspan="53" |J4J1.674| rowspan="53" |SAI1_RXD3SAI5_RXD0| rowspan="53" |CPU.SAI1_RXD3SAI5_RXD0| rowspan="53" |J2M5| rowspan="53" |NVCC_3V3| rowspan="53" |I/O| rowspan="53" |internally used for BOOT config
|ALT0
|SAI1_RX_DATA3SAI5_RX_DATA0
|-
|ALT1
|SAI5_RX_DATA3|-|ALT4|CORESIGHT_TRACE3SAI1_TX_DATA2
|-
|ALT5
|GPIO4_IO05GPIO3_IO21
|-
|ALT6|SRC_BOOT_CFG3|-| rowspan="5" |J4J1.776| rowspan="5" |SAI1_RXD2SAI5_RXD1| rowspan="5" |CPU.SAI1_RXD2SAI5_RXD1| rowspan="5" |H2L4
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |internally used for BOOT config
|ALT0
|SAI1_RX_DATA2SAI5_RX_DATA1
|-
|ALT1
|SAI5_RX_DATA2SAI1_TX_DATA3
|-
|ALT4ALT2|CORESIGHT_TRACE2SAI1_TX_SYNC|-|ALT3|SAI5_TX_SYNC
|-
|ALT5
|GPIO4_IO04GPIO3_IO212
|-
|ALT6|SRC_BOOT_CFG2|-| rowspan="5" |J4J1.878| rowspan="5" |SAI1_RXD1SAI5_RXD2| rowspan="5" |CPU.SAI1_RXD1SAI5_RXD2| rowspan="5" |L2M4
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |internally used for BOOT config
|ALT0
|SAI1_RX_DATA1SAI5_RX_DATA2
|-
|ALT1
|SAI5_RX_DATA1SAI1_TX_DATA4|-|ALT2|SAI1_TX_SYNC
|-
|ALT4ALT3|CORESIGHT_TRACE1SAI5_TX_BCLK
|-
|ALT5
|GPIO4_IO03GPIO3_IO23
|-
|ALT6|SRC_BOOT_CFG1|-| rowspan="5" |J4J1.980| rowspan="5" |SAI1_RXD0SAI5_RXD3| rowspan="5" |CPU.SAI1_RXD0SAI5_RXD3| rowspan="5" |K2K5
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |internally used for BOOT config
|ALT0
|SAI1_RX_DATA0SAI5_RX_DATA3
|-
|ALT1
|SAI5_RX_DATA0SAI1_TX_DATA5|-|ALT2|SAI1_TX_SYNC
|-
|ALT4ALT3|CORESIGHT_TRACE0SAI5_TX_DATA0
|-
|ALT5
|GPIO4_IO02GPIO3_IO24
|-
|ALT6J1.82|DGND|DGND| -|<nowiki>-</nowiki>|G|||SRC_BOOT_CFG0
|-
| rowspan="4" |J4J1.1084| rowspan="4" |SAI1_RXCCLK2_N| rowspan="4" |CPU.SAI1_RXCCLK2_N| rowspan="4" |K1T22| rowspan="4" |NVCC_3V3VDDA_1V8| rowspan="4" |I/OD| rowspan="4" |Internally used for PCIe CLK, do not connect|ALT0|SAI1_RX_BCLK
|-
|ALT1J1.86|CLK2_P|CPU.CLK2_P|U22|VDDA_1V8|D|Internally used for PCIe CLK, do not connect||SAI5_RX_BCLK
|-
|ALT4J1.88|PCIE1_REF_CLKN|CPU.PCIE1_REF_PAD_CLK_N|K24|VDD_PHY_3V3|D|||CORESIGHT_TRACE_CTL
|-
|ALT5|GPIO4_IO01|-| rowspan="4" |J4J1.1190| rowspan="4" |SAI1_RXFSPCIE1_REF_CLKP| rowspan="4" |CPU.SAI1_RXFS| rowspan="4" |L1| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|SAI1_RX_SYNC|-|ALT1|SAI5_RX_SYNC|-|ALT4|CORESIGHT_TRACE_CLK|-|ALT5|GPIO4_IO00|-|J4.12|DGND|DGNDPCIE1_REF_PAD_CLK_P| -K25|<nowiki>-</nowiki>VDD_PHY_3V3|GD
|
|
|
|-
| rowspan="4" |J4J1.1392| rowspan="4" |SAI1_MCLKPCIE1_RXN| rowspan="4" |CPU.SAI1_MCLK| rowspan="4" || rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|SAI1_MCLK|-|ALT1|SAI5_MCLK |-|ALT2|SAI1_TX_BCLK|-|ALT5|GPIO4_IO20|-|J4.14|DGND|DGNDPCIE1_RXN_N| -H24|<nowiki>-</nowiki>VDD_PHY_3V3|GD
|
|
|
|-
| rowspan="4" |J4J1.1594| rowspan="4" |SAI1_TXFSPCIE1_RXP| rowspan="4" |CPU.SAI1_TXFSPCIE1_RXN_P| rowspan="4" |H4H25| rowspan="4" |NVCC_3V3VDD_PHY_3V3| rowspan="4" |I/OD| rowspan="4" ||ALT0|SAI1_TX_SYNC
|-
|ALT1J1.96|PCIE1_TXN|CPU.PCIE1_TXN_N|J24|VDD_PHY_3V3|D|||SAI5_TX_SYNC
|-
|ALT4J1.98|PCIE1_TXP|CPU.PCIE1_TXN_P|J25|VDD_PHY_3V3|D|||CORESIGHT_EVENTO
|-
|ALT5J1.100|DGND|DGND| -|<nowiki>-</nowiki>|G|||GPIO4_IO10
|-
| rowspan="4" |J4J1.16102| rowspan="4" |SAI1_TXCCSI1_CLK_N| rowspan="4" |CPU.SAI1_TXCMIPI_CSI1_CLK_N| rowspan="4" |J5A22| rowspan="4" |NVCC_3V3-| rowspan="4" |I/OD| rowspan="4" ||ALT0|SAI1_TX_BCLK
|-
|ALT1J1.104|SAI5_TX_BCLKCSI1_CLK_P|CPU.MIPI_CSI1_CLK_P|B22|-|ALT4D|||CORESIGHT_EVENTI
|-
|ALT5J1.106|CSI1_D0_N|CPU.MIPI_CSI1_D0_N|A23| -|D|||GPIO4_IO11
|-
| rowspan="5" |J4J1.17108| rowspan="5" |SAI1_TXD0CSI1_D0_P| rowspan="5" |CPU.SAI1_TXD0MIPI_CSI1_D0_P| rowspan="5" |F2B23| rowspan="5" |NVCC_3V3-| rowspan="5" |I/OD| rowspan="5" |internally used for BOOT config|ALT0|SAI1_TX_DATA0
|-
|ALT1J1.110|CSI1_D1_N|CPU.MIPI_CSI1_D1_N|C22| -|D|||SAI5_TX_DATA0
|-
|ALT4J1.112|CSI1_D1_P|CPU.MIPI_CSI1_D1_P|D22| -|D|||CORESIGHT_TRACE8
|-
|ALT5J1.114|CSI1_D2_N|CPU.MIPI_CSI1_D2_N|B24| -|D|||GPIO4_IO12
|-
|ALT6J1.116|CSI1_D2_P|CPU.MIPI_CSI1_D2_P|C23| -|D|||SRC_BOOT_CFG8
|-
| rowspan="5" |J4J1.18118| rowspan="5" |SAI1_TXD1CSI1_D3_N| rowspan="5" |CPU.SAI1_TXD1MIPI_CSI1_D3_N| rowspan="5" |E2C21| rowspan="5" |NVCC_3V3-| rowspan="5" |I/OD| rowspan="5" |internally used for BOOT config|ALT0|SAI1_TX_DATA1
|-
|ALT1J1.120|SAI5_TX_DATA1CSI1_D3_P|CPU.MIPI_CSI1_D3_P|D21|-|ALT4D|||CORESIGHT_TRACE9
|-
|ALT5J1.122|DGND|DGND| -|<nowiki>-</nowiki>|G|||GPIO4_IO13
|-
|ALT6J1.124(NAND on board)|NAND_DQS|CPU.NAND_DQS|M20|NVCC_3V3|I/O|Internally used for NAND, do not connect||SRC_BOOT_CFG9
|-
| rowspan="53" |J4J1.19124(eMMC on board)| rowspan="53" |SAI1_TXD2NAND_DQS| rowspan="53" |CPU.SAI1_TXD2NAND_DQS| rowspan="53" |B2M20| rowspan="53" |NVCC_3V3| rowspan="53" |I/O| rowspan="53" |internally used for BOOT config
|ALT0
|SAI1_TX_DATA2RAWNAND_DQS
|-
|ALT1
|SAI5_TX_DATA2|-|ALT4|CORESIGHT_TRACE10QSPI_A_DQS
|-
|ALT5
|GPIO4_IO14GPIO3_IO14
|-
|ALT6J1.126(NAND on board)|NAND_ALE|CPU.NAND_ALE|G19|NVCC_3V3|I/O|Internally used for NAND, do not connect||SRC_BOOT_CFG10
|-
| rowspan="53" |J4J1.20126(eMMC on board)| rowspan="53" |SAI1_TXD3NAND_ALE| rowspan="53" |CPU.SAI1_TXD3NAND_ALE| rowspan="53" |D1G19| rowspan="53" |NVCC_3V3| rowspan="53" |I/O| rowspan="53" |internally used for BOOT config
|ALT0
|SAI1_TX_DATA3RAWNAND_ALE
|-
|ALT1
|SAI5_TX_DATA3QSPI_A_SCLK|-|ALT5|GPIO3_IO00
|-
|ALT4rowspan="2" |J1.128(NAND on board)| rowspan="2" |SD1_CLK| rowspan="2" |CPU.SD1_CLK| rowspan="2" |L25| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" ||ALT0|CORESIGHT_TRACE11USDHC1_CLK
|-
|ALT5
|GPIO4_IO15GPIO2_IO00
|-
|ALT6|SRC_BOOT_CFG11|-| rowspan="63" |J4J1.21128(eMMC on board)| rowspan="63" |SAI1_TXD4NAND_CE0_B| rowspan="63" |CPU.SAI1_TXD4NAND_CE0_B| rowspan="63" |D2H19| rowspan="63" |NVCC_3V3| rowspan="63" |I/O| rowspan="63" |internally used for BOOT config
|ALT0
|SAI1_TX_DATA4RAWNAND_CE0_B
|-
|ALT1
|SAI6_RX_BCLKQSPI_A_SS0_B
|-
|ALT2ALT5|SAI6_TX_BCLKGPIO3_IO01
|-
|ALT4rowspan="2" |J1.130(NAND on board)| rowspan="2" |SD1_CMD| rowspan="2" |CPU.SD1_CMD| rowspan="2" |L24| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" ||ALT0|CORESIGHT_TRACE12USDHC1_CMD
|-
|ALT5
|GPIO4_IO16GPIO2_IO01
|-
|ALT6|SRC_BOOT_CFG12|-| rowspan="63" |J4J1.22130(eMMC on board)| rowspan="63" |SAI1_TXD5NAND_CE1_B| rowspan="63" |CPU.SAI1_TXD5NAND_CE1_B| rowspan="63" |C2G21| rowspan="63" |NVCC_3V3| rowspan="63" |I/O| rowspan="63" |internally used for BOOT config
|ALT0
|SAI1_TX_DATA5RAWNAND_CE1_B
|-
|ALT1
|SAI6_RX_DATA0|-|ALT2|SAI6_TX_DATA0|-|ALT4|CORESIGHT_TRACE13QSPI_A_SS1_B
|-
|ALT5
|GPIO4_IO17GPIO3_IO02
|-
|ALT6|SRC_BOOT_CFG13|-| rowspan="62" |J4J1.23132(NAND on board)| rowspan="62" |SAI1_TXD6SD1_RST_B| rowspan="62" |CPU.SAI1_TXD6SD1_RST_B| rowspan="62" |B3R24| rowspan="62" |NVCC_3V3(NVCC_1V8 on request)| rowspan="62" |I/O| rowspan="62" |internally used for BOOT config
|ALT0
|SAI1_TX_DATA6USDHC1_RESET_B
|-
|ALT1ALT5|SAI6_RX_SYNCGPIO2_IO10
|-
|ALT2rowspan="3" |J1.132(eMMC on board)| rowspan="3" |NAND_CE2_B| rowspan="3" |CPU.NAND_CE2_B| rowspan="3" |F21| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|SAI6_TX_SYNCRAWNAND_CE2_B
|-
|ALT4ALT1|CORESIGHT_TRACE14QSPI_B_SS0_B
|-
|ALT5
|GPIO4_IO18GPIO3_IO03|-| rowspan="2" |J1.134(NAND on board)| rowspan="2" |SD1_STROBE| rowspan="2" |CPU.SD1_STROBE| rowspan="2" |T24| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_STROBE
|-
|ALT6ALT5|SRC_BOOT_CFG14GPIO2_IO11
|-
| rowspan="53" |J4J1.24134(eMMC on board)| rowspan="53" |SAI1_TXD7NAND_CE3_B| rowspan="53" |CPU.SAI1_TXD7NAND_CE3_B| rowspan="53" |C1H20| rowspan="53" |NVCC_3V3| rowspan="53" |I/O| rowspan="53" |internally used for BOOT config
|ALT0
|SAI1_TX_DATA7RAWNAND_CE3_B
|-
|ALT1
|SAI6_MCLK|-|ALT4|CORESIGHT_TRACE15QSPI_B_SS1_B
|-
|ALT5
|GPIO4_IO19GPIO3_IO034
|-
|ALT6J1.136|SRC_BOOT_CFG15(NAND on board)|-NAND_CLE|J4CPU.25|DGNDNAND_CLE|DGNDH21| -NVCC_3V3|<nowiki>-<I/nowiki>O|GInternally used for NAND, do not connect
|
|
|
|}
===Pinout Table J5 pins declaration ===
{| class="wikitable"
! latexfontsize="scriptsize" | Pin
! latexfontsize="scriptsize" | Pin Name
! latexfontsize="scriptsize" | Internal Connections
! latexfontsize="scriptsize" | Ball/pin #
! latexfontsize="scriptsize" |<nowiki>Voltage|domain</nowiki>
! latexfontsize="scriptsize" | Type
! latexfontsize="scriptsize" | Notes
! colspan="2" |Alternative Functions
|-
|J5rowspan="3" |J1.1136(eMMC on board)|DGNDrowspan="3" |NAND_CLE|DGNDrowspan="3" |CPU.NAND_CLE| -rowspan="3" |H21| rowspan="3" |NVCC_3V3|<nowiki>-<rowspan="3" |I/nowiki>O|Growspan="3" ||ALT0|RAWNAND_CLE|-|ALT1|QSPI_B_SCLK
|-
|J5.2|PCIE2_RXN|CPU.PCIE2_RXN_N|D24| -|D||ALT5|GPIO3_IO05
|-
|J5rowspan="2" |J1.3138(NAND on board)|PCIE2_RXProwspan="2" |SD1_DATA0| rowspan="2" |CPU.PCIE2_RXN_PSD1_DATA0|D25rowspan="2" |M25| -rowspan="2" |NVCC_3V3(NVCC_1V8 on request)|Drowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_DATA0
|-
|J5.4|DGND|DGND| -|<nowiki>-</nowiki>|G||ALT5|GPIO2_IO02
|-
|J5rowspan="3" |J1.5138(eMMC on board)|PCIE2_TXNrowspan="3" |NAND_DATA00| rowspan="3" |CPU.PCIE2_TXN_NNAND_DATA00|E24rowspan="3" |G20| -rowspan="3" |NVCC_3V3|Drowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_DATA00
|-
|J5.6|PCIE2_TXP|CPU.PCIE2_TXN_P|E25| -|D||ALT1|QSPI_A_DATA0
|-
|J5.7|DGND|DGND| -|<nowiki>-</nowiki>|G||ALT5|GPIO3_IO06
|-
|J5rowspan="2" |J1.8140(NAND on board)|PCIE2_REF_CLKNrowspan="2" |SD1_DATA1| rowspan="2" |CPU.PCIE2_REF_PAD_CLK_NSD1_DATA1|F24rowspan="2" |M24| -rowspan="2" |NVCC_3V3(NVCC_1V8 on request)|Drowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_DATA1
|-
|J5.9|PCIE2_REF_CLKP|CPU.PCIE2_REF_PAD_CLK_P|F25| -|D||ALT5|GPIO2_IO0
|-
|J5rowspan="3" |J1.10140(eMMC on board)| rowspan="3" |DGNDNAND_DATA01|DGNDrowspan="3" |CPU.NAND_DATA01| -rowspan="3" |J20|<nowiki>-<rowspan="3" |NVCC_3V3| rowspan="3" |I/nowiki>O|Growspan="3" ||ALT0|RAWNAND_DATA01
|-
|J5.11|CSI_P2_CKN|CPU.MIPI_CSI2_CLK_N|A19| -|D||ALT1|QSPI_A_DATA1
|-
|J5.12|CSI_P2_CKP|CPU.MIPI_CSI2_CLK_P|B19| -|D||ALT5|GPIO3_IO07
|-
|J5rowspan="2" |J1.13142(NAND on board)| rowspan="2" |SD1_DATA2|DGNDrowspan="2" |CPU.SD1_DATA2|DGNDrowspan="2" |N25| -rowspan="2" |NVCC_3V3(NVCC_1V8 on request)|<nowiki>-<rowspan="2" |I/nowiki>O|Growspan="2" ||ALT0|USDHC1_DATA2
|-
|J5.14|CSI_P2_DN0|CPU.MIPI_CSI2_D0_N|C20| -|D||ALT5|GPIO2_IO04
|-
|J5rowspan="3" |J1.15142(eMMC on board)|CSI_P2_DP0rowspan="3" |NAND_DATA02| rowspan="3" |CPU.MIPI_CSI2_D0_PNAND_DATA02| rowspan="3" |H22| rowspan="3" |NVCC_3V3| rowspan="3" |I/O|D10rowspan="3" || -ALT0|DRAWNAND_DATA02|-|ALT1|QSPI_A_DATA2
|-
|J5.16|CSI_P2_DN1|CPU.MIPI_CSI2_D1_N|A20| -|D||ALT5|GPIO3_IO08
|-
|J5rowspan="2" |J1.17144(NAND on board)|CSI_P2_DP1rowspan="2" |SD1_DATA3| rowspan="2" |CPU.MIPI_CSI2_D1_PSD1_DATA3| rowspan="2" |P25| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O|B20rowspan="2" ||ALT0|USDHC1_DATA3| -|DALT5|GPIO2_IO05|-|rowspan="3" |J1.144(eMMC on board)| rowspan="3" |NAND_DATA03| rowspan="3" |CPU.NAND_DATA03| rowspan="3" |J21| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_DATA03|-|ALT1|QSPI_A_DATA3|-|ALT5|GPIO3_IO09
|-
|J5J1.18146
|DGND
|DGND
|
|-
|J5rowspan="2" |J1.19148(NAND on board)|CSI_P2_DN2rowspan="2" |SD1_DATA4| rowspan="2" |CPU.MIPI_CSI2_D2_NSD1_DATA4|A21rowspan="2" |N24| -rowspan="2" |NVCC_3V3(NVCC_1V8 on request)|Drowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_DATA4
|-
|J5.20|CSI_P2_DP2|CPU.MIPI_CSI2_D2_P|B21| -|D||ALT5|GPIO2_IO06
|-
|J5rowspan="3" |J1.21148(eMMC on board)|CSI_P2_DN3rowspan="3" |NAND_DATA04| rowspan="3" |CPU.MIPI_CSI2_D3_NNAND_DATA04| rowspan="3" |L20| rowspan="3" |NVCC_3V3| rowspan="3" |I/O|C19rowspan="3" || -ALT0|DRAWNAND_DATA04|-|ALT1|QSPI_B_DATA0
|-
|J5.22|CSI_P2_DP3|CPU.MIPI_CSI2_D3_P|D19| -|D||ALT5|GPIO3_IO10
|-
|J5.23|DGND|DGND| -|<nowiki>-</nowiki>|G||||-| rowspan="42" |J5J1.24150(NAND on board)| rowspan="42" |I2C4_SCLSD1_DATA5| rowspan="42" |CPU.I2C4_SCLSD1_DATA5| rowspan="42" |F8P24| rowspan="42" |NVCC_3V3(NVCC_1V8 on request)| rowspan="42" |I/O| rowspan="42" |
|ALT0
|I2C4_SCL|-|ALT1|PWM2_OUT|-|ALT2|PCIE1_CLKREQ_BUSDHC1_DATA5
|-
|ALT5
|GPIO5_IO20GPIO2_IO07
|-
| rowspan="43" |J5J1.25150(eMMC on board)| rowspan="43" |I2C4_SDANAND_DATA05| rowspan="43" |CPU.I2C4_SDANAND_DATA05| rowspan="43" |F9J22| rowspan="43" |NVCC_3V3| rowspan="43" |I/O| rowspan="43" |
|ALT0
|I2C4_SDARAWNAND_DATA05
|-
|ALT1
|PWM1_OUT|-|ALT2|PCIE2_CLKREQ_BQSPI_B_DATA1
|-
|ALT5
|GPIO5_IO21|} ===Pinout Table JD5 pins declaration ==={| class="wikitable" ! latexfontsize="scriptsize" | Pin ! latexfontsize="scriptsize" | Pin Name! latexfontsize="scriptsize" | Internal Connections ! latexfontsize="scriptsize" | Ball/pin # ! latexfontsize="scriptsize" |<nowiki> Voltage|domain</nowiki>! latexfontsize="scriptsize" | Type ! latexfontsize="scriptsize" | Notes! colspan="2" latexfontsize="scriptsize" | Alternative FunctionsGPIO3_IO11
|-
|JD5rowspan="2" |J1.1152(NAND on board)| rowspan="2" |SD1_DATA6|DGNDrowspan="2" |CPU.SD1_DATA6|DGNDrowspan="2" |R25| -rowspan="2" |NVCC_3V3(NVCC_1V8 on request)|<nowiki>-<rowspan="2" |I/nowiki>O|Growspan="2" ||ALT0|USDHC1_DATA6
|-
|JD5.2|EEPROM_WP|Internal EEPROM Write Protect| -|NVCC_3V3|I||ALT5|GPIO2_IO08
|-
|JD5.rowspan="3" |NCJ1.152|Not Connected(eMMC on board)| -rowspan="3" | -NAND_DATA06|Zrowspan="3" ||||-|JD5CPU.4NAND_DATA06|JTAG_TCKrowspan="3" |CPU.JTAG_TCKL19|T5rowspan="3" |NVCC_3V3| rowspan="3" |I/O|internal pull-up 10k to NVCC_3V3rowspan="3" ||ALT0|RAWNAND_DATA06
|-
|JD5.5|JTAG_TMS|CPU.JTAG_TMS|V5|NVCC_3V3|I||ALT1|QSPI_B_DATA2
|-
|JD5.6|JTAG_TDO|CPU.JTAG_TDO|U5|NVCC_3V3|O||ALT5|GPIO3_IO12
|-
|JD5rowspan="2" |J1.7154(NAND on board)|JTAG_TDIrowspan="2" |SD1_DATA7| rowspan="2" |CPU.JTAG_TDISD1_DATA7|W5rowspan="2" |T25| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_DATA7|-|JD5ALT5|GPIO2_IO09|-| rowspan="3" |J1.8154(eMMC on board)| rowspan="3" |NAND_DATA07| rowspan="3" |CPU.NAND_DATA07| rowspan="3" |M19| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_DATA07|-|ALT1|QSPI_B_DATA3|-|ALT5|GPIO3_IO13|-|J1.156(NAND on board)|JTAG_nTRSTNAND_RE_B|CPU.JTAG_TRST_BNAND_RE_B|U6K19|NVCC_3V3|I/O|Internally used for NAND, do not connect
|
|
|-
|JD5rowspan="3" |J1.9156(eMMC on board)|CPU_PORnrowspan="3" |NAND_RE_B| rowspan="3" |CPU.POR_BNAND_RE_BPMIC| rowspan="3" |K19| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_RE_B|-|ALT1|QSPI_B_DQS|-|ALT5|GPIO3_IO15|-|J1.RESETMCU158(NAND on board)|NAND_READY_B|W20CPU.NAND_READY_B3|K20|NVCC_SNVSNVCC_3V3
|I/O
|internal pull-up 100k to NVCC_SNVSInternally used for NAND, do not connect
|
|
|-
|JD5rowspan="2" |J1.10158(eMMC on board)| rowspan="2" |NAND_READY_B| rowspan="2" |CPU.NAND_READY_B| rowspan="2" |K20| rowspan="2" |NVCC_3V3|NVCC_3V3rowspan="2" |I/O| rowspan="2" ||ALT0|RAWNAND_READY_B| -|<nowiki>ALT5|GPIO3_IO16|-<|J1.160(NAND on board)|NAND_WE_B|CPU.NAND_WE_B|K22|NVCC_3V3|I/nowiki>O|SInternally used for NAND, do not connect
|
|
|-
| rowspan="2" |J1.160
(eMMC on board)
| rowspan="2" |NAND_WE_B
| rowspan="2" |CPU.NAND_WE_B
| rowspan="2" |K22
| rowspan="2" |NVCC_3V3
| rowspan="2" |I/O
| rowspan="2" |
|ALT0
|RAWNAND_WE_B
|-
|ALT5
|GPIO3_IO17
|-
|J1.162
(NAND on board)
|NAND_WP_B
|CPU.NAND_WP_B
|K21
|NVCC_3V3
|I/O
|Internally used for NAND, do not connect
|
|
|-
| rowspan="2" |J1.162
(eMMC on board)
| rowspan="2" |NAND_WP_B
| rowspan="2" |CPU.NAND_WP_B
| rowspan="2" |K21
| rowspan="2" |NVCC_3V3
| rowspan="2" |I/O
| rowspan="2" |
|ALT0
|RAWNAND_WP_B
|-
|ALT5
|GPIO3_IO18
|-
|J1.164
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
|J1.166
|CLK1_N
|CPU.CLK1_N
|T23
|
|D
|
|
|
|-
|J1.168
|CLK1_P
|CPU.CLK1_P
|R23
|
|D
|
|
|
|-
|J1.170
|USB2_RXN
|CPU.USB2_RX_N
|B8
|
|D
|
|
|
|-
|J1.172
|USB2_RXP
|CPU.USB2_RX_P
|A8
|
|D
|
|
|
|-
|J1.174
|USB2_TXN
|CPU.USB2_TX_N
|B9
|
|D
|
|
|
|-
|J1.176
|USB2_TXP
|CPU.USB2_TX_P
|A9
|
|D
|
|
|
|-
|J1.178
|USB1_RXN
|CPU.USB1_RX_N
|B12
|
|D
|
|
|
|-
|J1.180
|USB1_RXP
|CPU.USB1_RX_P
|A12
|
|D
|
|
|
|-
|J1.182
|USB1_TXN
|CPU.USB1_TX_N
|B13
|
|D
|
|
|
|-
|J1.184
|USB1_TXP
|CPU.USB1_TX_P
|A13
|
|D
|
|
|
|-
|J1.186
|USB1_VBUS
|CPU.USB1_VBUS
|D14
| -
|S
|Absolute maximum ratings 5.25V
|
|
|-
|J1.188
|USB2_VBUS
|CPU.USB2_VBUS
|D9
| -
|S
|Absolute maximum ratings 5.25V
|
|
|-
|J1.190
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
|J1.192
|USB1_ID
|CPU.USB1_ID
|C14
|VDD_PHY_3V3
|I
|
|
|
|-
|J1.194
|USB2_ID
|CPU.USB2_ID
|C9
|VDD_PHY_3V3
|I
|
|
|
|-
|J1.196
|USB1_DN
|CPU.USB1_DN
|B14
| -
|D
|
|
|
|-
|J1.198
|USB1_DP
|CPU.USB1_DP
|A14
| -
|D
|
|
|
|-
|J1.200
|USB2_DP
|CPU.USB2_DP
|A10
| -
|D
|
|
|
|-
|J1.202
|USB2_DN
|CPU.USB2_DN
|B10
| -
|D
|
|
|
|-
|J1.204
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
|}
 
==ONE PIECE J4 pins declaration ==
{| class="wikitable"
! latexfontsize="scriptsize" | Pin
! latexfontsize="scriptsize" | Pin Name
! latexfontsize="scriptsize" | Internal Connections
! latexfontsize="scriptsize" | Ball/pin #
! latexfontsize="scriptsize" | Voltage domain
! latexfontsize="scriptsize" | Type
! latexfontsize="scriptsize" | Notes
! colspan="2" |Alternative Functions
|-
|J4.1
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
| rowspan="7" |J4.2
| rowspan="7" |SAI1_RXD7
| rowspan="7" |CPU.SAI1_RXD7
| rowspan="7" |G1
| rowspan="7" |NVCC_3V3
| rowspan="7" |I/O
| rowspan="7" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_RX_DATA7
|-
|ALT1
|SAI6_MCLK
|-
|ALT2
|SAI1_TX_SYNC
|-
|ALT3
|SAI1_TX_DATA4
|-
|ALT4
|CORESIGHT_TRACE7
|-
|ALT5
|GPIO4_IO09
|-
|ALT6
|SRC_BOOT_CFG7
|-
| rowspan="6" |J4.3
| rowspan="6" |SAI1_RXD6
| rowspan="6" |CPU.SAI1_RXD6
| rowspan="6" |G2
| rowspan="6" |NVCC_3V3
| rowspan="6" |I/O
| rowspan="6" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_RX_DATA6
|-
|ALT1
|SAI6_TX_SYNC
|-
|ALT2
|SAI6_RX_SYNC
|-
|ALT4
|CORESIGHT_TRACE6
|-
|ALT5
|GPIO4_IO08
|-
|ALT6
|SRC_BOOT_CFG6
|-
| rowspan="7" |J4.4
| rowspan="7" |SAI1_RXD5
| rowspan="7" |CPU.SAI1_RXD5
| rowspan="7" |F1
| rowspan="7" |NVCC_3V3
| rowspan="7" |I/O
| rowspan="7" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_RX_DATA5
|-
|ALT1
|SAI6_TX_DATA0
|-
|ALT2
|SAI6_RX_DATA0
|-
|ALT3
|SAI1_RX_SYNC
|-
|ALT4
|CORESIGHT_TRACE5
|-
|ALT5
|GPIO4_IO07
|-
|ALT6
|SRC_BOOT_CFG5
|-
| rowspan="6" |J4.5
| rowspan="6" |SAI1_RXD4
| rowspan="6" |CPU.SAI1_RXD4
| rowspan="6" |J1
| rowspan="6" |NVCC_3V3
| rowspan="6" |I/O
| rowspan="6" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_RX_DATA4
|-
|ALT1
|SAI6_TX_BCLK
|-
|ALT2
|SAI6_RX_BCLK
|-
|ALT4
|CORESIGHT_TRACE4
|-
|ALT5
|GPIO4_IO06
|-
|ALT6
|SRC_BOOT_CFG4
|-
| rowspan="5" |J4.6
| rowspan="5" |SAI1_RXD3
| rowspan="5" |CPU.SAI1_RXD3
| rowspan="5" |J2
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_RX_DATA3
|-
|ALT1
|SAI5_RX_DATA3
|-
|ALT4
|CORESIGHT_TRACE3
|-
|ALT5
|GPIO4_IO05
|-
|ALT6
|SRC_BOOT_CFG3
|-
| rowspan="5" |J4.7
| rowspan="5" |SAI1_RXD2
| rowspan="5" |CPU.SAI1_RXD2
| rowspan="5" |H2
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_RX_DATA2
|-
|ALT1
|SAI5_RX_DATA2
|-
|ALT4
|CORESIGHT_TRACE2
|-
|ALT5
|GPIO4_IO04
|-
|ALT6
|SRC_BOOT_CFG2
|-
| rowspan="5" |J4.8
| rowspan="5" |SAI1_RXD1
| rowspan="5" |CPU.SAI1_RXD1
| rowspan="5" |L2
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_RX_DATA1
|-
|ALT1
|SAI5_RX_DATA1
|-
|ALT4
|CORESIGHT_TRACE1
|-
|ALT5
|GPIO4_IO03
|-
|ALT6
|SRC_BOOT_CFG1
|-
| rowspan="5" |J4.9
| rowspan="5" |SAI1_RXD0
| rowspan="5" |CPU.SAI1_RXD0
| rowspan="5" |K2
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_RX_DATA0
|-
|ALT1
|SAI5_RX_DATA0
|-
|ALT4
|CORESIGHT_TRACE0
|-
|ALT5
|GPIO4_IO02
|-
|ALT6
|SRC_BOOT_CFG0
|-
| rowspan="4" |J4.10
| rowspan="4" |SAI1_RXC
| rowspan="4" |CPU.SAI1_RXC
| rowspan="4" |K1
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |
|ALT0
|SAI1_RX_BCLK
|-
|ALT1
|SAI5_RX_BCLK
|-
|ALT4
|CORESIGHT_TRACE_CTL
|-
|ALT5
|GPIO4_IO01
|-
| rowspan="4" |J4.11
| rowspan="4" |SAI1_RXFS
| rowspan="4" |CPU.SAI1_RXFS
| rowspan="4" |L1
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |
|ALT0
|SAI1_RX_SYNC
|-
|ALT1
|SAI5_RX_SYNC
|-
|ALT4
|CORESIGHT_TRACE_CLK
|-
|ALT5
|GPIO4_IO00
|-
|J4.12
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
| rowspan="4" |J4.13
| rowspan="4" |SAI1_MCLK
| rowspan="4" |CPU.SAI1_MCLK
| rowspan="4" |
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |
|ALT0
|SAI1_MCLK
|-
|ALT1
|SAI5_MCLK
|-
|ALT2
|SAI1_TX_BCLK
|-
|ALT5
|GPIO4_IO20
|-
|J4.14
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
| rowspan="4" |J4.15
| rowspan="4" |SAI1_TXFS
| rowspan="4" |CPU.SAI1_TXFS
| rowspan="4" |H4
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |
|ALT0
|SAI1_TX_SYNC
|-
|ALT1
|SAI5_TX_SYNC
|-
|ALT4
|CORESIGHT_EVENTO
|-
|ALT5
|GPIO4_IO10
|-
| rowspan="4" |J4.16
| rowspan="4" |SAI1_TXC
| rowspan="4" |CPU.SAI1_TXC
| rowspan="4" |J5
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |
|ALT0
|SAI1_TX_BCLK
|-
|ALT1
|SAI5_TX_BCLK
|-
|ALT4
|CORESIGHT_EVENTI
|-
|ALT5
|GPIO4_IO11
|-
| rowspan="5" |J4.17
| rowspan="5" |SAI1_TXD0
| rowspan="5" |CPU.SAI1_TXD0
| rowspan="5" |F2
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_TX_DATA0
|-
|ALT1
|SAI5_TX_DATA0
|-
|ALT4
|CORESIGHT_TRACE8
|-
|ALT5
|GPIO4_IO12
|-
|ALT6
|SRC_BOOT_CFG8
|-
| rowspan="5" |J4.18
| rowspan="5" |SAI1_TXD1
| rowspan="5" |CPU.SAI1_TXD1
| rowspan="5" |E2
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_TX_DATA1
|-
|ALT1
|SAI5_TX_DATA1
|-
|ALT4
|CORESIGHT_TRACE9
|-
|ALT5
|GPIO4_IO13
|-
|ALT6
|SRC_BOOT_CFG9
|-
| rowspan="5" |J4.19
| rowspan="5" |SAI1_TXD2
| rowspan="5" |CPU.SAI1_TXD2
| rowspan="5" |B2
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_TX_DATA2
|-
|ALT1
|SAI5_TX_DATA2
|-
|ALT4
|CORESIGHT_TRACE10
|-
|ALT5
|GPIO4_IO14
|-
|ALT6
|SRC_BOOT_CFG10
|-
| rowspan="5" |J4.20
| rowspan="5" |SAI1_TXD3
| rowspan="5" |CPU.SAI1_TXD3
| rowspan="5" |D1
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_TX_DATA3
|-
|ALT1
|SAI5_TX_DATA3
|-
|ALT4
|CORESIGHT_TRACE11
|-
|ALT5
|GPIO4_IO15
|-
|ALT6
|SRC_BOOT_CFG11
|-
| rowspan="6" |J4.21
| rowspan="6" |SAI1_TXD4
| rowspan="6" |CPU.SAI1_TXD4
| rowspan="6" |D2
| rowspan="6" |NVCC_3V3
| rowspan="6" |I/O
| rowspan="6" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_TX_DATA4
|-
|ALT1
|SAI6_RX_BCLK
|-
|ALT2
|SAI6_TX_BCLK
|-
|ALT4
|CORESIGHT_TRACE12
|-
|ALT5
|GPIO4_IO16
|-
|ALT6
|SRC_BOOT_CFG12
|-
| rowspan="6" |J4.22
| rowspan="6" |SAI1_TXD5
| rowspan="6" |CPU.SAI1_TXD5
| rowspan="6" |C2
| rowspan="6" |NVCC_3V3
| rowspan="6" |I/O
| rowspan="6" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_TX_DATA5
|-
|ALT1
|SAI6_RX_DATA0
|-
|ALT2
|SAI6_TX_DATA0
|-
|ALT4
|CORESIGHT_TRACE13
|-
|ALT5
|GPIO4_IO17
|-
|ALT6
|SRC_BOOT_CFG13
|-
| rowspan="6" |J4.23
| rowspan="6" |SAI1_TXD6
| rowspan="6" |CPU.SAI1_TXD6
| rowspan="6" |B3
| rowspan="6" |NVCC_3V3
| rowspan="6" |I/O
| rowspan="6" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_TX_DATA6
|-
|ALT1
|SAI6_RX_SYNC
|-
|ALT2
|SAI6_TX_SYNC
|-
|ALT4
|CORESIGHT_TRACE14
|-
|ALT5
|GPIO4_IO18
|-
|ALT6
|SRC_BOOT_CFG14
|-
| rowspan="5" |J4.24
| rowspan="5" |SAI1_TXD7
| rowspan="5" |CPU.SAI1_TXD7
| rowspan="5" |C1
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_TX_DATA7
|-
|ALT1
|SAI6_MCLK
|-
|ALT4
|CORESIGHT_TRACE15
|-
|ALT5
|GPIO4_IO19
|-
|ALT6
|SRC_BOOT_CFG15
|-
|J4.25
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|}
 
==ONE PIECE J5 pins declaration ==
{| class="wikitable"
! latexfontsize="scriptsize" | Pin
! latexfontsize="scriptsize" | Pin Name
! latexfontsize="scriptsize" | Internal Connections
! latexfontsize="scriptsize" | Ball/pin #
! latexfontsize="scriptsize" | Voltage domain
! latexfontsize="scriptsize" | Type
! latexfontsize="scriptsize" | Notes
! colspan="2" |Alternative Functions
|-
|J5.1
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
|J5.2
|PCIE2_RXN
|CPU.PCIE2_RXN_N
|D24
| -
|D
|
|
|
|-
|J5.3
|PCIE2_RXP
|CPU.PCIE2_RXN_P
|D25
| -
|D
|
|
|
|-
|J5.4
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
|J5.5
|PCIE2_TXN
|CPU.PCIE2_TXN_N
|E24
| -
|D
|
|
|
|-
|J5.6
|PCIE2_TXP
|CPU.PCIE2_TXN_P
|E25
| -
|D
|
|
|
|-
|J5.7
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
|J5.8
|PCIE2_REF_CLKN
|CPU.PCIE2_REF_PAD_CLK_N
|F24
| -
|D
|
|
|
|-
|J5.9
|PCIE2_REF_CLKP
|CPU.PCIE2_REF_PAD_CLK_P
|F25
| -
|D
|
|
|
|-
|J5.10
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
|J5.11
|CSI_P2_CKN
|CPU.MIPI_CSI2_CLK_N
|A19
| -
|D
|
|
|
|-
|J5.12
|CSI_P2_CKP
|CPU.MIPI_CSI2_CLK_P
|B19
| -
|D
|
|
|
|-
|J5.13
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
|J5.14
|CSI_P2_DN0
|CPU.MIPI_CSI2_D0_N
|C20
| -
|D
|
|
|
|-
|J5.15
|CSI_P2_DP0
|CPU.MIPI_CSI2_D0_P
|D10
| -
|D
|
|
|
|-
|J5.16
|CSI_P2_DN1
|CPU.MIPI_CSI2_D1_N
|A20
| -
|D
|
|
|
|-
|J5.17
|CSI_P2_DP1
|CPU.MIPI_CSI2_D1_P
|B20
| -
|D
|
|
|
|-
|J5.18
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
|J5.19
|CSI_P2_DN2
|CPU.MIPI_CSI2_D2_N
|A21
| -
|D
|
|
|
|-
|J5.20
|CSI_P2_DP2
|CPU.MIPI_CSI2_D2_P
|B21
| -
|D
|
|
|
|-
|J5.21
|CSI_P2_DN3
|CPU.MIPI_CSI2_D3_N
|C19
| -
|D
|
|
|
|-
|J5.22
|CSI_P2_DP3
|CPU.MIPI_CSI2_D3_P
|D19
| -
|D
|
|
|
|-
|J5.23
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
| rowspan="4" |J5.24
| rowspan="4" |I2C4_SCL
| rowspan="4" |CPU.I2C4_SCL
| rowspan="4" |F8
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |
|ALT0
|I2C4_SCL
|-
|ALT1
|PWM2_OUT
|-
|ALT2
|PCIE1_CLKREQ_B
|-
|ALT5
|GPIO5_IO20
|-
| rowspan="4" |J5.25
| rowspan="4" |I2C4_SDA
| rowspan="4" |CPU.I2C4_SDA
| rowspan="4" |F9
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |
|ALT0
|I2C4_SDA
|-
|ALT1
|PWM1_OUT
|-
|ALT2
|PCIE2_CLKREQ_B
|-
|ALT5
|GPIO5_IO21
|}
U0007
Bureaucrats, dave_user, Administrators
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