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MITO 8M SOM/MITO 8M Hardware/Pinout Table

14,026 bytes added, 17:49, 28 December 2023
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<section begin="History" />
{| style="border-collapse:collapse; "
! colspan="4" style="width:100%; text-align:left" ; border-bottom:solid 2px #ededed" |History
|-
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Version
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Issue Date
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Notes
|-
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |1.0.0{{oldid| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" 10368|Sep 2020/09/29}}
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |First release
|-
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#ededed; padding:5px; color:#000000" |2021/02/02
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#ededed; padding:5px; color:#000000" |Add pull-up/down information
|-
|}
<section end="History" /><section begin="Body" />==Connectors and Pinout Table=====Introduction=description==
This chapter contains === Connectors description ===In the following table are described all available connectors integrated on MITO 8M SOM:{| class="wikitable"|-!Connector name!Connector Type!Notes!Carrier board counterpart|-|J1|SODIMM edge connector 204 pin|partially compatible with [[AXEL Lite SOM]]|TE Connectivity 2-2013289-1|-|J4|ONE PIECE connector single row 25pins||SAMTEC FSI-125-03-G-S-AD-TR|-|J5|ONE PIECE connector single row 25pins||SAMTEC FSI-125-03-G-S-AD-TR|}The dedicated carrier board must mount the mating connector and connect the desired peripheral interfaces according to MITO 8M pinout specifications. See the images below for reference: [[File:MITO 8M-conn-TOP.png|500px|thumb|MITO 8M TOP view|none]][[File:MITO 8M-conn-BOTTOM.png|500px|thumb|MITO 8M BOTTOM view|none]] Below a detailed description of the MITO 8M modulepinout, grouped in the following tables:* two tables (odd ODD and even EVEN pins) that report the pin mapping of the 204-pin SO-DIMM MITO 8M edge* a dedicated tables for J4 one-piece connector* a dedicated tables for J5 one-piece connector.
=== Pinout Table description ===
Each row in the pinout tables contains the following information:
 {| class="wikitable" style="width:50%;"
|-
|'''Pin'''
|-
|'''Pin Name'''
| Pin (signal) name on the AxelLite MITO 8M connectors
|-
|'''Internal<br>connections'''
| Connections to the Axel Ultra components
* CPU.<x> : pin connected to CPU pad named <x>
* PMIC.<x> : pin connected to the Power Manager IC(NXP PF4210)* LAN.<x> : pin connected to the LAN PHY(MICROCHIP KSZ9031RNX)* BRIDGE.<x> : pin connected to the MIPI-to-LVDS bridge* SV.<x>: pin connected to voltage supervisor(TI SN65DSI84)
|-
|'''Ball/pin #'''
|}
===Pinout Table SODIMM J1 ODD pins declaration ===
===Pinout Table EVEN pins declaration === {| class="wikitable"
! latexfontsize="scriptsize" | Pin
! latexfontsize="scriptsize" | Pin Name
! latexfontsize="scriptsize" | Internal Connections
! latexfontsize="scriptsize" | Ball/pin #
! latexfontsize="scriptsize" |<nowiki>Voltage|domain</nowiki>
! latexfontsize="scriptsize" | Type
! latexfontsize="scriptsize" | Notes
! colspan="2" latexfontsize="scriptsize" | Alternative Functions
|-
|J1.21
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|-
|J1.43|3.3VIN
|INPUT VOLTAGE
| -
|
|-
|J1.65|3.3VIN
|INPUT VOLTAGE
| -
|
|-
|J1.87|3.3VIN
|INPUT VOLTAGE
| -
|
|-
|J1.109|3.3VIN
|INPUT VOLTAGE
| -
|
|-
|J1.1211
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|-
|J1.1413|PMIC_LICELL ETH0_LED1|PMICLAN.LICELLLED1/PME_N1|3017|NVCC_1V8|I/O|Must be level translated if used @ 3V3Internally pulled-up to 1.8V during bootstrap|||-|J1.15|ETH0_LED2|LAN.LED2|15|NVCC_1V8|I/O|Must be level translated if used @ 3V3Internally pulled-up to 1.8V during bootstrap|||-|J1.17|DGND|DGND| -
| -
|SG
|
|
|
|-
|J1.1619|CPU_ONOFFETH0_TXRX0_P|CPULAN.ONOFFTXRXP_A|W212|NVCC_SNVS-|ID|internal pull-up 100k to NVCC_SNVS
|
|
|-
|J1.1821|BOARD_PGOODETH0_TXRX0_M|LAN.TXRXM_A|3
| -
| -|NVCC_3V3|OD
|
|
|
|-
|J1.2023|BOOT_MODE_SELETH0_TXRX1_P|BOOT MODE SELECTIONLAN.TXRXP_B|5
| -
|NVCC_3V3D|I|internal pull-up to NVCC_3V3
|
|
|-
|J1.2225|CPU_PORnETH0_TXRX1_M|CPULAN.POR_BTXRXM_BPMIC|6| -|D||||-|J1.RESETMCU27|W20ETH0_TXRX2_P3|LAN.TXRXP_C|NVCC_SNVS7|I/O-|D|internal pull-up 100k to NVCC_SNVS
|
|
|-
|J1.2429|EXT_RESETETH0_TXRX2_M|MASTER RESETLAN.TXRXM_C|8
| -
|D
|
|
|
|-
|J1.31
|ETH0_TXRX3_P
|LAN.TXRXP_D
|10
| -
|ID|internal pull-up to NVCC_SNVS
|
|
|-
|J1.33|ETH0_TXRX3_M|LAN.TXRXM_D|11| -|D||||-|J1.35|DGND|DGND| -| -|G||||-| rowspan="4" |J1.2637| rowspan="4" |SAI3_RXCGPIO1_IO00| rowspan="4" |CPU.SAI3_RXCGPIO1_IO00| rowspan="4" |F4T6| rowspan="4" |NVCC_3V3| rowspan="4" |I/O
| rowspan="4" |
|ALT0
|SAI3_RX_BCLKGPIO1_IO00
|-
|ALT1
|GPT1_CAPTURE2CCM_ENET_PHY_REF_CLK_ROOT
|-
|ALT2ALT5|SAI5_RX_BCLKANAMIX_REF_CLK_32K
|-
|ALT5ALT6|GPIO4_IO29CCM_EXT_CLK1
|-
| rowspan="4" |J1.2839| rowspan="4" |GPIO1_IO02GPIO1_IO01| rowspan="4" |CPU.GPIO1_IO02GPIO1_IO01| rowspan="4" |R4T7
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |Internally used for SW ETH PHY reset, do not connect
|ALT0
|GPIO1_IO02GPIO1_IO01
|-
|ALT1
|WDOG1_WDOG_BPWM1_OUT
|-
|ALT5
|WDOG1_WDOG_ANYANAMIX_REF_CLK_25M
|-
|ALT7ALT6|SJC_DE_BCCM_EXT_CLK2
|-
|J1.30|DGND|DGND| -|<nowiki>-</nowiki>|G||||-| rowspan="43" |J1.3241| rowspan="43" |SAI3_RXDSPDIF_EXT_CLK| rowspan="43" |CPU.SAI3_RXDSPDIF_EXT_CLK| rowspan="43" |F3E6| rowspan="43" |NVCC_3V3| rowspan="43" |I/O| rowspan="43" |
|ALT0
|SAI3_RX_DATA0SPDIF1_EXT_CLK
|-
|ALT1
|GPT1_COMPARE1|-|ALT2|SAI5_RX_DATA0PWM1_OUT
|-
|ALT5
|GPIO4_IO30GPIO5_IO05
|-
| rowspan="3" |J1.3443| rowspan="3" |SAI2_MCLKGPIO1_IO13| rowspan="3" |CPU.SAI2_MCLKGPIO1_IO13| rowspan="3" |H5K6
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |Internally used, do not connect
|ALT0
|SAI2_MCLKGPIO1_IO13
|-
|ALT1
|SAI5_MCLKUSB1_OTG_OC
|-
|ALT5
|GPIO4_IO27PWM2_OUT
|-
|J1.45|VDD_PHY_1V8||||||||-| rowspan="43" |J1.3647| rowspan="43" |SAI3_RXFSECSPI2_SCLK| rowspan="43" |CPU.SAI3_RXFSECSPI2_SCLK| rowspan="43" |G4C5| rowspan="43" |NVCC_3V3| rowspan="43" |I/O| rowspan="43" |
|ALT0
|SAI3_RX_SYNCECSPI2_SCLK
|-
|ALT1
|GPT1_CAPTURE1|-|ALT2|SAI5_RX_SYNCUART4_RX
|-
|ALT5
|GPIO4_IO28GPIO5_IO10
|-
| rowspan="43" |J1.3849| rowspan="43" |I2C3_SCLECSPI2_MOSI| rowspan="43" |CPU.I2C3_SCLECSPI2_MOSI| rowspan="43" |G8E5| rowspan="43" |NVCC_3V3| rowspan="43" |I/O| rowspan="43" |
|ALT0
|I2C3_SCLECSPI2_MOSI
|-
|ALT1
|PWM4_OUT|-|ALT2|GPT2_CLKUART4_TX
|-
|ALT5
|GPIO5_IO18GPIO5_IO11
|-
| rowspan="43" |J1.4051| rowspan="43" |SAI3_TXFSGPIO1_IO08| rowspan="43" |CPU.SAI3_TXFSGPIO1_IO08| rowspan="43" |G3N7| rowspan="43" |NVCC_3V3| rowspan="43" |I/O| rowspan="43" |
|ALT0
|SAI3_TX_SYNCGPIO1_IO08
|-
|ALT1
|GPT1_CLK|-|ALT2|SAI5_RX_DATA1ENET1_1588_EVENT0_IN
|-
|ALT5
|GPIO4_IO31USDHC2_RESET_B
|-
| rowspan="3" |J1.4253| rowspan="3" |SPDIF_RXGPIO1_IO09| rowspan="3" |CPU.SPDIF_RXGPIO1_IO09| rowspan="3" |G6M7
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|SPDIF1_INGPIO1_IO09
|-
|ALT1
|PWM2_OUTENET1_1588_EVENT0_OUT
|-
|ALT5
|GPIO5_IO04SDMA2_EXT_EVENT0
|-
| rowspan="3" |J1.4455| rowspan="3" |SPDIF_TXECSPI2_MISO| rowspan="3" |CPU.SPDIF_TXECSPI2_MISO| rowspan="3" |F6B5
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|SPDIF1_OUTECSPI2_MISO
|-
|ALT1
|PWM3_OUTUART4_CTS_B
|-
|ALT5
|GPIO5_IO03GPIO5_IO12
|-
|J1.57|DGND |DGND| -| -|G||||-| rowspan="43" |J1.4659| rowspan="43" |SAI3_MCLKECSPI2_SS0| rowspan="43" |CPU.SAI3_MCLKECSPI2_SS0| rowspan="43" |D3A5| rowspan="43" |NVCC_3V3| rowspan="43" |I/O| rowspan="43" |
|ALT0
|SAI3_MCLKECSPI2_SS0
|-
|ALT1
|PWM4_OUT|-|ALT2|SAI5_MCLKUART4_RTS_B
|-
|ALT5
|GPIO5_IO02GPIO5_IO13
|-
| rowspan="43" |J1.4861| rowspan="43" |I2C3_SDAGPIO1_IO05| rowspan="43" |CPU.I2C3_SDAGPIO1_IO05| rowspan="43" |E9P7| rowspan="43" |NVCC_3V3| rowspan="43" |I/O| rowspan="43" |Internally used for MIPI-to-LVDS interrupt, do not connectPulled-up to NVCC_3V3
|ALT0
|I2C3_SDAGPIO1_IO05
|-
|ALT1
|PWM3_OUTM4_NMI
|-
|ALT2ALT5|GPT3_CLKCCM_PMIC_READY|-| rowspan="3" |J1.63| rowspan="3" |I2C2_SCL| rowspan="3" |CPU.I2C2_SCL| rowspan="3" |G7| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|I2C2_SCL|-|ALT1|ENET1_1588_EVENT1_IN
|-
|ALT5
|GPIO5_IO19GPIO5_IO16
|-
| rowspan="43" |J1.5065| rowspan="43" |SAI3_TXCI2C2_SDA| rowspan="43" |CPU.SAI3_TXCI2C2_SDA| rowspan="43" |C4F7| rowspan="43" |NVCC_3V3| rowspan="43" |I/O| rowspan="43" |
|ALT0
|SAI3_TX_BCLKI2C2_SDA
|-
|ALT1
|GPT1_COMPARE2|-|ALT2|SAI5_RX_DATA2ENET1_1588_EVENT1_OUT
|-
|ALT5
|GPIO5_IO00GPIO5_IO17
|-
| rowspan="4" |J1.5267| rowspan="4" |SAI3_TXDGPIO1_IO06| rowspan="4" |CPU.SAI3_TXDGPIO1_IO06| rowspan="4" |C3N5
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |Internally used for MIPI-to-LVDS enable, do not connect
|ALT0
|SAI3_TX_DATA0GPIO1_IO06
|-
|ALT1
|GPT1_COMPARE3|-|ALT2|SAI5_RX_DATA3ENET1_MDC
|-
|ALT5
|GPIO5_IO01USDHC1_CD_B
|-
|ALT6|CCM_EXT_CLK3|-| rowspan="3" |J1.69| rowspan="3" |SAI2_RXC| rowspan="3" |CPU.SAI2_RXC| rowspan="3" |H3| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|SAI2_RX_BCLK|-|ALT1|SAI5_TX_BCLK|-|ALT5|GPIO4_IO22|-| rowspan="23" |J1.5471| rowspan="23" |GPIO1_IO10SAI2_RXFS| rowspan="23" |CPU.GPIO1_IO10SAI2_RXFS| rowspan="23" |M7J4| rowspan="23" |NVCC_3V3| rowspan="23" |I/O| rowspan="23" |Internally used for ETH PHY interrupt, do not connect
|ALT0
|GPIO1_IO10SAI2_RX_SYNC
|-
|ALT1
|USB1_OTG_IDSAI5_TX_SYNC|-|ALT5|GPIO4_IO21
|-
|J1.5673|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|-
| rowspan="42" |J1.5875| rowspan="42" |SAI5_MCLKSD2_DATA0| rowspan="42" |CPU.SAI5_MCLKSD2_DATA0| rowspan="42" |K4N22| rowspan="42" |NVCC_3V3| rowspan="42" |I/O| rowspan="42" |
|ALT0
|SAI5_MCLKUSDHC2_DATA0
|-
|ALT1ALT5|SAI1_TX_BCLKGPIO2_IO15
|-
|ALT2rowspan="2" |J1.77| rowspan="2" |SD2_DATA1| rowspan="2" |CPU.SD2_DATA1| rowspan="2" |N21| rowspan="2" |NVCC_3V3| rowspan="2" |I/O| rowspan="2" ||ALT0|SAI4_MCLKUSDHC2_DATA1
|-
|ALT5
|GPIO3_IO25GPIO2_IO16
|-
| rowspan="42" |J1.6079| rowspan="42" |GPIO1_IO15SD2_DATA2| rowspan="42" |CPU.GPIO1_IO15SD2_DATA2| rowspan="42" |J6P22| rowspan="42" |NVCC_3V3| rowspan="42" |I/O| rowspan="42" |
|ALT0
|GPIO1_IO15USDHC2_DATA2|-|ALT5|GPIO2_IO17
|-
|ALT1rowspan="2" |J1.81| rowspan="2" |SD2_DATA3| rowspan="2" |CPU.SD2_DATA03| rowspan="2" |P21| rowspan="2" |NVCC_3V3| rowspan="2" |I/O| rowspan="2" ||ALT0|USB2_OTG_OCUSDHC2_DATA3
|-
|ALT5
|PWM4_OUTGPIO2_IO18
|-
|ALT6rowspan="2" |J1.83| rowspan="2" |SD2_CMD| rowspan="2" |CPU.SD2_CMD| rowspan="2" |M22| rowspan="2" |NVCC_3V3| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC2_CMD|-|ALT5|GPIO2_IO14|-| rowspan="2" |J1.85| rowspan="2" |SD2_CLK| rowspan="2" |CPU.SD2_CLK| rowspan="2" |L22| rowspan="2" |NVCC_3V3| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC2_CLK|-|ALT5|GPIO2_IO13|-|J1.87|DGND |DGND| -| -|G|||CCM_CLKO2
|-
| rowspan="3" |J1.6289| rowspan="3" |SAI5_RXFSUART3_TXD| rowspan="3" |CPU.SAI5_RXFSUART3_TXD| rowspan="3" |N4B7
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|SAI5_RX_SYNCUART3_TX
|-
|ALT1
|SAI1_TX_DATA0UART1_RTS_B
|-
|ALT5
|GPIO3_IO19GPIO5_IO27
|-
| rowspan="3" |J1.6491| rowspan="3" |SAI5_RXCUART3_RXD| rowspan="3" |CPU.SAI5_RXCUART3_RXD| rowspan="3" |L5A6
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|SAI5_RX_BCLKUART3_RX
|-
|ALT1
|SAI1_TX_DATA1UART1_CTS_B
|-
|ALT5
|GPIO3_IO20GPIO5_IO26
|-
| rowspan="34" |J1.6693| rowspan="34" |SAI2_TXCUART4_TXD| rowspan="34" |CPU.SAI2_TXCUART4_TXD| rowspan="34" |J5D7| rowspan="34" |NVCC_3V3| rowspan="34" |I/O| rowspan="34" |
|ALT0
|SAI2_TX_BCLKUART4_TX
|-
|ALT1
|SAI5_TX_DATA2UART2_RTS_B|-|ALT2|PCIE2_CLKREQ_B
|-
|ALT5
|GPIO4_IO25GPIO5_IO29
|-
| rowspan="34" |J1.6895| rowspan="34" |SAI2_TXD0UART4_RXD| rowspan="34" |CPU.SAI2_TXD0UART4_RXD| rowspan="34" |G5C6| rowspan="34" |NVCC_3V3| rowspan="34" |I/O| rowspan="34" |
|ALT0
|SAI2_TX_DATA0UART4_RX
|-
|ALT1
|SAI5_TX_DATA3UART2_CTS_B|-|ALT2|PCIE1_CLKREQ_B
|-
|ALT5
|GPIO4_IO26GPIO5_IO28
|-
| rowspan="32" |J1.7097| rowspan="32" |SAI2_TXFSSD2_WP| rowspan="32" |CPU.SAI2_TXFSSD2_WP| rowspan="32" |H4M21| rowspan="32" |NVCC_3V3| rowspan="32" |I/O| rowspan="32" |
|ALT0
|SAI2_TX_SYNC|-|ALT1|SAI5_TX_DATA1USDHC2_WP
|-
|ALT5
|GPIO4_IO24GPIO2_IO20
|-
| rowspan="32" |J1.7299| rowspan="32" |SAI2_RXD0SD2_RST_B| rowspan="32" |CPU.SAI2_RXD0SD2_RESET_B| rowspan="32" |H6R22| rowspan="32" |NVCC_3V3| rowspan="32" |I/O| rowspan="32" |
|ALT0
|SAI2_RX_DATA0USDHC2_RESET_B
|-
|ALT1ALT5|SAI5_TX_DATA0GPIO2_IO19
|-
|ALT5J1.101|HDMI_DDC_SCL|CPU.HDMI_DDC_SCL|R3|VDD_PHY_1V8|I/O|||GPIO4_IO23
|-
| rowspan="3" |J1.74103| rowspan="3" |SAI5_RXD0HDMI_DDC_SDA| rowspan="3" |CPU.SAI5_RXD0HDMI_DDC_SDA| rowspan="3" |M5P3| rowspan="3" |NVCC_3V3VDD_PHY_1V8| rowspan="3" |I/O| rowspan="3" ||ALT0|SAI5_RX_DATA0
|-
|ALT1J1.105|HDMI_AUX_N|CPU.HDMI_AUX_N|V2| -|D|connected with capacitor in series||SAI1_TX_DATA2
|-
|ALT5J1.107|HDMI_AUX_P|CPU.HDMI_AUX_P|V1| -|D|connected with capacitor in series||GPIO3_IO21
|-
| rowspan="5" |J1.76109| rowspan="5" |SAI5_RXD1DGND | rowspan="5" |CPU.SAI5_RXD1DGND| rowspan="5" |L4-| rowspan="5" |NVCC_3V3-| rowspan="5" |I/OG| rowspan="5" ||ALT0|SAI5_RX_DATA1
|-
|ALT1J1.111|HDMI_TX_M_LN_3|CPU.HDMI_TX_M_LN_3|M2| -|D|connected with capacitor in series|||-|J1.113|HDMI_TX_P_LN_3|CPU.HDMI_TX_P_LN_3|M1| -|D|connected with capacitor in series||SAI1_TX_DATA3
|-
|ALT2J1.115|HDMI_TX_M_LN_0|CPU.HDMI_TX_M_LN_0|T2| -|D|connected with capacitor in series||SAI1_TX_SYNC
|-
|ALT3J1.117|HDMI_TX_P_LN_0|CPU.HDMI_TX_P_LN_0|T1| -|D|connected with capacitor in series||SAI5_TX_SYNC
|-
|ALT5J1.119|HDMI_TX_M_LN_1|CPU.HDMI_TX_M_LN_1|U1| -|D|connected with capacitor in series||GPIO3_IO212
|-
| rowspan="5" |J1.78121| rowspan="5" |SAI5_RXD2HDMI_TX_P_LN_1| rowspan="5" |CPU.SAI5_RXD2HDMI_TX_P_LN_1| rowspan="5" |M4U2| rowspan="5" |NVCC_3V3-| rowspan="5" |I/OD| rowspan="5" |connected with capacitor in series|ALT0|SAI5_RX_DATA2
|-
|ALT1J1.123|HDMI_TX_M_LN_2|CPU.HDMI_TX_M_LN_2|N1| -|D|connected with capacitor in series||SAI1_TX_DATA4
|-
|ALT2J1.125|HDMI_TX_P_LN_2|CPU.HDMI_TX_P_LN_2|N2| -|D|connected with capacitor in series||SAI1_TX_SYNC
|-
|ALT3J1.127|HDMI_CEC|CPU.HDMI_CEC|W3|VDD_PHY_1V8|I/O|||SAI5_TX_BCLK
|-
|ALT5J1.129|HDMI_HPD|CPU.HDMI_HPD|W2|VDD_PHY_1V8|I/O|||GPIO3_IO23
|-
| rowspan="5" |J1.80| rowspan="5" |SAI5_RXD3| rowspan="5" |CPU.SAI5_RXD3| rowspan="5" |K5| rowspan="5" |NVCC_3V3| rowspan="5" |I/O| rowspan="5" ||ALT0|SAI5_RX_DATA3|-|ALT1|SAI1_TX_DATA5|-|ALT2|SAI1_TX_SYNC|-|ALT3|SAI5_TX_DATA0|-|ALT5|GPIO3_IO24|-|J1.82131|DGND|DGND| -|<nowiki>-</nowiki>
|G
|
|
|-
|J1.84133|CLK2_NLVDS0_CLK_N|CPUBRIDGE.CLK2_NA_CLKN|T22F9|VDDA_1V8-
|D
|
|
|-
|J1.86135|CLK2_PLVDS0_CLK_P|CPUBRIDGE.CLK2_PA_CLKP|U22F8|VDDA_1V8-
|D
|
|
|-
|J1.88137|PCIE1_REF_CLKNLVDS0_TX0_N|CPUBRIDGE.PCIE1_REF_PAD_CLK_NA_Y0N|K24C9|VDD_PHY_3V3-
|D
|
|
|-
|J1.90139|PCIE1_REF_CLKPLVDS0_TX0_P|CPUBRIDGE.PCIE1_REF_PAD_CLK_PA_Y0P|K25C8|VDD_PHY_3V3-
|D
|
|
|-
|J1.92141|PCIE1_RXNLVDS0_TX1_N|CPUBRIDGE.PCIE1_RXN_NA_Y1N|H24D9|VDD_PHY_3V3-
|D
|
|
|-
|J1.94143|PCIE1_RXPLVDS0_TX1_P|CPUBRIDGE.PCIE1_RXN_PA_Y1P|H25D8|VDD_PHY_3V3-
|D
|
|
|-
|J1.96145|PCIE1_TXNLVDS0_TX2_N|CPUBRIDGE.PCIE1_TXN_NA_Y2N|J24E9|VDD_PHY_3V3-
|D
|
|
|-
|J1.98147|PCIE1_TXPLVDS0_TX2_P|CPUBRIDGE.PCIE1_TXN_PA_Y2P|J25E8|VDD_PHY_3V3-|D
|
|
|
|-
|J1.100149|DGNDLVDS0_TX3_N|DGNDBRIDGE.A_Y3N|G9
| -
|<nowiki>-</nowiki>|GD
|
|
|
|-
|J1.102151|CSI1_CLK_NLVDS0_TX3_P|CPUBRIDGE.MIPI_CSI1_CLK_NA_Y3P|A22G8
| -
|D
|
|-
|J1.104153|CSI1_CLK_PDGND |CPU.MIPI_CSI1_CLK_PDGND|B22-
| -
|DG
|
|
|
|-
|J1.106155|CSI1_D0_NLVDS1_CLK_N|CPUBRIDGE.MIPI_CSI1_D0_NB_CLKN|A23A6
| -
|D
|
|-
|J1.108157|CSI1_D0_PLVDS1_CLK_P|CPUBRIDGE.MIPI_CSI1_D0_PB_CLKP|B23B6
| -
|D
|
|-
|J1.110159|CSI1_D1_NLVDS1_TX0_N|CPUBRIDGE.MIPI_CSI1_D1_NB_Y0N|C22A3
| -
|D
|
|-
|J1.112161|CSI1_D1_PLVDS1_TX0_P|CPUBRIDGE.MIPI_CSI1_D1_PB_Y0P|D22B3| -|D||||-|J1.163|LVDS1_TX1_N|BRIDGE.B_Y1N|A4| -|D||||-|J1.165|LVDS1_TX1_P|BRIDGE.B_Y1P|B4
| -
|D
|
|-
|J1.114167|CSI1_D2_NLVDS1_TX2_N|CPUBRIDGE.MIPI_CSI1_D2_NB_Y2N|B24A5
| -
|D
|
|-
|J1.116169|CSI1_D2_PLVDS1_TX2_P|CPUBRIDGE.MIPI_CSI1_D2_PB_Y2P|C23B5
| -
|D
|
|-
|J1.118171|CSI1_D3_NLVDS1_TX3_N|CPUBRIDGE.MIPI_CSI1_D3_NB_Y3N|C21A7
| -
|D
|
|-
|J1.120173|CSI1_D3_PLVDS1_TX3_P|CPUBRIDGE.MIPI_CSI1_D3_PB_Y3P|D21B7
| -
|D
|
|-
|J1.122175|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|-
| rowspan="2" |J1.124177(NAND on board)| rowspan="2" |SD2_CD_B|NAND_DQSrowspan="2" |CPU.NAND_DQSSD2_CD_B|M20rowspan="2" |L21| rowspan="2" |NVCC_3V3| rowspan="2" |I/O|Internally used for NAND, do not connectrowspan="2" ||ALT0|USDHC2_CD_B|-|ALT5|GPIO2_IO12
|-
| rowspan="3" |J1.124(eMMC on board)179| rowspan="3" |NAND_DQSECSPI1_SS0| rowspan="3" |CPU.NAND_DQSECSPI1_SS0| rowspan="3" |M20D4
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|RAWNAND_DQSECSPI1_SS0
|-
|ALT1
|QSPI_A_DQSUART3_RTS_B
|-
|ALT5
|GPIO3_IO14GPIO5_IO09
|-
| rowspan="3" |J1.126181(NAND on board)| rowspan="3" |ECSPI1_SCLK|NAND_ALErowspan="3" |CPU.NAND_ALEECSPI1_SCLK|G19rowspan="3" |D5| rowspan="3" |NVCC_3V3| rowspan="3" |I/O|Internally used for NAND, do not connectrowspan="3" ||ALT0|ECSPI1_SCLK
|-
|ALT1|UART3_RX|-|ALT5|GPIO5_IO06|-| rowspan="3" |J1.126(eMMC on board)183| rowspan="3" |NAND_ALEECSPI1_MISO| rowspan="3" |CPU.NAND_ALEECSPI1_MISO| rowspan="3" |G19B4
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|RAWNAND_ALEECSPI1_MISO
|-
|ALT1
|QSPI_A_SCLKUART3_CTS_B
|-
|ALT5
|GPIO3_IO00GPIO5_IO08
|-
| rowspan="23" |J1.128(NAND on board)185| rowspan="23" |SD1_CLKGPIO1_IO03| rowspan="23" |CPU.SD1_CLKGPIO1_IO03| rowspan="23" |L25P4| rowspan="23" |NVCC_3V3(NVCC_1V8 on request)| rowspan="23" |I/O| rowspan="23" |
|ALT0
|USDHC1_CLKGPIO1_IO03|-|ALT1|USDHC1_VSELECT
|-
|ALT5
|GPIO2_IO00SDMA1_EXT_EVENT0
|-
| rowspan="3" |J1.128(eMMC on board)187| rowspan="3" |NAND_CE0_BUART2_TXD| rowspan="3" |CPU.NAND_CE0_BUART2_TXD| rowspan="3" |H19D6
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |used as default Linux console
|ALT0
|RAWNAND_CE0_BUART2_TX
|-
|ALT1
|QSPI_A_SS0_BECSPI3_SS0
|-
|ALT5
|GPIO3_IO01GPIO5_IO25
|-
| rowspan="23" |J1.130(NAND on board)189| rowspan="23" |SD1_CMDUART2_RXD| rowspan="23" |CPU.SD1_CMDUART2_RXD| rowspan="23" |L24B6| rowspan="23" |NVCC_3V3(NVCC_1V8 on request)| rowspan="23" |I/O| rowspan="23" |used as default Linux console
|ALT0
|USDHC1_CMDUART2_RXD|-|ALT1|ECSPI3_MISO
|-
|ALT5
|GPIO2_IO01GPIO5_IO24
|-
| rowspan="3" |J1.130(eMMC on board)191| rowspan="3" |NAND_CE1_BUART1_TXD| rowspan="3" |CPU.NAND_CE1_BUART1_TXD| rowspan="3" |G21A7
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|RAWNAND_CE1_BUART1_TX
|-
|ALT1
|QSPI_A_SS1_BECSPI3_MOSI
|-
|ALT5
|GPIO3_IO02GPIO5_IO23
|-
| rowspan="23" |J1.132(NAND on board)193| rowspan="23" |SD1_RST_BUART1_RXD| rowspan="23" |CPU.SD1_RST_BUART1_RXD| rowspan="23" |R24C7| rowspan="23" |NVCC_3V3(NVCC_1V8 on request)| rowspan="23" |I/O| rowspan="23" |
|ALT0
|USDHC1_RESET_BUART1_RXD|-|ALT1|ECSPI3_SCLK
|-
|ALT5
|GPIO2_IO10GPIO5_IO22
|-
| rowspan="3" |J1.132(eMMC on board)195| rowspan="3" |NAND_CE2_BECSPI1_MOSI| rowspan="3" |CPU.NAND_CE2_BECSPI1_MOSI| rowspan="3" |F21A4
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|RAWNAND_CE2_BECSPI1_MOSI
|-
|ALT1
|QSPI_B_SS0_BUART3_TX
|-
|ALT5
|GPIO3_IO03GPIO5_IO07
|-
| rowspan="24" |J1.134(NAND on board)197| rowspan="24" |SD1_STROBEGPIO1_IO14| rowspan="24" |CPU.SD1_STROBEGPIO1_IO14| rowspan="24" |T24K7| rowspan="24" |NVCC_3V3(NVCC_1V8 on request)| rowspan="24" |I/O| rowspan="24" |
|ALT0
|USDHC1_STROBEGPIO1_IO14|-|ALT1|USB2_OTG_PWR
|-
|ALT5
|GPIO2_IO11PWM3_OUT|-|ALT6|CCM_CLKO1
|-
| rowspan="3" |J1.134(eMMC on board)199| rowspan="3" |NAND_CE3_BGPIO1_IO04| rowspan="3" |CPU.NAND_CE3_BGPIO1_IO04| rowspan="3" |H20P5
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|RAWNAND_CE3_BGPIO1_IO04
|-
|ALT1
|QSPI_B_SS1_BUSDHC2_VSELECT
|-
|ALT5
|GPIO3_IO034|-|J1.136(NAND on board)|NAND_CLE|CPU.NAND_CLE|H21|NVCC_3V3|I/O|Internally used for NAND, do not connect||SDMA1_EXT_EVENT1
|-
| rowspan="3" |J1.136(eMMC on board)201| rowspan="3" |NAND_CLEGPIO1_IO12| rowspan="3" |CPU.NAND_CLEGPIO1_IO12| rowspan="3" |H21L7
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|RAWNAND_CLEGPIO1_IO12
|-
|ALT1
|QSPI_B_SCLKUSB1_OTG_PWR
|-
|ALT5
|GPIO3_IO05SDMA2_EXT_EVENT1
|-
| rowspan="2" |J1.138(NAND on board)203| rowspan="2" |SD1_DATA0DGND | rowspan="2" |CPU.SD1_DATA0DGND| rowspan="2" |M25-| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)-| rowspan="2" |I/OG| rowspan="2" ||ALT0|USDHC1_DATA0
|-
|ALT5} ==SODIMM J1 EVEN pins declaration == {| class="wikitable" ! latexfontsize="scriptsize" | Pin ! latexfontsize="scriptsize" | Pin Name! latexfontsize="scriptsize" | Internal Connections ! latexfontsize="scriptsize" | Ball/pin # ! latexfontsize="scriptsize" | Voltage domain ! latexfontsize="scriptsize" | Type ! latexfontsize="scriptsize" | Notes! colspan="2" latexfontsize="scriptsize" |GPIO2_IO02Alternative Functions
|-
| rowspan="3" |J1.1382(eMMC on board)| rowspan="3" |NAND_DATA00DGND| rowspan="3" |CPU.NAND_DATA00DGND| rowspan="3" |G20-| rowspan="3" |NVCC_3V3<nowiki>-</nowiki>| rowspan="3" |I/OG| rowspan="3" ||ALT0|RAWNAND_DATA00
|-
|ALT1J1.4|3.3VIN |INPUT VOLTAGE| -|3.3VIN|S|||QSPI_A_DATA0
|-
|ALT5J1.6|3.3VIN |INPUT VOLTAGE| -|3.3VIN|S|||GPIO3_IO06
|-
| rowspan="2" |J1.140(NAND on board)8| rowspan="2" |SD1_DATA13.3VIN | rowspan="2" |CPU.SD1_DATA1INPUT VOLTAGE| rowspan="2" |M24-| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)3.3VIN| rowspan="2" |I/OS| rowspan="2" ||ALT0|USDHC1_DATA1
|-
|ALT5J1.10|3.3VIN |INPUT VOLTAGE| -|3.3VIN|S|||GPIO2_IO0
|-
| rowspan="3" |J1.14012(eMMC on board)| rowspan="3" |NAND_DATA01DGND| rowspan="3" |CPU.NAND_DATA01DGND| rowspan="3" |J20-| rowspan="3" |NVCC_3V3<nowiki>-</nowiki>| rowspan="3" |I/OG| rowspan="3" ||ALT0|RAWNAND_DATA01
|-
|ALT1J1.14|PMIC_LICELL |PMIC.LICELL|30| -|S|||QSPI_A_DATA1
|-
|ALT5J1.16|CPU_ONOFF|CPU.ONOFF|W21|NVCC_SNVS|I|internal pull-up 100k to NVCC_SNVS||GPIO3_IO07
|-
| rowspan="2" |J1.142(NAND on board)18| rowspan="2" |SD1_DATA2BOARD_PGOOD| rowspan="2" |CPU.SD1_DATA2-| rowspan="2" |N25-| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_DATA2
|-
|ALT5J1.20|BOOT_MODE_SEL|BOOT MODE SELECTION| -|NVCC_3V3|I|internal pull-up to NVCC_3V3||GPIO2_IO04
|-
|J1.22|CPU_PORn|CPU.POR_BPMIC.RESETMCU|W203|NVCC_SNVS|I/O|internal pull-up 100k to NVCC_SNVS|||-|J1.24|EXT_RESET|MASTER RESET| -| -|I|internal pull-up to NVCC_SNVS|||-| rowspan="34" |J1.142(eMMC on board)26| rowspan="34" |NAND_DATA02SAI3_RXC| rowspan="34" |CPU.NAND_DATA02SAI3_RXC| rowspan="34" |H22F4| rowspan="34" |NVCC_3V3| rowspan="34" |I/O| rowspan="34" ||ALT0|RAWNAND_DATA02SAI3_RX_BCLK
|-
|ALT1
|QSPI_A_DATA2GPT1_CAPTURE2|-|ALT2|SAI5_RX_BCLK
|-
|ALT5
|GPIO3_IO08GPIO4_IO29
|-
| rowspan="24" |J1.144(NAND on board)28| rowspan="24" |SD1_DATA3GPIO1_IO02| rowspan="24" |CPU.SD1_DATA3GPIO1_IO02| rowspan="24" |P25R4| rowspan="24" |NVCC_3V3(NVCC_1V8 on request)| rowspan="24" |I/O| rowspan="24" |Internally used for SW reset, do not connect
|ALT0
|USDHC1_DATA3|-|ALT5|GPIO2_IO05|-| rowspan="3" |J1.144(eMMC on board)| rowspan="3" |NAND_DATA03| rowspan="3" |CPU.NAND_DATA03| rowspan="3" |J21| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_DATA03GPIO1_IO02
|-
|ALT1
|QSPI_A_DATA3WDOG1_WDOG_B
|-
|ALT5
|GPIO3_IO09WDOG1_WDOG_ANY|-|ALT7|SJC_DE_B
|-
|J1.14630
|DGND
|DGND
|
|-
| rowspan="24" |J1.148(NAND on board)32| rowspan="24" |SD1_DATA4SAI3_RXD| rowspan="24" |CPU.SD1_DATA4SAI3_RXD| rowspan="24" |N24F3| rowspan="24" |NVCC_3V3(NVCC_1V8 on request)| rowspan="24" |I/O| rowspan="24" |
|ALT0
|USDHC1_DATA4SAI3_RX_DATA0|-|ALT1|GPT1_COMPARE1|-|ALT2|SAI5_RX_DATA0
|-
|ALT5
|GPIO2_IO06GPIO4_IO30
|-
| rowspan="3" |J1.148(eMMC on board)34| rowspan="3" |NAND_DATA04SAI2_MCLK| rowspan="3" |CPU.NAND_DATA04SAI2_MCLK| rowspan="3" |L20H5
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|RAWNAND_DATA04SAI2_MCLK
|-
|ALT1
|QSPI_B_DATA0SAI5_MCLK
|-
|ALT5
|GPIO3_IO10GPIO4_IO27
|-
| rowspan="24" |J1.150(NAND on board)36| rowspan="24" |SD1_DATA5SAI3_RXFS| rowspan="24" |CPU.SD1_DATA5SAI3_RXFS| rowspan="24" |P24G4| rowspan="24" |NVCC_3V3(NVCC_1V8 on request)| rowspan="24" |I/O| rowspan="24" |
|ALT0
|USDHC1_DATA5SAI3_RX_SYNC|-|ALT1|GPT1_CAPTURE1|-|ALT2|SAI5_RX_SYNC
|-
|ALT5
|GPIO2_IO07GPIO4_IO28
|-
| rowspan="34" |J1.150(eMMC on board)38| rowspan="34" |NAND_DATA05I2C3_SCL| rowspan="34" |CPU.NAND_DATA05I2C3_SCL| rowspan="34" |J22G8| rowspan="34" |NVCC_3V3| rowspan="34" |I/O| rowspan="34" |
|ALT0
|RAWNAND_DATA05I2C3_SCL
|-
|ALT1
|QSPI_B_DATA1PWM4_OUT|-|ALT2|GPT2_CLK
|-
|ALT5
|GPIO3_IO11GPIO5_IO18
|-
| rowspan="24" |J1.152(NAND on board)40| rowspan="24" |SD1_DATA6SAI3_TXFS| rowspan="24" |CPU.SD1_DATA6SAI3_TXFS| rowspan="24" |R25G3| rowspan="24" |NVCC_3V3(NVCC_1V8 on request)| rowspan="24" |I/O| rowspan="24" |
|ALT0
|USDHC1_DATA6SAI3_TX_SYNC|-|ALT1|GPT1_CLK|-|ALT2|SAI5_RX_DATA1
|-
|ALT5
|GPIO2_IO08GPIO4_IO31
|-
| rowspan="3" |J1.152(eMMC on board)42| rowspan="3" |NAND_DATA06SPDIF_RX| rowspan="3" |CPU.NAND_DATA06SPDIF_RX| rowspan="3" |L19G6
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|RAWNAND_DATA06SPDIF1_IN
|-
|ALT1
|QSPI_B_DATA2PWM2_OUT
|-
|ALT5
|GPIO3_IO12GPIO5_IO04
|-
| rowspan="23" |J1.154(NAND on board)44| rowspan="23" |SD1_DATA7SPDIF_TX| rowspan="23" |CPU.SD1_DATA7SPDIF_TX| rowspan="23" |T25F6| rowspan="23" |NVCC_3V3(NVCC_1V8 on request)| rowspan="23" |I/O| rowspan="23" |
|ALT0
|USDHC1_DATA7SPDIF1_OUT|-|ALT1|PWM3_OUT
|-
|ALT5
|GPIO2_IO09GPIO5_IO03
|-
| rowspan="34" |J1.154(eMMC on board)46| rowspan="34" |NAND_DATA07SAI3_MCLK| rowspan="34" |CPU.NAND_DATA07SAI3_MCLK| rowspan="34" |M19D3| rowspan="34" |NVCC_3V3| rowspan="34" |I/O| rowspan="34" |
|ALT0
|RAWNAND_DATA07SAI3_MCLK
|-
|ALT1
|QSPI_B_DATA3PWM4_OUT|-|ALT2|SAI5_MCLK
|-
|ALT5
|GPIO3_IO13GPIO5_IO02
|-
|J1.156(NAND on board)|NAND_RE_B|CPU.NAND_RE_B|K19|NVCC_3V3|I/O|Internally used for NAND, do not connect|||-| rowspan="34" |J1.156(eMMC on board)48| rowspan="34" |NAND_RE_BI2C3_SDA| rowspan="34" |CPU.NAND_RE_BI2C3_SDA| rowspan="34" |K19E9| rowspan="34" |NVCC_3V3| rowspan="34" |I/O| rowspan="34" |
|ALT0
|RAWNAND_RE_BI2C3_SDA
|-
|ALT1
|QSPI_B_DQSPWM3_OUT|-|ALT2|GPT3_CLK
|-
|ALT5
|GPIO3_IO15GPIO5_IO19
|-
| rowspan="4" |J1.15850(NAND on board)| rowspan="4" |SAI3_TXC|NAND_READY_Browspan="4" |CPU.NAND_READY_BSAI3_TXC|K20rowspan="4" |C4| rowspan="4" |NVCC_3V3| rowspan="4" |I/O|Internally used for NAND, do not connectrowspan="4" ||ALT0|SAI3_TX_BCLK|-|ALT1|GPT1_COMPARE2
|-
| rowspan="2" |J1.158(eMMC on board)| rowspan="2" |NAND_READY_B| rowspan="2" |CPU.NAND_READY_B| rowspan="2" |K20| rowspan="2" |NVCC_3V3| rowspan="2" |I/O| rowspan="2" ||ALT0ALT2|RAWNAND_READY_BSAI5_RX_DATA2
|-
|ALT5
|GPIO3_IO16GPIO5_IO00
|-
| rowspan="4" |J1.16052(NAND on board)| rowspan="4" |SAI3_TXD|NAND_WE_Browspan="4" |CPU.NAND_WE_BSAI3_TXD|K22rowspan="4" |C3| rowspan="4" |NVCC_3V3| rowspan="4" |I/O|Internally used for NAND, do not connectrowspan="4" ||ALT0|SAI3_TX_DATA0|-|ALT1|GPT1_COMPARE3
|-
| rowspan="2" |J1.160(eMMC on board)| rowspan="2" |NAND_WE_B| rowspan="2" |CPU.NAND_WE_B| rowspan="2" |K22| rowspan="2" |NVCC_3V3| rowspan="2" |I/O| rowspan="2" ||ALT0ALT2|RAWNAND_WE_BSAI5_RX_DATA3
|-
|ALT5
|GPIO3_IO17GPIO5_IO01
|-
|J1.162(NAND on board)|NAND_WP_B|CPU.NAND_WP_B|K21|NVCC_3V3|I/O|Internally used for NAND, do not connect|||-| rowspan="2" |J1.162(eMMC on board)54| rowspan="2" |NAND_WP_BGPIO1_IO10| rowspan="2" |CPU.NAND_WP_BGPIO1_IO10| rowspan="2" |K21M7
| rowspan="2" |NVCC_3V3
| rowspan="2" |I/O
| rowspan="2" |Internally used for ETH PHY interrupt, do not connect
|ALT0
|RAWNAND_WP_BGPIO1_IO10
|-
|ALT5ALT1|GPIO3_IO18USB1_OTG_ID
|-
|J1.16456
|DGND
|DGND
|
|-
| rowspan="4" |J1.16658|CLK1_Nrowspan="4" |SAI5_MCLK| rowspan="4" |CPU.CLK1_NSAI5_MCLK|T23rowspan="4" |K4| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|DSAI5_MCLK|-|ALT1|SAI1_TX_BCLK
|-
|J1.168|CLK1_P|CPU.CLK1_P|R23||D||ALT2|SAI4_MCLK
|-
|J1.170|USB2_RXN|CPU.USB2_RX_N|B8||D||ALT5|GPIO3_IO25
|-
| rowspan="4" |J1.17260|USB2_RXProwspan="4" |GPIO1_IO15| rowspan="4" |CPU.USB2_RX_PGPIO1_IO15|A8rowspan="4" |J6| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|DGPIO1_IO15|-|ALT1|USB2_OTG_OC
|-
|J1.174|USB2_TXN|CPU.USB2_TX_N|B9||D||ALT5|PWM4_OUT
|-
|J1.176|USB2_TXP|CPU.USB2_TX_P|A9||D||ALT6|CCM_CLKO2
|-
| rowspan="3" |J1.17862|USB1_RXNrowspan="3" |SAI5_RXFS| rowspan="3" |CPU.USB1_RX_NSAI5_RXFS|B12rowspan="3" |N4|rowspan="3" |NVCC_3V3|Drowspan="3" |I/O| rowspan="3" ||ALT0|SAI5_RX_SYNC
|-
|J1.180|USB1_RXP|CPU.USB1_RX_P|A12||D||ALT1|SAI1_TX_DATA0
|-
|ALT5|GPIO3_IO19|-| rowspan="3" |J1.18264|USB1_TXNrowspan="3" |SAI5_RXC| rowspan="3" |CPU.USB1_TX_NSAI5_RXC|B13rowspan="3" |L5|rowspan="3" |NVCC_3V3|Drowspan="3" |I/O| rowspan="3" ||ALT0|SAI5_RX_BCLK
|-
|J1.184|USB1_TXP|CPU.USB1_TX_P|A13||D||ALT1|SAI1_TX_DATA1
|-
|J1.186|USB1_VBUS|CPU.USB1_VBUS|D14| -|S||ALT5|GPIO3_IO20
|-
| rowspan="3" |J1.18866|USB2_VBUSrowspan="3" |SAI2_TXC| rowspan="3" |CPU.USB2_VBUSSAI2_TXC|D9rowspan="3" |J5| -rowspan="3" |NVCC_3V3|Srowspan="3" |I/O| rowspan="3" ||ALT0|SAI2_TX_BCLK
|-
|J1.190|DGND|DGND| -|<nowiki>-</nowiki>|G||ALT1|SAI5_TX_DATA2
|-
|ALT5|GPIO4_IO25|-| rowspan="3" |J1.19268|USB1_IDrowspan="3" |SAI2_TXD0| rowspan="3" |CPU.USB1_IDSAI2_TXD0|C14rowspan="3" |G5|VDD_PHY_3V3rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|SAI2_TX_DATA0
|-
|J1.194|USB2_ID|CPU.USB2_ID|C9|VDD_PHY_3V3|I||ALT1|SAI5_TX_DATA3
|-
|J1.196|USB1_DN|CPU.USB1_DN|B14| -|D||ALT5|GPIO4_IO26
|-
| rowspan="3" |J1.19870|USB1_DProwspan="3" |SAI2_TXFS| rowspan="3" |CPU.USB1_DPSAI2_TXFS|A14rowspan="3" |H4| -rowspan="3" |NVCC_3V3|Drowspan="3" |I/O| rowspan="3" ||ALT0|SAI2_TX_SYNC
|-
|J1.200|USB2_DP|CPU.USB2_DP|A10| -|D||ALT1|SAI5_TX_DATA1
|-
|ALT5|GPIO4_IO24|-| rowspan="3" |J1.20272|USB2_DNrowspan="3" |SAI2_RXD0| rowspan="3" |CPU.USB2_DNSAI2_RXD0|B10rowspan="3" |H6| -rowspan="3" |NVCC_3V3|Drowspan="3" |I/O| rowspan="3" ||ALT0|SAI2_RX_DATA0
|-
|J1.204|DGND|DGND| -|<nowiki>-</nowiki>|G||ALT1|SAI5_TX_DATA0
|-
|}ALT5 ===Pinout Table J4 pins declaration ==={| class="wikitable" ! latexfontsize="scriptsize" | Pin ! latexfontsize="scriptsize" | Pin Name! latexfontsize="scriptsize" | Internal Connections ! latexfontsize="scriptsize" | Ball/pin # ! latexfontsize="scriptsize" |<nowiki>Voltage|domain</nowiki>! latexfontsize="scriptsize" | Type ! latexfontsize="scriptsize" | Notes! colspan="2" |Alternative FunctionsGPIO4_IO23
|-
|J4.1|DGND|DGND| -|<nowiki>-</nowiki>|G||||-| rowspan="73" |J4J1.274| rowspan="73" |SAI1_RXD7SAI5_RXD0| rowspan="73" |CPU.SAI1_RXD7SAI5_RXD0| rowspan="73" |G1M5| rowspan="73" |NVCC_3V3| rowspan="73" |I/O| rowspan="73" |internally used for BOOT config
|ALT0
|SAI1_RX_DATA7SAI5_RX_DATA0
|-
|ALT1
|SAI6_MCLKSAI1_TX_DATA2
|-
|ALT2ALT5|SAI1_TX_SYNCGPIO3_IO21
|-
|ALT3|SAI1_TX_DATA4|-|ALT4|CORESIGHT_TRACE7|-|ALT5|GPIO4_IO09|-|ALT6|SRC_BOOT_CFG7|-| rowspan="65" |J4J1.376| rowspan="65" |SAI1_RXD6SAI5_RXD1| rowspan="65" |CPU.SAI1_RXD6SAI5_RXD1| rowspan="65" |G2L4| rowspan="65" |NVCC_3V3| rowspan="65" |I/O| rowspan="65" |internally used for BOOT config
|ALT0
|SAI1_RX_DATA6SAI5_RX_DATA1
|-
|ALT1
|SAI6_TX_SYNCSAI1_TX_DATA3
|-
|ALT2
|SAI6_RX_SYNCSAI1_TX_SYNC
|-
|ALT4ALT3|CORESIGHT_TRACE6SAI5_TX_SYNC
|-
|ALT5
|GPIO4_IO08GPIO3_IO212
|-
|ALT6|SRC_BOOT_CFG6|-| rowspan="75" |J4J1.478| rowspan="75" |SAI1_RXD5SAI5_RXD2| rowspan="75" |CPU.SAI1_RXD5SAI5_RXD2| rowspan="75" |F1M4| rowspan="75" |NVCC_3V3| rowspan="75" |I/O| rowspan="75" |internally used for BOOT config
|ALT0
|SAI1_RX_DATA5SAI5_RX_DATA2
|-
|ALT1
|SAI6_TX_DATA0SAI1_TX_DATA4
|-
|ALT2
|SAI6_RX_DATA0SAI1_TX_SYNC
|-
|ALT3
|SAI1_RX_SYNC|-|ALT4|CORESIGHT_TRACE5SAI5_TX_BCLK
|-
|ALT5
|GPIO4_IO07GPIO3_IO23
|-
|ALT6|SRC_BOOT_CFG5|-| rowspan="65" |J4J1.580| rowspan="65" |SAI1_RXD4SAI5_RXD3| rowspan="65" |CPU.SAI1_RXD4SAI5_RXD3| rowspan="65" |J1K5| rowspan="65" |NVCC_3V3| rowspan="65" |I/O| rowspan="65" |internally used for BOOT config
|ALT0
|SAI1_RX_DATA4SAI5_RX_DATA3
|-
|ALT1
|SAI6_TX_BCLKSAI1_TX_DATA5
|-
|ALT2
|SAI6_RX_BCLKSAI1_TX_SYNC
|-
|ALT4ALT3|CORESIGHT_TRACE4SAI5_TX_DATA0
|-
|ALT5
|GPIO4_IO06GPIO3_IO24
|-
|ALT6J1.82|DGND|DGND| -|<nowiki>-</nowiki>|G|||SRC_BOOT_CFG4
|-
| rowspan="5" |J4J1.684| rowspan="5" |SAI1_RXD3CLK2_N| rowspan="5" |CPU.SAI1_RXD3CLK2_N| rowspan="5" |J2T22| rowspan="5" |NVCC_3V3VDDA_1V8| rowspan="5" |I/OD| rowspan="5" |internally Internally used for BOOT configPCIe CLK, do not connect|ALT0|SAI1_RX_DATA3
|-
|ALT1J1.86|CLK2_P|CPU.CLK2_P|U22|VDDA_1V8|D|Internally used for PCIe CLK, do not connect||SAI5_RX_DATA3
|-
|ALT4J1.88|PCIE1_REF_CLKN|CPU.PCIE1_REF_PAD_CLK_N|K24|VDD_PHY_3V3|D|||CORESIGHT_TRACE3
|-
|ALT5J1.90|PCIE1_REF_CLKP|CPU.PCIE1_REF_PAD_CLK_P|K25|VDD_PHY_3V3|D|||GPIO4_IO05
|-
|ALT6J1.92|PCIE1_RXN|CPU.PCIE1_RXN_N|H24|VDD_PHY_3V3|D|||SRC_BOOT_CFG3
|-
| rowspan="5" |J4J1.794| rowspan="5" |SAI1_RXD2PCIE1_RXP| rowspan="5" |CPU.SAI1_RXD2PCIE1_RXN_P| rowspan="5" |H2H25| rowspan="5" |NVCC_3V3VDD_PHY_3V3| rowspan="5" |I/OD| rowspan="5" |internally used for BOOT config|ALT0|SAI1_RX_DATA2
|-
|ALT1J1.96|PCIE1_TXN|CPU.PCIE1_TXN_N|J24|VDD_PHY_3V3|D|||SAI5_RX_DATA2
|-
|ALT4J1.98|PCIE1_TXP|CPU.PCIE1_TXN_P|J25|VDD_PHY_3V3|D|||CORESIGHT_TRACE2
|-
|ALT5J1.100|DGND|DGND| -|<nowiki>-</nowiki>|G|||GPIO4_IO04
|-
|ALT6J1.102|CSI1_CLK_N|CPU.MIPI_CSI1_CLK_N|A22| -|D|||SRC_BOOT_CFG2
|-
| rowspan="5" |J4J1.8104| rowspan="5" |SAI1_RXD1CSI1_CLK_P| rowspan="5" |CPU.SAI1_RXD1MIPI_CSI1_CLK_P| rowspan="5" |L2B22| rowspan="5" |NVCC_3V3-| rowspan="5" |I/OD| rowspan="5" |internally used for BOOT config|ALT0|SAI1_RX_DATA1
|-
|ALT1J1.106|SAI5_RX_DATA1CSI1_D0_N|CPU.MIPI_CSI1_D0_N|A23|-|ALT4D|||CORESIGHT_TRACE1
|-
|ALT5J1.108|CSI1_D0_P|CPU.MIPI_CSI1_D0_P|B23| -|D|||GPIO4_IO03
|-
|ALT6J1.110|CSI1_D1_N|CPU.MIPI_CSI1_D1_N|C22| -|D|||SRC_BOOT_CFG1
|-
| rowspan="5" |J4J1.9112| rowspan="5" |SAI1_RXD0CSI1_D1_P| rowspan="5" |CPU.SAI1_RXD0MIPI_CSI1_D1_P| rowspan="5" |K2D22| rowspan="5" |NVCC_3V3-| rowspan="5" |I/OD| rowspan="5" |internally used for BOOT config|ALT0|SAI1_RX_DATA0
|-
|ALT1J1.114|CSI1_D2_N|CPU.MIPI_CSI1_D2_N|B24| -|D|||SAI5_RX_DATA0
|-
|ALT4J1.116|CSI1_D2_P|CPU.MIPI_CSI1_D2_P|C23| -|D|||CORESIGHT_TRACE0
|-
|ALT5J1.118|GPIO4_IO02CSI1_D3_N|CPU.MIPI_CSI1_D3_N|C21|-|ALT6D|||SRC_BOOT_CFG0
|-
| rowspan="4" |J4J1.10120| rowspan="4" |SAI1_RXCCSI1_D3_P| rowspan="4" |CPU.SAI1_RXCMIPI_CSI1_D3_P| rowspan="4" |K1D21| rowspan="4" |NVCC_3V3-| rowspan="4" |I/OD| rowspan="4" ||ALT0|SAI1_RX_BCLK
|-
|ALT1J1.122|DGND|DGND| -|<nowiki>-</nowiki>|G|||SAI5_RX_BCLK
|-
|ALT4J1.124(NAND on board)|NAND_DQS|CPU.NAND_DQS|M20|NVCC_3V3|I/O|Internally used for NAND, do not connect||CORESIGHT_TRACE_CTL
|-
|ALT5|GPIO4_IO01|-| rowspan="43" |J4J1.11124(eMMC on board)| rowspan="43" |SAI1_RXFSNAND_DQS| rowspan="43" |CPU.SAI1_RXFSNAND_DQS| rowspan="43" |L1M20| rowspan="43" |NVCC_3V3| rowspan="43" |I/O| rowspan="43" |
|ALT0
|SAI1_RX_SYNCRAWNAND_DQS
|-
|ALT1
|SAI5_RX_SYNCQSPI_A_DQS
|-
|ALT4ALT5|CORESIGHT_TRACE_CLKGPIO3_IO14
|-
|ALT5J1.126|GPIO4_IO00(NAND on board)|-NAND_ALE|J4CPU.12|DGNDNAND_ALE|DGNDG19| -NVCC_3V3|<nowiki>-<I/nowiki>|GO|Internally used for NAND, do not connect
|
|
|-
| rowspan="43" |J4J1.13126(eMMC on board)| rowspan="43" |SAI1_MCLKNAND_ALE| rowspan="43" |CPU.SAI1_MCLKNAND_ALE| rowspan="43" |G19| rowspan="43" |NVCC_3V3| rowspan="43" |I/O| rowspan="43" |
|ALT0
|SAI1_MCLKRAWNAND_ALE
|-
|ALT1
|SAI5_MCLK |-|ALT2|SAI1_TX_BCLKQSPI_A_SCLK
|-
|ALT5
|GPIO4_IO20GPIO3_IO00
|-
|J4.14|DGND|DGND| -|<nowiki>-</nowiki>|G||||-| rowspan="42" |J4J1.15128(NAND on board)| rowspan="42" |SAI1_TXFSSD1_CLK| rowspan="42" |CPU.SAI1_TXFSSD1_CLK| rowspan="42" |H4L25| rowspan="42" |NVCC_3V3(NVCC_1V8 on request)| rowspan="42" |I/O| rowspan="42" |
|ALT0
|SAI1_TX_SYNC|-|ALT1|SAI5_TX_SYNC|-|ALT4|CORESIGHT_EVENTOUSDHC1_CLK
|-
|ALT5
|GPIO4_IO10GPIO2_IO00
|-
| rowspan="43" |J4J1.16128(eMMC on board)| rowspan="43" |SAI1_TXCNAND_CE0_B| rowspan="43" |CPU.SAI1_TXCNAND_CE0_B| rowspan="43" |J5H19| rowspan="43" |NVCC_3V3| rowspan="43" |I/O| rowspan="43" |
|ALT0
|SAI1_TX_BCLKRAWNAND_CE0_B
|-
|ALT1
|SAI5_TX_BCLK|-|ALT4|CORESIGHT_EVENTIQSPI_A_SS0_B
|-
|ALT5
|GPIO4_IO11GPIO3_IO01
|-
| rowspan="52" |J4J1.17130(NAND on board)| rowspan="2" |SD1_CMD| rowspan="2" |CPU.SD1_CMD| rowspan="2" |L24| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_CMD|-|ALT5|GPIO2_IO01|-| rowspan="3" |J1.130(eMMC on board)| rowspan="53" |SAI1_TXD0NAND_CE1_B| rowspan="53" |CPU.SAI1_TXD0NAND_CE1_B| rowspan="53" |F2G21| rowspan="53" |NVCC_3V3| rowspan="53" |I/O| rowspan="53" |internally used for BOOT config
|ALT0
|SAI1_TX_DATA0RAWNAND_CE1_B
|-
|ALT1
|SAI5_TX_DATA0|-|ALT4|CORESIGHT_TRACE8QSPI_A_SS1_B
|-
|ALT5
|GPIO4_IO12GPIO3_IO02
|-
|ALT6rowspan="2" |J1.132(NAND on board)| rowspan="2" |SD1_RST_B| rowspan="2" |CPU.SD1_RST_B| rowspan="2" |R24| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_RESET_B|-|ALT5|SRC_BOOT_CFG8GPIO2_IO10
|-
| rowspan="53" |J4J1.18132(eMMC on board)| rowspan="53" |SAI1_TXD1NAND_CE2_B| rowspan="53" |CPU.SAI1_TXD1NAND_CE2_B| rowspan="53" |E2F21| rowspan="53" |NVCC_3V3| rowspan="53" |I/O| rowspan="53" |internally used for BOOT config
|ALT0
|SAI1_TX_DATA1RAWNAND_CE2_B
|-
|ALT1
|SAI5_TX_DATA1|-|ALT4|CORESIGHT_TRACE9QSPI_B_SS0_B
|-
|ALT5
|GPIO4_IO13GPIO3_IO03|-| rowspan="2" |J1.134(NAND on board)| rowspan="2" |SD1_STROBE| rowspan="2" |CPU.SD1_STROBE| rowspan="2" |T24| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_STROBE
|-
|ALT6ALT5|SRC_BOOT_CFG9GPIO2_IO11
|-
| rowspan="53" |J4J1.19134(eMMC on board)| rowspan="53" |SAI1_TXD2NAND_CE3_B| rowspan="53" |CPU.SAI1_TXD2NAND_CE3_B| rowspan="53" |B2H20| rowspan="53" |NVCC_3V3| rowspan="53" |I/O| rowspan="53" |internally used for BOOT config
|ALT0
|SAI1_TX_DATA2RAWNAND_CE3_B
|-
|ALT1
|SAI5_TX_DATA2QSPI_B_SS1_B
|-
|ALT4ALT5|CORESIGHT_TRACE10GPIO3_IO034
|-
|ALT5J1.136(NAND on board)|NAND_CLE|CPU.NAND_CLE|H21|NVCC_3V3|I/O|Internally used for NAND, do not connect||GPIO4_IO14
|-
|ALT6|SRC_BOOT_CFG10|-| rowspan="53" |J4J1.20136(eMMC on board)| rowspan="53" |SAI1_TXD3NAND_CLE| rowspan="53" |CPU.SAI1_TXD3NAND_CLE| rowspan="53" |D1H21| rowspan="53" |NVCC_3V3| rowspan="53" |I/O| rowspan="53" |internally used for BOOT config
|ALT0
|SAI1_TX_DATA3RAWNAND_CLE
|-
|ALT1
|SAI5_TX_DATA3|-|ALT4|CORESIGHT_TRACE11QSPI_B_SCLK
|-
|ALT5
|GPIO4_IO15GPIO3_IO05
|-
|ALT6|SRC_BOOT_CFG11|-| rowspan="62" |J4J1.21138(NAND on board)| rowspan="62" |SAI1_TXD4SD1_DATA0| rowspan="62" |CPU.SAI1_TXD4SD1_DATA0| rowspan="62" |D2M25| rowspan="62" |NVCC_3V3(NVCC_1V8 on request)| rowspan="62" |I/O| rowspan="62" |internally used for BOOT config
|ALT0
|SAI1_TX_DATA4|-|ALT1|SAI6_RX_BCLK|-|ALT2|SAI6_TX_BCLK|-|ALT4|CORESIGHT_TRACE12USDHC1_DATA0
|-
|ALT5
|GPIO4_IO16GPIO2_IO02
|-
|ALT6|SRC_BOOT_CFG12|-| rowspan="63" |J4J1.22138(eMMC on board)| rowspan="63" |SAI1_TXD5NAND_DATA00| rowspan="63" |CPU.SAI1_TXD5NAND_DATA00| rowspan="63" |C2G20| rowspan="63" |NVCC_3V3| rowspan="63" |I/O| rowspan="63" |internally used for BOOT config
|ALT0
|SAI1_TX_DATA5RAWNAND_DATA00
|-
|ALT1
|SAI6_RX_DATA0|-|ALT2|SAI6_TX_DATA0|-|ALT4|CORESIGHT_TRACE13QSPI_A_DATA0
|-
|ALT5
|GPIO4_IO17GPIO3_IO06
|-
|ALT6|SRC_BOOT_CFG13|-| rowspan="62" |J4J1.23140(NAND on board)| rowspan="62" |SAI1_TXD6SD1_DATA1| rowspan="62" |CPU.SAI1_TXD6SD1_DATA1| rowspan="62" |B3M24| rowspan="62" |NVCC_3V3(NVCC_1V8 on request)| rowspan="62" |I/O| rowspan="62" |internally used for BOOT config
|ALT0
|SAI1_TX_DATA6USDHC1_DATA1
|-
|ALT1ALT5|SAI6_RX_SYNCGPIO2_IO0
|-
|ALT2rowspan="3" |J1.140(eMMC on board)| rowspan="3" |NAND_DATA01| rowspan="3" |CPU.NAND_DATA01| rowspan="3" |J20| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|SAI6_TX_SYNCRAWNAND_DATA01
|-
|ALT4ALT1|CORESIGHT_TRACE14QSPI_A_DATA1
|-
|ALT5
|GPIO4_IO18GPIO3_IO07
|-
|ALT6rowspan="2" |J1.142(NAND on board)| rowspan="2" |SD1_DATA2| rowspan="2" |CPU.SD1_DATA2| rowspan="2" |N25| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_DATA2|-|ALT5|SRC_BOOT_CFG14GPIO2_IO04
|-
| rowspan="53" |J4J1.24142(eMMC on board)| rowspan="53" |SAI1_TXD7NAND_DATA02| rowspan="53" |CPU.SAI1_TXD7NAND_DATA02| rowspan="53" |C1H22| rowspan="53" |NVCC_3V3| rowspan="53" |I/O| rowspan="53" |internally used for BOOT config
|ALT0
|SAI1_TX_DATA7RAWNAND_DATA02
|-
|ALT1
|SAI6_MCLK|-|ALT4|CORESIGHT_TRACE15QSPI_A_DATA2
|-
|ALT5
|GPIO4_IO19GPIO3_IO08
|-
|ALT6rowspan="2" |J1.144(NAND on board)| rowspan="2" |SD1_DATA3| rowspan="2" |CPU.SD1_DATA3| rowspan="2" |P25| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" ||ALT0|SRC_BOOT_CFG15USDHC1_DATA3
|-
|J4.25ALT5|DGND|DGND| -|<nowiki>-</nowiki>|G||||}===Pinout Table J5 pins declaration ==={| class="wikitable" ! latexfontsize="scriptsize" | Pin ! latexfontsize="scriptsize" | Pin Name! latexfontsize="scriptsize" | Internal Connections ! latexfontsize="scriptsize" | Ball/pin # ! latexfontsize="scriptsize" |<nowiki>Voltage|domain</nowiki>! latexfontsize="scriptsize" | Type ! latexfontsize="scriptsize" | Notes! colspan="2" |Alternative FunctionsGPIO2_IO05
|-
|J5rowspan="3" |J1.1144(eMMC on board)| rowspan="3" |NAND_DATA03| rowspan="3" |CPU.NAND_DATA03| rowspan="3" |J21| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_DATA03|-|ALT1|QSPI_A_DATA3|-|ALT5|GPIO3_IO09|-|J1.146
|DGND
|DGND
|
|-
|J5rowspan="2" |J1.148(NAND on board)| rowspan="2" |SD1_DATA4|PCIE2_RXNrowspan="2" |CPU.PCIE2_RXN_NSD1_DATA4|D24rowspan="2" |N24| -rowspan="2" |NVCC_3V3(NVCC_1V8 on request)|Drowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_DATA4
|-
|J5.3|PCIE2_RXP|CPU.PCIE2_RXN_P|D25| -|D||ALT5|GPIO2_IO06
|-
|J5rowspan="3" |J1.4148(eMMC on board)| rowspan="3" |DGNDNAND_DATA04|DGNDrowspan="3" |CPU.NAND_DATA04| -rowspan="3" |L20|<nowiki>-<rowspan="3" |NVCC_3V3| rowspan="3" |I/nowiki>O|Growspan="3" ||ALT0|RAWNAND_DATA04
|-
|J5.5|PCIE2_TXN|CPU.PCIE2_TXN_N|E24| -|D||ALT1|QSPI_B_DATA0
|-
|J5.6|PCIE2_TXP|CPU.PCIE2_TXN_P|E25| -|D||ALT5|GPIO3_IO10
|-
|J5rowspan="2" |J1.7150(NAND on board)| rowspan="2" |SD1_DATA5|DGNDrowspan="2" |CPU.SD1_DATA5|DGNDrowspan="2" |P24| -rowspan="2" |NVCC_3V3(NVCC_1V8 on request)|<nowiki>-<rowspan="2" |I/nowiki>O|Growspan="2" ||ALT0|USDHC1_DATA5
|-
|J5.8|PCIE2_REF_CLKN|CPU.PCIE2_REF_PAD_CLK_N|F24| -|D||ALT5|GPIO2_IO07
|-
|J5rowspan="3" |J1.9150(eMMC on board)|PCIE2_REF_CLKProwspan="3" |NAND_DATA05| rowspan="3" |CPU.PCIE2_REF_PAD_CLK_PNAND_DATA05|F25rowspan="3" |J22| -rowspan="3" |NVCC_3V3|Drowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_DATA05
|-
|J5.10|DGND|DGND| -|<nowiki>-</nowiki>|G||ALT1|QSPI_B_DATA1
|-
|J5.11|CSI_P2_CKN|CPU.MIPI_CSI2_CLK_N|A19| -|D||ALT5|GPIO3_IO11
|-
|J5rowspan="2" |J1.12152(NAND on board)|CSI_P2_CKProwspan="2" |SD1_DATA6| rowspan="2" |CPU.MIPI_CSI2_CLK_PSD1_DATA6|B19rowspan="2" |R25| -rowspan="2" |NVCC_3V3(NVCC_1V8 on request)|Drowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_DATA6
|-
|J5.13|DGND|DGND| -|<nowiki>-</nowiki>|G||ALT5|GPIO2_IO08
|-
|J5rowspan="3" |J1.14152(eMMC on board)|CSI_P2_DN0rowspan="3" |NAND_DATA06| rowspan="3" |CPU.MIPI_CSI2_D0_NNAND_DATA06|C20rowspan="3" |L19| -rowspan="3" |NVCC_3V3|Drowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_DATA06
|-
|J5.15|CSI_P2_DP0|CPU.MIPI_CSI2_D0_P|D10| -|D||ALT1|QSPI_B_DATA2
|-
|J5.16|CSI_P2_DN1|CPU.MIPI_CSI2_D1_N|A20| -|D||ALT5|GPIO3_IO12
|-
|J5rowspan="2" |J1.17154(NAND on board)|CSI_P2_DP1rowspan="2" |SD1_DATA7| rowspan="2" |CPU.MIPI_CSI2_D1_PSD1_DATA7|B20rowspan="2" |T25| -rowspan="2" |NVCC_3V3(NVCC_1V8 on request)|Drowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_DATA7
|-
|J5ALT5|GPIO2_IO09|-| rowspan="3" |J1.18154(eMMC on board)| rowspan="3" |NAND_DATA07|DGNDrowspan="3" |CPU.NAND_DATA07|DGNDrowspan="3" |M19| -rowspan="3" |NVCC_3V3|<nowiki>-<rowspan="3" |I/nowiki>O|Growspan="3" ||ALT0|RAWNAND_DATA07
|-
|J5.19|CSI_P2_DN2|CPU.MIPI_CSI2_D2_N|A21| -|D||ALT1|QSPI_B_DATA3
|-
|J5.20|CSI_P2_DP2|CPU.MIPI_CSI2_D2_P|B21| -|D||ALT5|GPIO3_IO13
|-
|J5J1.21156(NAND on board)|CSI_P2_DN3NAND_RE_B|CPU.MIPI_CSI2_D3_NNAND_RE_B|C19K19| -NVCC_3V3|DI/O|Internally used for NAND, do not connect
|
|
|-
|J5.22|CSI_P2_DP3|CPU.MIPI_CSI2_D3_P|D19| -|D||||-|J5.23|DGND|DGND| -|<nowiki>-</nowiki>|G||||-| rowspan="43" |J5J1.24156(eMMC on board)| rowspan="43" |I2C4_SCLNAND_RE_B| rowspan="43" |CPU.I2C4_SCLNAND_RE_B| rowspan="43" |F8K19| rowspan="43" |NVCC_3V3| rowspan="43" |I/O| rowspan="43" |
|ALT0
|I2C4_SCLRAWNAND_RE_B
|-
|ALT1
|PWM2_OUT|-|ALT2|PCIE1_CLKREQ_BQSPI_B_DQS
|-
|ALT5
|GPIO5_IO20GPIO3_IO15
|-
|J1.158(NAND on board)|NAND_READY_B|CPU.NAND_READY_B|K20|NVCC_3V3|I/O|Internally used for NAND, do not connect|||-| rowspan="42" |J5J1.25158(eMMC on board)| rowspan="42" |I2C4_SDANAND_READY_B| rowspan="42" |CPU.I2C4_SDANAND_READY_B| rowspan="42" |F9K20| rowspan="42" |NVCC_3V3| rowspan="42" |I/O| rowspan="42" |
|ALT0
|I2C4_SDARAWNAND_READY_B
|-
|ALT1ALT5|PWM1_OUTGPIO3_IO16
|-
|ALT2|PCIE2_CLKREQ_B|-|ALT5|GPIO5_IO21|} ===Pinout Table JD5 pins declaration ==={| class="wikitable" ! latexfontsize="scriptsize" | Pin ! latexfontsize="scriptsize" | Pin Name! latexfontsize="scriptsize" | Internal Connections ! latexfontsize="scriptsize" | Ball/pin # ! latexfontsize="scriptsize" |<nowiki> Voltage|domain</nowiki>! latexfontsize="scriptsize" | Type ! latexfontsize="scriptsize" | Notes! colspan="2" latexfontsize="scriptsize" | Alternative Functions|-|JD5J1.1|DGND160|DGND(NAND on board)| -NAND_WE_B|<nowiki>-</nowiki>|G||||-|JD5CPU.2|EEPROM_WP|Internal EEPROM Write ProtectNAND_WE_B| -K22
|NVCC_3V3
|I/O|Internally used for NAND, do not connect
|
|
|-
|JD5rowspan="2" |J1.3160(eMMC on board)|NCrowspan="2" |NAND_WE_B|Not Connectedrowspan="2" |CPU.NAND_WE_B| -rowspan="2" |K22| -rowspan="2" |NVCC_3V3|Zrowspan="2" |I/O| rowspan="2" ||ALT0|RAWNAND_WE_B
|-
|JD5.4|JTAG_TCK|CPU.JTAG_TCK|T5|NVCC_3V3|I|internal pull-up 10k to NVCC_3V3|ALT5|GPIO3_IO17
|-
|JD5J1.5162(NAND on board)|JTAG_TMSNAND_WP_B|CPU.JTAG_TMSNAND_WP_B|V5K21
|NVCC_3V3
|I/O|Internally used for NAND, do not connect
|
|
|-
|JD5rowspan="2" |J1.6162(eMMC on board)| rowspan="2" |JTAG_TDONAND_WP_B| rowspan="2" |CPU.JTAG_TDONAND_WP_B|U5rowspan="2" |K21| rowspan="2" |NVCC_3V3|rowspan="2" |I/O|rowspan="2" ||ALT0|RAWNAND_WP_B|-|ALT5|GPIO3_IO18|-|JD5J1.7164|JTAG_TDIDGND|CPU.JTAG_TDIDGND|W5-|NVCC_3V3<nowiki>-</nowiki>|IG
|
|
|
|-
|JD5J1.8166|JTAG_nTRSTCLK1_N|CPU.JTAG_TRST_BCLK1_N|U6T23|NVCC_3V3|ID
|
|
|
|-
|JD5J1.9168|CPU_PORnCLK1_P|CPU.POR_BCLK1_PPMIC|R23||D||||-|J1.170|USB2_RXN|CPU.RESETMCUUSB2_RX_N|B8||W20D3||NVCC_SNVS|I/O|internal pull-up 100k to NVCC_SNVS|J1.172|USB2_RXP|CPU.USB2_RX_P|A8||D|
|
|
|-
|JD5J1.10174|NVCC_3V3USB2_TXN|NVCC_3V3CPU.USB2_TX_N| -B9|<nowiki>-</nowiki>|SD
|
|
|
|-
|J1.176
|USB2_TXP
|CPU.USB2_TX_P
|A9
|
|D
|
|
|
|-
|J1.178
|USB1_RXN
|CPU.USB1_RX_N
|B12
|
|D
|
|
|
|-
|J1.180
|USB1_RXP
|CPU.USB1_RX_P
|A12
|
|D
|
|
|
|-
|J1.182
|USB1_TXN
|CPU.USB1_TX_N
|B13
|
|D
|
|
|
|-
|J1.184
|USB1_TXP
|CPU.USB1_TX_P
|A13
|
|D
|
|
|
|-
|J1.186
|USB1_VBUS
|CPU.USB1_VBUS
|D14
| -
|S
|Absolute maximum ratings 5.25V
|
|
|-
|J1.188
|USB2_VBUS
|CPU.USB2_VBUS
|D9
| -
|S
|Absolute maximum ratings 5.25V
|
|
|-
|J1.190
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
|J1.192
|USB1_ID
|CPU.USB1_ID
|C14
|VDD_PHY_3V3
|I
|
|
|
|-
|J1.194
|USB2_ID
|CPU.USB2_ID
|C9
|VDD_PHY_3V3
|I
|
|
|
|-
|J1.196
|USB1_DN
|CPU.USB1_DN
|B14
| -
|D
|
|
|
|-
|J1.198
|USB1_DP
|CPU.USB1_DP
|A14
| -
|D
|
|
|
|-
|J1.200
|USB2_DP
|CPU.USB2_DP
|A10
| -
|D
|
|
|
|-
|J1.202
|USB2_DN
|CPU.USB2_DN
|B10
| -
|D
|
|
|
|-
|J1.204
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
|}
 
==ONE PIECE J4 pins declaration ==
{| class="wikitable"
! latexfontsize="scriptsize" | Pin
! latexfontsize="scriptsize" | Pin Name
! latexfontsize="scriptsize" | Internal Connections
! latexfontsize="scriptsize" | Ball/pin #
! latexfontsize="scriptsize" | Voltage domain
! latexfontsize="scriptsize" | Type
! latexfontsize="scriptsize" | Notes
! colspan="2" |Alternative Functions
|-
|J4.1
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
| rowspan="7" |J4.2
| rowspan="7" |SAI1_RXD7
| rowspan="7" |CPU.SAI1_RXD7
| rowspan="7" |G1
| rowspan="7" |NVCC_3V3
| rowspan="7" |I/O
| rowspan="7" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_RX_DATA7
|-
|ALT1
|SAI6_MCLK
|-
|ALT2
|SAI1_TX_SYNC
|-
|ALT3
|SAI1_TX_DATA4
|-
|ALT4
|CORESIGHT_TRACE7
|-
|ALT5
|GPIO4_IO09
|-
|ALT6
|SRC_BOOT_CFG7
|-
| rowspan="6" |J4.3
| rowspan="6" |SAI1_RXD6
| rowspan="6" |CPU.SAI1_RXD6
| rowspan="6" |G2
| rowspan="6" |NVCC_3V3
| rowspan="6" |I/O
| rowspan="6" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_RX_DATA6
|-
|ALT1
|SAI6_TX_SYNC
|-
|ALT2
|SAI6_RX_SYNC
|-
|ALT4
|CORESIGHT_TRACE6
|-
|ALT5
|GPIO4_IO08
|-
|ALT6
|SRC_BOOT_CFG6
|-
| rowspan="7" |J4.4
| rowspan="7" |SAI1_RXD5
| rowspan="7" |CPU.SAI1_RXD5
| rowspan="7" |F1
| rowspan="7" |NVCC_3V3
| rowspan="7" |I/O
| rowspan="7" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_RX_DATA5
|-
|ALT1
|SAI6_TX_DATA0
|-
|ALT2
|SAI6_RX_DATA0
|-
|ALT3
|SAI1_RX_SYNC
|-
|ALT4
|CORESIGHT_TRACE5
|-
|ALT5
|GPIO4_IO07
|-
|ALT6
|SRC_BOOT_CFG5
|-
| rowspan="6" |J4.5
| rowspan="6" |SAI1_RXD4
| rowspan="6" |CPU.SAI1_RXD4
| rowspan="6" |J1
| rowspan="6" |NVCC_3V3
| rowspan="6" |I/O
| rowspan="6" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_RX_DATA4
|-
|ALT1
|SAI6_TX_BCLK
|-
|ALT2
|SAI6_RX_BCLK
|-
|ALT4
|CORESIGHT_TRACE4
|-
|ALT5
|GPIO4_IO06
|-
|ALT6
|SRC_BOOT_CFG4
|-
| rowspan="5" |J4.6
| rowspan="5" |SAI1_RXD3
| rowspan="5" |CPU.SAI1_RXD3
| rowspan="5" |J2
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_RX_DATA3
|-
|ALT1
|SAI5_RX_DATA3
|-
|ALT4
|CORESIGHT_TRACE3
|-
|ALT5
|GPIO4_IO05
|-
|ALT6
|SRC_BOOT_CFG3
|-
| rowspan="5" |J4.7
| rowspan="5" |SAI1_RXD2
| rowspan="5" |CPU.SAI1_RXD2
| rowspan="5" |H2
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_RX_DATA2
|-
|ALT1
|SAI5_RX_DATA2
|-
|ALT4
|CORESIGHT_TRACE2
|-
|ALT5
|GPIO4_IO04
|-
|ALT6
|SRC_BOOT_CFG2
|-
| rowspan="5" |J4.8
| rowspan="5" |SAI1_RXD1
| rowspan="5" |CPU.SAI1_RXD1
| rowspan="5" |L2
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_RX_DATA1
|-
|ALT1
|SAI5_RX_DATA1
|-
|ALT4
|CORESIGHT_TRACE1
|-
|ALT5
|GPIO4_IO03
|-
|ALT6
|SRC_BOOT_CFG1
|-
| rowspan="5" |J4.9
| rowspan="5" |SAI1_RXD0
| rowspan="5" |CPU.SAI1_RXD0
| rowspan="5" |K2
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_RX_DATA0
|-
|ALT1
|SAI5_RX_DATA0
|-
|ALT4
|CORESIGHT_TRACE0
|-
|ALT5
|GPIO4_IO02
|-
|ALT6
|SRC_BOOT_CFG0
|-
| rowspan="4" |J4.10
| rowspan="4" |SAI1_RXC
| rowspan="4" |CPU.SAI1_RXC
| rowspan="4" |K1
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |
|ALT0
|SAI1_RX_BCLK
|-
|ALT1
|SAI5_RX_BCLK
|-
|ALT4
|CORESIGHT_TRACE_CTL
|-
|ALT5
|GPIO4_IO01
|-
| rowspan="4" |J4.11
| rowspan="4" |SAI1_RXFS
| rowspan="4" |CPU.SAI1_RXFS
| rowspan="4" |L1
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |
|ALT0
|SAI1_RX_SYNC
|-
|ALT1
|SAI5_RX_SYNC
|-
|ALT4
|CORESIGHT_TRACE_CLK
|-
|ALT5
|GPIO4_IO00
|-
|J4.12
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
| rowspan="4" |J4.13
| rowspan="4" |SAI1_MCLK
| rowspan="4" |CPU.SAI1_MCLK
| rowspan="4" |
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |
|ALT0
|SAI1_MCLK
|-
|ALT1
|SAI5_MCLK
|-
|ALT2
|SAI1_TX_BCLK
|-
|ALT5
|GPIO4_IO20
|-
|J4.14
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
| rowspan="4" |J4.15
| rowspan="4" |SAI1_TXFS
| rowspan="4" |CPU.SAI1_TXFS
| rowspan="4" |H4
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |
|ALT0
|SAI1_TX_SYNC
|-
|ALT1
|SAI5_TX_SYNC
|-
|ALT4
|CORESIGHT_EVENTO
|-
|ALT5
|GPIO4_IO10
|-
| rowspan="4" |J4.16
| rowspan="4" |SAI1_TXC
| rowspan="4" |CPU.SAI1_TXC
| rowspan="4" |J5
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |
|ALT0
|SAI1_TX_BCLK
|-
|ALT1
|SAI5_TX_BCLK
|-
|ALT4
|CORESIGHT_EVENTI
|-
|ALT5
|GPIO4_IO11
|-
| rowspan="5" |J4.17
| rowspan="5" |SAI1_TXD0
| rowspan="5" |CPU.SAI1_TXD0
| rowspan="5" |F2
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_TX_DATA0
|-
|ALT1
|SAI5_TX_DATA0
|-
|ALT4
|CORESIGHT_TRACE8
|-
|ALT5
|GPIO4_IO12
|-
|ALT6
|SRC_BOOT_CFG8
|-
| rowspan="5" |J4.18
| rowspan="5" |SAI1_TXD1
| rowspan="5" |CPU.SAI1_TXD1
| rowspan="5" |E2
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_TX_DATA1
|-
|ALT1
|SAI5_TX_DATA1
|-
|ALT4
|CORESIGHT_TRACE9
|-
|ALT5
|GPIO4_IO13
|-
|ALT6
|SRC_BOOT_CFG9
|-
| rowspan="5" |J4.19
| rowspan="5" |SAI1_TXD2
| rowspan="5" |CPU.SAI1_TXD2
| rowspan="5" |B2
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_TX_DATA2
|-
|ALT1
|SAI5_TX_DATA2
|-
|ALT4
|CORESIGHT_TRACE10
|-
|ALT5
|GPIO4_IO14
|-
|ALT6
|SRC_BOOT_CFG10
|-
| rowspan="5" |J4.20
| rowspan="5" |SAI1_TXD3
| rowspan="5" |CPU.SAI1_TXD3
| rowspan="5" |D1
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_TX_DATA3
|-
|ALT1
|SAI5_TX_DATA3
|-
|ALT4
|CORESIGHT_TRACE11
|-
|ALT5
|GPIO4_IO15
|-
|ALT6
|SRC_BOOT_CFG11
|-
| rowspan="6" |J4.21
| rowspan="6" |SAI1_TXD4
| rowspan="6" |CPU.SAI1_TXD4
| rowspan="6" |D2
| rowspan="6" |NVCC_3V3
| rowspan="6" |I/O
| rowspan="6" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_TX_DATA4
|-
|ALT1
|SAI6_RX_BCLK
|-
|ALT2
|SAI6_TX_BCLK
|-
|ALT4
|CORESIGHT_TRACE12
|-
|ALT5
|GPIO4_IO16
|-
|ALT6
|SRC_BOOT_CFG12
|-
| rowspan="6" |J4.22
| rowspan="6" |SAI1_TXD5
| rowspan="6" |CPU.SAI1_TXD5
| rowspan="6" |C2
| rowspan="6" |NVCC_3V3
| rowspan="6" |I/O
| rowspan="6" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_TX_DATA5
|-
|ALT1
|SAI6_RX_DATA0
|-
|ALT2
|SAI6_TX_DATA0
|-
|ALT4
|CORESIGHT_TRACE13
|-
|ALT5
|GPIO4_IO17
|-
|ALT6
|SRC_BOOT_CFG13
|-
| rowspan="6" |J4.23
| rowspan="6" |SAI1_TXD6
| rowspan="6" |CPU.SAI1_TXD6
| rowspan="6" |B3
| rowspan="6" |NVCC_3V3
| rowspan="6" |I/O
| rowspan="6" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_TX_DATA6
|-
|ALT1
|SAI6_RX_SYNC
|-
|ALT2
|SAI6_TX_SYNC
|-
|ALT4
|CORESIGHT_TRACE14
|-
|ALT5
|GPIO4_IO18
|-
|ALT6
|SRC_BOOT_CFG14
|-
| rowspan="5" |J4.24
| rowspan="5" |SAI1_TXD7
| rowspan="5" |CPU.SAI1_TXD7
| rowspan="5" |C1
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_TX_DATA7
|-
|ALT1
|SAI6_MCLK
|-
|ALT4
|CORESIGHT_TRACE15
|-
|ALT5
|GPIO4_IO19
|-
|ALT6
|SRC_BOOT_CFG15
|-
|J4.25
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|}
 
==ONE PIECE J5 pins declaration ==
{| class="wikitable"
! latexfontsize="scriptsize" | Pin
! latexfontsize="scriptsize" | Pin Name
! latexfontsize="scriptsize" | Internal Connections
! latexfontsize="scriptsize" | Ball/pin #
! latexfontsize="scriptsize" | Voltage domain
! latexfontsize="scriptsize" | Type
! latexfontsize="scriptsize" | Notes
! colspan="2" |Alternative Functions
|-
|J5.1
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
|J5.2
|PCIE2_RXN
|CPU.PCIE2_RXN_N
|D24
| -
|D
|
|
|
|-
|J5.3
|PCIE2_RXP
|CPU.PCIE2_RXN_P
|D25
| -
|D
|
|
|
|-
|J5.4
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
|J5.5
|PCIE2_TXN
|CPU.PCIE2_TXN_N
|E24
| -
|D
|
|
|
|-
|J5.6
|PCIE2_TXP
|CPU.PCIE2_TXN_P
|E25
| -
|D
|
|
|
|-
|J5.7
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
|J5.8
|PCIE2_REF_CLKN
|CPU.PCIE2_REF_PAD_CLK_N
|F24
| -
|D
|
|
|
|-
|J5.9
|PCIE2_REF_CLKP
|CPU.PCIE2_REF_PAD_CLK_P
|F25
| -
|D
|
|
|
|-
|J5.10
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
|J5.11
|CSI_P2_CKN
|CPU.MIPI_CSI2_CLK_N
|A19
| -
|D
|
|
|
|-
|J5.12
|CSI_P2_CKP
|CPU.MIPI_CSI2_CLK_P
|B19
| -
|D
|
|
|
|-
|J5.13
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
|J5.14
|CSI_P2_DN0
|CPU.MIPI_CSI2_D0_N
|C20
| -
|D
|
|
|
|-
|J5.15
|CSI_P2_DP0
|CPU.MIPI_CSI2_D0_P
|D10
| -
|D
|
|
|
|-
|J5.16
|CSI_P2_DN1
|CPU.MIPI_CSI2_D1_N
|A20
| -
|D
|
|
|
|-
|J5.17
|CSI_P2_DP1
|CPU.MIPI_CSI2_D1_P
|B20
| -
|D
|
|
|
|-
|J5.18
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
|J5.19
|CSI_P2_DN2
|CPU.MIPI_CSI2_D2_N
|A21
| -
|D
|
|
|
|-
|J5.20
|CSI_P2_DP2
|CPU.MIPI_CSI2_D2_P
|B21
| -
|D
|
|
|
|-
|J5.21
|CSI_P2_DN3
|CPU.MIPI_CSI2_D3_N
|C19
| -
|D
|
|
|
|-
|J5.22
|CSI_P2_DP3
|CPU.MIPI_CSI2_D3_P
|D19
| -
|D
|
|
|
|-
|J5.23
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
| rowspan="4" |J5.24
| rowspan="4" |I2C4_SCL
| rowspan="4" |CPU.I2C4_SCL
| rowspan="4" |F8
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |
|ALT0
|I2C4_SCL
|-
|ALT1
|PWM2_OUT
|-
|ALT2
|PCIE1_CLKREQ_B
|-
|ALT5
|GPIO5_IO20
|-
| rowspan="4" |J5.25
| rowspan="4" |I2C4_SDA
| rowspan="4" |CPU.I2C4_SDA
| rowspan="4" |F9
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |
|ALT0
|I2C4_SDA
|-
|ALT1
|PWM1_OUT
|-
|ALT2
|PCIE2_CLKREQ_B
|-
|ALT5
|GPIO5_IO21
|}
U0007
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